JP2012023471A - Interface circuit and electronic apparatus using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit area of an interface circuit having a plurality of ports.SOLUTION: An interface circuit 100 receives, at a plurality of ports, an encrypted data stream from a plurality of external apparatus, and outputs the encrypted data stream input to an active port while decrypting. A first computing module 30 establishes a link between each of a plurality of the external apparatus, and computes data required for maintaining it. A second computing module 32 receives data corresponding to the active port out of the data obtained by computation of the first computing module 30, and generates a release code required for deciphering the data stream input to the active port. A decryption module 40 decrypts the data stream S1 input to the active port by using the release code S2 output from the second computing module 32.

Description

  The present invention relates to an interface circuit for decrypting encrypted data.

  Multimedia devices such as televisions and AV amplifiers are equipped with a multi-channel input interface and selector, and a plurality of devices can be connected, and a data stream from a device connected to one channel selected by the selector Can be processed.

  In recent years, high-definition multimedia interface (HDMI) standards, digital visual interface (DVI) standards, and the like have become widespread as interfaces for such multimedia devices. In the HDMI standard and the DVI standard, after connected devices mutually authenticate each other, a data stream such as video and audio is encrypted and transmitted.

WO09 / 108818 Pamphlet JP 2001-127754 A JP 2007-89013 A

  Patent Document 1 discloses a circuit configuration that receives an encrypted data stream from a plurality of external devices (source devices), and selects and outputs one of them. In this technique, as shown in FIG. 2, an HDCP (High-bandwidth Digital Content Protection) engine (104, 106, 108, 109) is provided for each source device. Of the decoding codes (Cipher outputs) generated by each HDCP engine, one corresponding to the active port is selected by the multiplexer (102). The decryption engine (De-cipher Engine 256) decrypts (decrypts) the video data and packet data of the active port using the selected data for decryption.

  In Patent Document 1, since an HDCP engine is required for each input port, the hardware scale increases as the number of ports increases.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an aspect thereof is to reduce a circuit area of an interface circuit having a plurality of ports.

  An embodiment of the present invention relates to an interface circuit that receives encrypted data streams from a plurality of external devices at a plurality of ports, and outputs the data streams input to an active port after being decrypted. The interface circuit establishes a link with each of a plurality of external devices, the first arithmetic module that calculates data necessary to maintain the link, and active data among the data obtained by the operation of the first arithmetic module A second arithmetic module that receives data corresponding to the port and generates a release code necessary for decoding the data stream input to the active port, and outputs the data stream input to the active port from the second arithmetic module And a decryption module that decrypts using the release code.

  According to this aspect, the first arithmetic module can continue to maintain the link with each external device, and the data stream of the active port can be decoded in parallel therewith. Even if the number of ports is increased, it is not necessary to increase the number of modules, so that an increase in circuit area can be suppressed.

  Another embodiment of the present invention is an electronic device. This electronic apparatus includes the above-described interface circuit.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the circuit area of an interface circuit having a plurality of ports can be reduced.

It is a block diagram which shows the structure of an electronic device provided with the interface circuit which concerns on embodiment. It is a block diagram which shows the structure of a 1st arithmetic module. FIGS. 3A and 3B are time charts showing the operation of the interface circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a block diagram illustrating a configuration of an electronic device 1 including an interface circuit 100 according to an embodiment. Examples of the electronic device 1 include multimedia devices such as a television having a plurality of input ports, a PC display, an AV amplifier, and a digital video recorder, but the application of the interface circuit 100 is not particularly limited. For example, the electronic device 1 may be an HDMI selector. In the present embodiment, description will be made assuming that electronic device 1 is a display device.

  The electronic device 1 is connected to an external device (not shown) via a multimedia interface, receives video data and audio data from the external device, and displays and reproduces them. Examples of the multimedia interface include HDMI standard, DVI standard, display port standard, VGA standard and the like. However, interface standards are not limited to these, and may be various known or proposed standards that require authentication prior to data transmission.

  In the following, for the purpose of facilitating understanding, the interface circuit 100 conforming to the HDMI standard is assumed and described.

The electronic device 1 is provided with a plurality of connectors _CN A -CN _D, external device is detachably connected, respectively. The number of connectors CN is not particularly limited, but the present invention is particularly meaningful when the number is 3 or more. The electronic device 1 displays video data (image data) from an external device connected to one connector (port) selected by the user. In this specification, a port to be processed by the electronic device 1 is referred to as an active port, and the other ports are referred to as inactive ports.

  The electronic device 1 includes a display panel 2, a panel driving unit 4, a DSP 6, and an interface circuit 100.

The interface circuit 100 receives a data stream from an external device to be input to the plurality of connectors CN _A -CN _D, select the data stream from an external device connected to set the connector CN to the active port, the The cipher is released and output from the output port P _OUT .

The DSP 6 performs predetermined signal processing on the output data D _OUT from the interface circuit 100 and outputs it to the panel drive unit 4. The panel driving unit 4 drives the display panel 2 based on the output data D _OUT.

  The above is the overall configuration of the electronic device 1. Next, the interface circuit 100 according to the embodiment will be described in detail.

  The multimedia interface described above requires authentication prior to data transmission. The interface circuit 100 transmits / receives data to / from an external device and performs authentication processing.

  In the HDMI standard, a system is composed of a source device, a sink device, and a cable. In the present embodiment, the electronic device 1 corresponds to a sink device, and the external device corresponds to a source device. Video data and audio data from the source device to the sink device are transmitted by the TMDS (Transition Minimized Differential Signaling) method. The source device and the sink device perform authentication processing after transmitting / receiving information (display data) such as the manufacturer, model number, and resolution of the display via a DDC (Display. Data Channel) line.

  In the HDCP standard, first, a source device and a sink device are authenticated by “Authentication First Part” (hereinafter referred to as “first authentication”), and a link is established. Specifically, an authentication request is issued from the source device to the sink device, and data necessary for authentication is transmitted and received between the sink device and the source device. If link establishment fails, the source device issues an authentication request to the link device again after a predetermined time.

  Once the link is established between the source device and the sink device, the link is maintained by “Authentication Third Part (hereinafter referred to as third authentication)”. Specifically, the source device outputs a synchronization signal (encryption enable: notification that it is an encrypted frame) ENC_EN synchronized with the frame to the sink device, and links to the sink device every 128 frames in a predetermined cycle. Confirm. The sink device responds to the link confirmation from the source device using the already received synchronization signal ENC_EN.

The interface circuit 100 includes a plurality of input ports _P1 A to P1 _D, a plurality of authentication port _P2 A to P2 _D, the selector 10, the decoder 12, DDC interface unit 14, decryption unit 20, decoding module 40, an output interface unit 42 Prepare.

Data streams from the plurality of external devices are input to the plurality of input ports P1 _{A to} P1 _D , respectively. The data stream includes video data, audio data, and the like. The multiple authentication ports _P2 A to P2 _D respectively, are connected to the DDC line of the corresponding HDMI cable. A signal necessary for authentication with each external device (source device) is transmitted / received via the authentication port P2. A transmission protocol via the DDC line is based on an I ² C (Inter IC) bus. In the HDMI standard, a CEC (Consumer Electronics Control) line is used in addition to the DDC line and the TMDS line, but is omitted here.

The selector 10 selects and outputs a data stream input to one of the plurality of input ports P1 _{A to} P1 _D set as an active port.

The decoder 12 receives the data stream D _ACT of the active port output from the selector 10 and extracts the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, video data, packet data, ENC_EN data, and ENC_DIS data.

  The descrambling unit 20 includes a register 22, a multiport control unit 24, and a cancellation code generation unit 26.

  The multiport control unit 24 performs processing related to switching of a plurality of ports. Data indicating an active port is input to a multiport control unit (Multiport Control Engine) 24. The multiport control unit 24 causes the selector 10 to select the data stream of the active port. In addition, the multiport control unit 24 controls the release code generation unit 26 to execute necessary arithmetic processing according to each port. The register 22, the multiport controller 24, and the release code generator 26 are connected via a bus 28.

Decryption unit 20 establishes the link between the plurality of external devices, the necessary code to maintain: to generate a (hdcpBlockCipher _{r i),} release needed to decrypt the data stream active port Generate code (hdcpStreamCipher and hdcpRekeyCipher).

The descrambling unit 20 roughly classifies and executes the following three arithmetic processes.
1. hdcpBlockCipher
In the first authentication (Authentication First Part), a session key Ks is generated, and in the third authentication (Authentication Third Part), a frame key Ki is generated for each synchronization signal ENC_EN, that is, for each frame.
2. hdcpStreamCipher
For the video data and packet data, a release code S2 to be input to the decoding module 40 is generated for each pixel.
3. hdcpRekeyCipher
After receiving one line of video data, Rekey data is generated.

The descrambling unit 20 includes a first arithmetic module 30 and a second arithmetic module 32.
The first calculation module 30 executes calculation processing related to hdcpBlockCipher for each port for each port, and generates a session key Ks and a frame key Ki. For each port, the session key Ks and the frame key Ki generated for each frame are stored in the register 22.
The code r _i ′ is generated every 128 frames by the frame key Ki of each port, accessed by the source device of that port, and used for maintaining authentication.
In addition, the first calculation module 30 outputs a parameter S3, which is a parameter generated during the calculation process for the active port and is necessary for the calculation process related to hdcpStreamCipher and hdcpRekeyCipher, to the second calculation module 32.

  The second calculation module 32 receives the parameter S3 from the first calculation module 30 for each frame of the active port, performs calculation related to hdcpStreamCipher for each pixel of the active port, and executes calculation processing related to hdcpRekeyCipher for each line of the active port To do.

  That is, the first calculation module 30 and the second calculation module 32 have different operation speeds. Specifically, the first arithmetic module 30 operates at 133 MHz, and the second arithmetic module 32 operates at the same speed as the pixel clock of the active port.

  Since the contents of the arithmetic processing in the first arithmetic module 30 and the second arithmetic module 32 are the same, the first arithmetic module 30 and the second arithmetic module 32 are similarly configured. FIG. 2 is a block diagram showing a configuration of the first arithmetic module 30. The second calculation module 32 is also configured similarly to the first calculation module 30 of FIG.

The first arithmetic module 30 includes an LFSR module 50, a block module 52, and an output function 54.
Processing of the first calculation module 30 will be described. i is a variable incremented for each frame. The first arithmetic module 30 executes the following process every time the synchronization signal ENC_EN is asserted for each port.
1-a) Initial values are loaded into the B and K registers of the block module 52.
1-b) 48 clocks are supplied to the block module 52.
1-c) A new frame key Ki [83: 0] is generated in the B register of the block module 52.
1-d) A new frame key Ki [83: 0] is assigned to the K register of the block module 52.
1-e) REPEATER || M _i-1 is assigned to the B register of the block module 52.
1-f) The LFSR module 50 is initialized with a new frame key Ki [55: 0].
1-g) Rekey is enabled, and 56 clocks are supplied to the LFSR module 50 and the block module 52. In the output function 54, the code Mi is generated in the last four clocks, and r _i ′ is generated in the last two clocks, and these are held.
1-h) Rekey is disabled.

  In the case of an active port, the first arithmetic module 30 outputs the values of all the nodes in the LFSR module 50 and the values of the B register and the K register of the block module 52 to the corresponding block of the second arithmetic module 32. . These values correspond to the parameter S3 described above.

Next, the processing of the second arithmetic module 32 will be described with reference to FIG.
The second calculation module 32 receives the parameter S3 from the first calculation module 30 with respect to the active port, and performs calculations related to hdcpStreamCipher and hdcpRekeyCipher. Specifically, the following processing is performed.
2-a) A signal ENC_EN indicating that the next frame is an HDCP encrypted data stream is provided from the decoder 12.
2-b) The parameter S3, specifically the values of all nodes in the LFSR module 50, and the values of the B register and K register in the block module 52 are received from the first calculation module 30, and are received as the second calculation module. Copy to the corresponding block in 32.
2-c) When video data or packet data is input, the LFSR module 50 and the block module 52 are operated with a pixel clock, and the output function 54 generates the release code S2 which is pseudo random data of 24 bits. Output to 40.

  The above is the configuration of the cancellation code generation unit 26.

  Returning to FIG. The decryption module 40 decrypts the encrypted video data or packet data (data stream) S1 from the decoder 12 by using the decryption code S2 from the descrambling unit 20. The decryption module 40 calculates an exclusive OR (ExOR) of the data stream S1 and the release code S2, and decrypts the data stream S1.

The data S4 decrypted by the decryption module 40 is serialized by the output interface unit 42 and output from the output terminal P _OUT .

The above is the configuration of the interface circuit 100.
Next, the operation will be described. 3A and 3B are time charts showing the operation of the interface circuit 100 of FIG.
In each port to D, each time the vertical synchronization signal VSYNC is asserted, the first calculation module 30 performs calculation processing related HdcpBlockCipher, it calculates the data _{r i.} Every 128 frames, the data r _i is accessed from the source device via the DDC interface unit 14 and used for maintaining the link. In the figure, data used for link maintenance is hatched.

FIG. 3B shows a time chart related to the active port. Each time the vertical synchronization signal VSYNC is asserted, the first arithmetic module 30 executes an operation B related to hdcpBlockCipher to calculate data r _i . The parameter S3 obtained at that time is passed to the second arithmetic module 32. The second calculation module 32 inherits the parameter S3 and executes the calculation S related to hdcpStreamCipher with a pixel clock during the data interval. Further, the calculation R related to hdcpRekeyCipher is executed during the blank period after one line of video data.

The above is the operation of the interface circuit 100.
According to the interface circuit 100, by providing a module (first calculation module 30) that performs calculation processing for each frame for all ports and a module (second calculation module 32) that performs calculation for each pixel for active ports. The encrypted data stream of the active port can be decrypted while establishing and maintaining links with all ports.

The advantages of the interface circuit 100 according to the embodiment are clarified by comparison with the technique of Patent Document 1. In the technique described in Patent Document 1, an arithmetic module (engine) is provided for each port, and the arithmetic module of each port executes arithmetic processing related to all hdcpBlockCipher, hdcpStreamCipher, and hdcpRekeyCipher. Therefore, the number of arithmetic modules proportional to the number of ports is required.
On the other hand, according to the interface circuit 100 according to the embodiment, even if the number of ports increases, the number of operation modules is sufficient, so that the circuit area can be greatly reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

In the embodiment, the case where there is one output port P _OUT has been described. However, the present invention is not limited to this, and a plurality of output ports P _OUT may be provided. In this case, a decoder 12 and a selector 10 may be provided for each output port.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, P1 ... Input port, 2 ... Display panel, P2 ... Authentication port, 4 ... Panel drive part, 6 ... DSP, 10 ... Selector, 12 ... Decoder, 14 ... DDC interface part, 20 ... Decryption part, DESCRIPTION OF SYMBOLS 22 ... Register, 24 ... Multiport control part, 26 ... Cancel code generation part, 30 ... 1st operation module, 32 ... 2nd operation module, 40 ... Decoding module, 42 ... Output interface part, 100 ... Interface circuit, _POUT ... output port.

Claims (3)

An interface circuit that receives encrypted data streams from a plurality of external devices to a plurality of ports, and outputs the data stream input to the active port after being decrypted,
A first computing module for computing data necessary to establish and maintain a link with each of the plurality of external devices;
A second operation module that receives data corresponding to an active port among data obtained by the operation of the first operation module, and generates a release code necessary for decoding the data stream input to the active port;
A decoding module for decoding the data stream input to the active port using a release code output from the second arithmetic module;
An interface circuit comprising: The data from the external device is image data,
The first calculation module executes calculation processing for each frame;
The interface circuit according to claim 1, wherein the second arithmetic module executes arithmetic processing for each pixel.   An electronic device comprising the interface circuit according to claim 1.

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