JP2012023165A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable and effective for practical use and where fluctuation of a pressure resisting feature is small in a high breakdown voltage semiconductor device which is integrated on an SOI substrate and in which rated voltage is shared between an embedded oxide film and a drain of an element active layer.SOLUTION: A high breakdown voltage semiconductor device of high reliability with small fluctuation of the pressure resisting feature can be provided by providing a floating resurf layer on a source side and an n-type electric field relaxation layer on a drain side and means for relaxing simultaneous electric field concentration in a source region and a drain region.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device suitable for using a dielectric isolation system for element isolation and optimally controlling a power device that drives a motor, and a method for manufacturing the same.

  A dielectric isolation type semiconductor device is used as a semiconductor device that optimally controls a power device. A dielectric isolation type semiconductor device is a semiconductor device in which a high breakdown voltage element, a large current output circuit, and a low breakdown voltage logic circuit are integrated, and each element is surrounded by a dielectric material such as a silicon oxide film. The element and the substrate are insulated and separated at a high voltage.

  For example, a dielectric separation type device for controlling the driving of a motor includes various circuits such as a high voltage side gate drive circuit, a high voltage MOS transistor for supplying a control signal to the high voltage side gate drive circuit, and a control logic circuit. It is what is done.

  FIG. 11 shows a cross-sectional view of a high voltage n-type MOS transistor based on the first prior art provided in a dielectric isolation type semiconductor device (hereinafter referred to as prior art A).

In FIG. 11, the source terminal is electrically ohmically connected to an n ⁺ type high impurity concentration layer 110 and a p ⁺ type high impurity concentration layer 120. The drain terminal is ohmically connected to the n ⁺ -type high impurity concentration layer 130. Reference numeral 102 denotes a gate electrode. Reference numeral 140 denotes a p-type channel region, and an n-type channel inversion layer is formed immediately below the gate electrode 102. Each of these n-type and p-type regions is formed by applying a silicon substrate called an SOI (Silicon On Insulator) substrate.

  The SOI substrate is a substrate composed of a silicon support substrate 105 and a silicon active layer 108 having a predetermined thickness with a silicon oxide film 106 interposed therebetween. Hereinafter, this intermediate silicon oxide film 106 is referred to as a buried oxide film.

  The silicon active layer 108 is formed with a dielectric isolation region 107 that electrically isolates the element from the surrounding region in a substantially vertical shape reaching the buried oxide film 106 from the surface of the silicon active layer 108. The dielectric isolation region 107 is composed of a silicon oxide film 171 formed on the side wall of the vertical groove and a polycrystalline silicon layer 172 buried therebetween. In addition, thick silicon oxide films 160 and 161 (hereinafter referred to as field oxide films) are formed in a predetermined region on the surface of the silicon active layer 108, and the n and p type impurity regions on the surface are separated from each other. ing.

In the cross-sectional view of the semiconductor device shown in FIG. 11, a p ⁻ -type high impurity concentration layer 100 is provided in a predetermined surface region of the silicon active layer between the source and the drain. Since the p ⁻ -type high impurity concentration layer 100 is formed in an electrically floating state, even if a high blocking voltage is applied, the electric field on the surface of the silicon active layer is relaxed and the breakdown voltage of the device is increased.

  Here, the floating state refers to a state in which the potential is not in contact with a semiconductor region, an electrode, or the like where the potential is not fixed.

  On the other hand, FIG. 12 shows a cross-sectional view of a high voltage n-type MOS transistor based on the second prior art provided in the dielectric isolation type semiconductor device (hereinafter referred to as prior art B).

In FIG. 12, the drain layer is composed of an n ⁺ -type high impurity concentration layer 130, an n-type impurity concentration layer 300 surrounding this, and an n ⁻ -type low impurity concentration layer 301 surrounding the n-type impurity concentration layer 300. . The n ⁻ type low impurity concentration layer 301 is specified as noffset. The noffset 301 is introduced for the purpose of reducing the resistance of the drain layer and realizing a breakdown voltage substantially equal to the breakdown voltage in the off state even when the element is on.

JP 2008-244092 A

Proc.ISPSD2006, pp.341-344

  However, it has been revealed for the first time by detailed studies by the present inventors that the elements based on the above two conventional techniques are insufficient in terms of reducing the characteristic variation of the blocking characteristics.

  Here, the characteristic fluctuation means the following phenomenon. That is, when a voltage is applied in the off state of the element, an off current flows at a voltage lower than a desired voltage value. After that, when the voltage is continuously applied, the off-current is decreased and a higher voltage can be applied. This is a phenomenon in which the voltage at which the off-current rises increases with time, and such a characteristic variation frequently occurs in a high-breakdown-voltage element to which a high voltage is applied. The problem is when the current rises at a voltage lower than the rated voltage of the element, and it is important to first make the voltage value at which the current rises higher than the rated blocking voltage.

  When the cause of the characteristic fluctuation of the lateral element structure in which the source and drain semiconductor layers are formed opposite to each other on the semiconductor surface was investigated, it was found that the cause was due to the electric field distribution on the silicon surface during application.

  This point will be described in further detail. The electric field distribution on the surface of the silicon active layer was numerically calculated by taking two types of element structures designed based on the prior art of FIGS. The result is shown in FIG.

  As shown in FIG. 13, it can be seen that there are regions where the electric field exceeds 250 kV / cm in the source region in the prior art A and in the drain region in the prior art B, respectively.

  In this way, when the surface electric field is locally concentrated, the influence of a slight interface charge existing at the interface between the oxide film and silicon is further added, and a high electric field exceeding the breakdown strength of silicon is concentrated locally. Appears where it is. For this reason, even if a voltage lower than the rated blocking voltage is applied, avalanche occurs on the silicon surface in this portion. When avalanche is generated, hot electrons with high energy are generated inside the silicon, so that hot electrons are injected into the oxide film beyond the potential barrier of the oxide film. Since the injected electrons neutralize the interface charge, the avalanche phenomenon is suppressed and the leakage current is reduced. When the applied voltage is increased, avalanche is generated again, hot electrons are generated again, and the interface charge is further neutralized. Repeating this phenomenon causes characteristic fluctuations in which the rising voltage of the current increases.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a stable and highly reliable element structure in which the above-described characteristic variation is small and a method for manufacturing the same in a MOS transistor. It is in.

  Another object of the present invention is to provide a semiconductor device having an element structure capable of increasing the withstand voltage suitable for practical use and a method for manufacturing the same. Here, the specific meaning of being suitable for practical use relates to the specification of the SOI substrate on which the element is formed, and is to widen the allowable range of the substrate to facilitate practical use.

  In order to achieve the above object, a semiconductor device of the present invention includes a support substrate, an insulating film stacked on the support substrate, and a semiconductor layer of a first conductivity type stacked on the insulating film. In a semiconductor device in which a high breakdown voltage MOS transistor is provided in at least one of semiconductor regions formed by separating the semiconductor layer by a dielectric that reaches the insulating film from the main surface of the layer, the high breakdown voltage MOS transistor includes: A first semiconductor region in which a first conductivity type semiconductor layer is a low-concentration drain layer and an electrically floating state formed on at least part of the surface of the first semiconductor region between a source electrode and a drain electrode A second semiconductor region of the second conductivity type, and a third semiconductor of high impurity concentration of the first conductivity type that is in ohmic contact with the drain electrode in a predetermined region of the first semiconductor region. A fourth semiconductor region having a lower impurity concentration than the third semiconductor region of the same conductivity type formed adjacent to and surrounding the third semiconductor region, and the fourth semiconductor having the same conductivity type And a fifth semiconductor region having a lower impurity concentration than that of the region, wherein the fifth semiconductor region is formed surrounding the fourth semiconductor region.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of preparing an SOI substrate in which a silicon oxide film and a silicon active layer are stacked on a silicon support substrate; and a main surface of the silicon layer. Forming a substantially vertical dielectric isolation groove reaching the silicon oxide film; filling the dielectric isolation groove with a thermal oxide film and polycrystalline silicon; and forming a silicon active layer on the surface of the silicon active layer. A step of forming a semiconductor region of the same conductivity type as the layer, a step of forming a semiconductor region of a conductivity type opposite to the silicon active layer on the surface of the silicon active layer, and a field oxide film separating the element active layer by selective oxidation Forming a gate oxide film and a gate electrode on the surface of the silicon active layer, forming a channel layer of a high voltage MOS transistor, Characterized in that it contains.

  According to the present invention, the electric field on the surface of the silicon active layer on which the high voltage MOS transistor is formed can be controlled independently and simultaneously for the source region and the drain region, and can be made substantially flat from the source region to the drain region. Therefore, in a MOS transistor, a stable and highly reliable element structure with little characteristic variation can be obtained.

  Furthermore, since the flatness of the electric field distribution in the depth direction of the silicon active layer can be improved, the allowable range for the resistivity of the silicon active layer can be expanded and the specification of the SOI substrate can be relaxed. Thereby, cost reduction of the SOI substrate can be realized.

It is sectional drawing which shows the dielectric isolation type semiconductor device concerning the 1st Embodiment of this invention. FIG. 6 is a characteristic diagram showing an impurity concentration distribution in a depth direction under an n ⁺ drain region of the dielectric isolation type semiconductor device according to the first embodiment of the present invention. 1 is a block diagram showing a motor drive system using a dielectric isolation type semiconductor device of the present invention. It is a characteristic view which shows the electric field distribution in the silicon | silicone active layer surface of the dielectric material isolation type semiconductor device concerning the 1st Embodiment of this invention. It is a characteristic view which shows the relationship between the proof pressure of the dielectric isolation type semiconductor device concerning the 1st Embodiment of this invention, and the resistivity of a silicon active layer. It is a top view which shows an example of the dielectric isolation type semiconductor device concerning the 1st Embodiment of this invention. It is a top view which shows the other example of the top view of the dielectric isolation type semiconductor device concerning the 1st Embodiment of this invention. It is sectional drawing which shows a part of manufacturing process of the dielectric isolation type semiconductor device concerning the 1st Embodiment of this invention. FIG. 9 is a cross-sectional view showing a part of the manufacturing process of the dielectric isolation type semiconductor device according to the first embodiment of the present invention and showing the continuation of the process of FIG. FIG. 8 is a cross-sectional view showing a part of the manufacturing process of the dielectric isolation type semiconductor device according to the first embodiment of the present invention and continued from FIG. It is sectional drawing which shows the dielectric isolation type semiconductor device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows the dielectric isolation type semiconductor device concerning the 3rd Embodiment of this invention. It is sectional drawing which shows the dielectric isolation type semiconductor device of 1st prior art A. It is sectional drawing which shows the dielectric isolation type semiconductor device of the 2nd prior art B. It is a characteristic view which shows electric field distribution in the silicon | silicone active layer surface of the dielectric isolation type semiconductor device of a prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that, in all the drawings for explaining the embodiments and in all the drawings for explaining the above-described prior art, the same or similar parts are denoted by the same or similar symbols in principle, and the repeated explanation thereof is omitted. To do.

  First, details of the dielectric isolation type semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 3 shows a motor drive system 1 using a dielectric isolation type semiconductor device. As shown in the figure, the motor drive system includes an IGBT module 5 that drives a load motor 3, a drive circuit 7 that basically includes two upper and lower MOS transistors that control the switching operation of the IGBT module 5, and It consists of a dielectric isolation type semiconductor device 10 that optimally controls the drive circuit 7. Here, the dielectric isolation type semiconductor device 10 has an interface with a high voltage side gate drive circuit 12, a high voltage MOS transistor 14 for supplying a control signal to the drive circuit 12, and a digital control IC for controlling the entire system. Although not shown in the figure, the control logic circuit 20 includes various protection circuits.

  In FIG. 3, the elements constituting the high voltage side gate driving circuit integrated as a dielectric isolation type semiconductor device have a MOS transistor structure. Since the high voltage side gate drive circuit operates by being connected to the gate terminal of the upper arm element in the output circuit of the motor driver, the source rises to a voltage higher than the high voltage power supply of the load, so the gate potential is raised to the high voltage potential. It is necessary to shift the level using a high breakdown voltage n-type MOS and a high breakdown voltage p-type MOS.

  FIG. 1 is a sectional view of a dielectric isolation type semiconductor device according to the first embodiment of the present invention, which is applied to a high breakdown voltage nMOS transistor forming an n-type channel. However, only nMOS transistors are shown in FIG. 1, and other elements are omitted. The semiconductor support substrate, particularly the silicon support substrate 105 is p-type, but there is no problem with n-type silicon.

N of the silicon oxide film high resistance at a constant impurity concentration through the (buried oxide) 106 (low impurity concentration) ^- -type silicon active layer 108 is disposed is stacked to form a so-called SOI substrate. A substantially vertical groove reaching the buried oxide film 106 from the main surface of the n ⁻ -type substrate 108 is formed. A dielectric member is embedded in the groove to form a dielectric isolation region 107. The planar shape of the groove is a closed loop and has a function of insulating and separating the inside and the outside. A silicon oxide film 171 is formed on both side surfaces of the groove, and polycrystalline silicon is buried between the silicon oxide films 171 to form a polycrystalline silicon layer 172.

In this embodiment, a structure in which the element formation region is surrounded by a single dielectric isolation region 107 is shown, but a multiple structure may be used. The n ⁻ -type silicon active layer 108 functions mainly as a drift layer that shares the blocking voltage in the OFF state of the NMOS transistor.

An n ⁺ type high impurity concentration layer 110 and a p ⁺ type high impurity concentration layer 120 are formed on one side of the gate electrode 102. This n ⁺ -type high impurity concentration layer 110 is a source layer of the MOS transistor, and is also referred to as an n ⁺ source 110 hereinafter. A p-type channel region 140 is formed so as to surround the n ⁺ source 110 and the p ⁺ -type high impurity concentration layer 120 and overlap by a predetermined distance from one end of the gate electrode 102. In the p-type channel region 140, an n-type inversion layer is formed on the surface overlapping with the gate electrode 102 when a positive voltage is applied to the gate electrode, and electrons are injected from the n ⁺ source 110. An electron channel region in which carriers flow through the inversion layer to the drain region facing the source region is formed. This state is called an on state of the element.

The p ⁺ -type high impurity concentration layer 120 described above is a layer that determines the potential of the p-type channel region 140 and is usually ohmically connected to the source electrode 101 simultaneously with the n ⁺ source 110. The drain region is formed on the surface of the silicon active layer 108 facing the source region with a predetermined distance from the gate electrode 102. First, an n ⁺ -type high impurity concentration layer 130 surrounds the n ⁺ -type high impurity concentration layer 130 and an n-type impurity concentration layer 300 lower than this layer further surrounds the n-type impurity concentration layer 300 and further has an impurity concentration. A low n ⁻ -type impurity concentration layer 400 is formed in the drain region.

FIG. 2 shows a representative example of the carrier concentration distribution (substantially equal to the impurity concentration distribution) taken in the depth direction from the surface of the silicon active layer in the drain region. As shown in the figure, the drain region has a four-stage configuration of N ⁺ , N, N ⁻ , and N ⁻ .

A thick silicon oxide film is formed in a predetermined planar shape on the main surface of the n ⁻ -type silicon active layer 108 to form field oxide films 160 and 161.

  The present embodiment is characterized in that the thickness of the field oxide film is not constant and is formed differently from two kinds of film thicknesses as shown in the figure. This is a structure in which measures are taken for the purpose of wiring processability and the effect of mitigating electric field concentration by increasing the thickness sequentially until reaching a thick oxide film.

Further, a p ⁻ type high impurity concentration layer 100 is formed on the surface of the n ⁻ type silicon active layer 108 between the n ⁻ type impurity concentration layer 400 and the n ⁺ source 110. The p ⁻ type high impurity concentration layer 100 shows a case where the p ⁻ type high impurity concentration layer 100 is formed so as to overlap with a source electrode formed extending on the field oxide film 162 in a planar arrangement. It should be determined in detail from the viewpoint of the relaxation design of the surface electric field. The important point is that the p ⁻ type high impurity concentration layer 100 is formed in a floating state. Further, although shown in contact with the n ⁻ -type impurity concentration layer 400 provided in the drain region, this point is not limited.

Next, the effect in this embodiment is explained in full detail. When a blocking voltage (also referred to as a reverse voltage) is applied between the source and the drain in an off state, that is, a state where 0 V or a negative voltage is applied to the gate electrode, the p-type channel region 140 and the n ⁻ A depletion layer with no carriers is formed in the depth and lateral direction from the pn junction surface with the silicon active layer 108 of the type drain. The spread of the depletion layer depends on the applied voltage. However, in the case of a general SOI type device, the electric field can be relaxed and high voltage can be prevented by designing the entire silicon active layer to be depleted.

  An object of the technique of the present invention is to reduce the fluctuation of the withstand voltage characteristics described above. For this purpose, an electric field on the surface of the silicon active layer becomes a problem. As shown in the problem of the prior art in FIG. 13, the electric field on the silicon surface has high electric field portions at two locations on the source side and the drain side. When this point is examined more specifically, the concentration point of the electric field is the terminal point of the source electrode 101 and the drain electrode 103. Therefore, it was considered that if the electric fields on the source side and the drain side can be controlled simultaneously, the electric field can be flattened as a whole, and an element that is resistant to characteristic fluctuations can be realized.

  Therefore, a structure in which an impurity concentration layer slightly higher than the impurity concentration of the silicon active layer 108 is provided in the drain region was examined. It has been found that the electric field distribution in the depth direction in the drain region becomes flatter than in the case where there is no impurity concentration layer, and as a result, the electric field on the drain surface can be reduced. This electric field relaxation effect is also related to the profile of the impurity concentration layer, and the electric field relaxation effect is strong with a profile in which the impurity concentration is sequentially reduced from the surface toward the inside, and it appears strongly when the depth is deep.

However, when a high voltage can be shared on the drain side, the electric field on the source side increases as a result of bearing the increased voltage on the source side. At this time, it is necessary to take measures to reduce the electric field at the end of the source electrode where electric field concentration appears. The p ⁻ type high impurity concentration layer 100 is considered as a countermeasure. The p ⁻ -type high impurity concentration layer 100 increases the spread of the depletion layer in the vicinity of the source electrode and exhibits a significant electric field relaxation effect. Therefore, it is desirable that the p ⁻ -type high impurity concentration layer 100 and the source electrode are arranged so as to overlap each other in plan position.

  FIG. 4 shows the electric field distribution from the source end toward the drain on the surface of the silicon active layer when the structure having the electric field relaxation action on the drain side and the source side is applied at the same time. It is a result.

  As shown in the figure, the peak values of the electric field on the source side and the drain side are substantially equal, and the electric field does not concentrate locally. Moreover, it can be controlled to a low value of 200 kV / cm or less. In general, in the case of silicon, it is known that an avalanche phenomenon occurs in an electric field of 300 kV / cm. Since this value is reduced by 30%, an avalanche is not generated on the surface and is generated inside the silicon, so that an element having no characteristic variation can be realized.

  FIG. 5 shows the relationship between the breakdown voltage of the NMOS transistor and the resistivity of the silicon active layer 108 (shown as the resistivity of the SOI active layer in the figure) as a prototype of the device of this embodiment. It shows in comparison with.

  As shown in the figure, an element having substantially the same breakdown voltage can be obtained in a wide range of resistivity from 30 Ω · cm to 50 Ω · cm, and the required specification for the resistivity of the SOI substrate can be greatly relaxed compared to the conventional device. . This achieves a significant yield improvement in manufacturing an SOI substrate, and achieves highly practical effects such as a reduction in substrate cost.

FIG. 6 shows a typical example of the planar pattern of the present embodiment. However, only the portion having the main function is shown. An n ⁺ source 110 is arranged in the central region of the dielectric isolation region 107, and an n ⁺ drain 130 surrounding the U ⁺ shape is arranged. A p ⁻ type high impurity concentration layer 100 is arranged in a ring shape so as to surround the n ⁺ source 110. The n ⁻ -type impurity concentration layer 400 is formed to surround the U-shaped n ⁺ drain 130 layer while facing the p ⁻ -type high impurity concentration layer 100. A portion of the outline of the n ⁻ -type impurity concentration layer 400 is disposed so as to be in contact with the element isolation region.

In the planar pattern of the present embodiment, the n ⁻ -type impurity concentration layer 400 is U-shaped. However, depending on the case, the entire outer portion may be in contact with the element isolation region on the drain side. In this manner, by providing the n ⁻ type high impurity concentration layer 400 in the entire outer region of the drain, the electric field relaxation in the element isolation region acts and the characteristic stability is increased.

FIG. 7 shows a second example of the planar pattern of the present embodiment. Only the part which has the main functions like FIG. 6 is shown. Unlike FIG. 6, an n ⁺ drain 130 is disposed in the central region of the dielectric isolation region 107, and an n ⁺ source 110 surrounding the U ⁺ shape is disposed. An n ⁻ type impurity concentration layer 400 is arranged in a donut shape so as to surround the n ⁺ drain 130. On the outside, the p ⁻ type high impurity concentration layer 100 is formed in the same donut shape while facing the n ⁻ type impurity concentration layer 400.

In the planar pattern of the present embodiment, in the n ⁺ source 110 surrounding one n ⁺ drain 130 in a U shape, the n ⁺ drain from the end of the U shape n ⁺ source 110 is the portion where the drain electrode is drawn to the external region. 130 protrudes. Electric field concentration is likely to occur where the drain electrode is drawn out. For this reason, the opposing length with respect to the n ⁺ source 110 is increased to effectively act on electric field relaxation.

  Although FIG. 6 and FIG. 7 show plan views of the first embodiment, the planar pattern can be considered as separate from the cross-sectional structure, and can be applied to other embodiments.

  Next, a method for manufacturing the dielectric isolation type semiconductor device according to the first embodiment will be described with reference to FIG.

  8A, 8B, and 8C are process cross-sectional views illustrating the manufacturing process of the dielectric isolation type semiconductor device according to the first embodiment. The manufacturing process is as shown in (a), (b), (c) of FIG. 8-1, (d), (e) of FIG. 8-2, and (f), (g) of FIG. In order.

First, as shown in FIG. 8A, an SOI substrate is prepared in which an n ⁻ -type silicon active layer 108 is stacked on one surface of a silicon support substrate 105 with a silicon oxide film 106 interposed therebetween. Different specifications may be applied to the thickness of the silicon oxide film 106 depending on the rated voltage of the semiconductor element.

  In order to guarantee the long-term reliability of the dielectric isolation type semiconductor device, the allowable electric field applied to the oxide film is set to 2 MV / cm or less. If the allowable electric field is to be satisfied with an element rated at 600 V, the thickness of the silicon oxide film needs to be 3 μm. On the other hand, when the thickness of the silicon oxide film increases, a large warp occurs due to the difference in thermal expansion coefficient between the silicon oxide film and silicon. When the warpage becomes large, troubles occur in mounting of a wafer on an exposure apparatus in photolithography, mounting of a wafer in a dry etching apparatus, and the like, and thus a countermeasure for reducing the warpage is required.

In FIG. 8B, a trench reaching the buried silicon oxide film 106 from the main surface of the n ⁻ -type silicon active layer 108 is formed in a vertical shape using a dry etching apparatus. Since it becomes difficult to fill the groove width as the width becomes wider, the width is set to about 2 μm. After forming the vertical groove, heat treatment is performed in an oxidizing atmosphere to form a silicon oxide film 171 on the side wall of the groove. Thereafter, a polycrystalline silicon layer 172 is formed and filled in the gap of the groove by a CVD method, and the dielectric isolation region 107 is formed.

In FIG. 8C, the main surface of the n ⁻ -type silicon active layer 108 is covered with a silicon oxide film 610 and a photoresist film 620 to form an n ⁻ -type impurity concentration layer 400 using a photolithography technique. Part of the resist is removed. Phosphorus ions are implanted into the silicon through this opening. The acceleration voltage is set to 100 keV to 150 keV, and the dose amount is set to about 10 ¹¹ to 10 ¹² pieces / cm ² . After the ion implantation, a heat treatment is performed at a temperature of about 1200 ° C. for several hours to extend the impurity element of phosphorus to a depth of at least 10 μm or more. This high-temperature heat treatment can suppress the fluctuation due to the redistribution of the impurity concentration distribution in the oxidation process performed in a later process.

In FIG. 8-2 (d), the photoresist film 621 is coated again, the resist for the p ⁻ type high impurity concentration layer 100 is removed by the photolithography technique, and boron ions are introduced into the silicon by the ion implantation technique. Inject. The acceleration voltage is 50 keV and the dose is about 10 ¹² / cm ² . After the ion implantation, the p ⁻ type high impurity concentration layer 100 is stretched by heat treatment at a temperature of 1100 ° C. to 1200 ° C. Although illustration is omitted, the photolithographic technique is applied in the same manner as described above, and phosphorus ions are implanted into silicon at an acceleration voltage of 125 keV, a dose of 10 ¹² / cm ² , and then at a temperature of 1200 ° C. An n-type impurity concentration layer 300 is formed by heat treatment for a time.

  In FIG. 8-2 (e), the selective oxidation method using a silicon nitride film is repeated twice to form a thick field oxide film 160 and a thin field oxide film 161. Alternatively, three types of oxide films having different thicknesses may be formed by repeating the selective oxidation method three times.

  In FIG. 8C, a silicon oxide film is formed on the main surface of the silicon active layer 108 with a thickness of 50 nm to 80 nm, and this is used as the gate oxide film 112. Then, a polycrystalline silicon film is formed on the gate oxide film, and this polycrystalline silicon film is patterned with a normal dry etching apparatus to form the gate electrode 102.

8G, boron ions are ion-implanted in an self-aligned manner with the gate electrode 102 at an acceleration voltage of several tens keV to form a p-type channel region 140 of a high breakdown voltage n-channel MOS. Next, ions are implanted using phosphorus ions at an acceleration voltage of 100 keV to form the n ⁺ drain 130. Further, the n ⁺ source 110, the p ⁺ type high impurity concentration layer 120, and the n ⁺ drain 130 are formed in a self-aligned manner by using the gate electrode 102 and the field oxide film 161, respectively, by ion implantation.

  Thereafter, a silicon oxide film is formed by a process necessary for a normal semiconductor manufacturing apparatus, for example, a CVD method, and a dry etching apparatus is used on each element where electrical connection such as a source, collector, and gate is necessary. The source electrode 101 and the drain electrode 103 are formed by an opening step, a step of forming and processing an electrode containing aluminum as a main component by sputtering, and the like. Thereafter, a silicon nitride film is formed for the purpose of protecting the element from the intrusion of impurities such as moisture, and a final electrode extraction opening is formed. The dielectric isolation type semiconductor device is completed through the above processes.

  Next, another embodiment according to the present invention will be described.

  Next, a dielectric isolation semiconductor device according to the second embodiment of the present invention will be described.

FIG. 9 is a sectional view of a dielectric isolation type semiconductor device according to the second embodiment of the present invention. Embodiment differs from FIG. 1, n ^- bottom type low impurity concentration in the silicon active layer 108, i.e., n in the region adjacent to the buried oxide film 106 ^- than type low impurity concentration in the silicon active layer 108 The n-type semiconductor layer 180 having a high impurity concentration is stacked.

The n-type semiconductor layer 180 laminated on the bottom surface needs to have an appropriate thickness and concentration. In this embodiment, the thickness is 10 μm or less, and the impurity concentration is 5 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm. A range of ^-3 is desirable.

  When a blocking voltage is applied to the drain, the silicon active layer 108, the n-type impurity concentration layer 180, and the buried oxide film 106 share this voltage. In the case of the present embodiment, the shared voltage ratio is generated on the silicon side because the shared voltage on the silicon oxide film 106 side increases and the shared voltage on the silicon side decreases due to the effect that the n-type semiconductor layer 180 is installed. And the applied blocking voltage can be increased.

  Next, a dielectric isolation semiconductor device according to the third embodiment of the present invention will be described.

FIG. 10 is a sectional view of a dielectric isolation type semiconductor device according to the third embodiment of the present invention. Each embodiment differs from FIGS. 1 and 9, the n ^- -type low impurity concentration bottom surface of the silicon active layer 108, that is, buried in the silicon oxide film 106 and the adjacent regions n ^- -type low impurity concentration That is, an n-type semiconductor layer 180 and an n-type semiconductor layer 181 having a higher impurity concentration than the silicon active layer 108 are stacked.

The n-type semiconductor layers 180 and 181 stacked on the bottom surface need to have an appropriate thickness and concentration. In this embodiment, the thickness is 10 μm or less, and the impurity concentration is 5 × 10 ¹⁴ cm ⁻³ to 1 × 10. A range of ¹⁶ cm ^-3 is desirable. The n-type semiconductor layer 180 is provided on the bottom surface of the silicon active layer 108 at a position substantially opposite to the n ⁻ -type impurity concentration layer 400. The n-type semiconductor layer 181 is disposed in a region other than the n-type semiconductor layer 180 on the bottom surface of the silicon active layer. The impurity concentration is set higher than that of the n-type semiconductor layer 180.

  Thus, the embodiment differs from the embodiment shown in FIG. 9 in that the impurity concentration of the n-type semiconductor layer provided on the bottom surface of the silicon active layer is different in each of the drain region and the source region.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Motor drive system 3 Motor 5 IGBT module 7 Drive circuit 10 Dielectric isolation type semiconductor device 12 High voltage side gate drive circuit 14 High voltage MOS transistor (n channel)
16 High voltage MOS transistor (p channel)
18 Low voltage side gate drive circuit 20 Control logic circuit 100 p ⁻ type high impurity concentration layer 101 Source electrode 102 Gate electrode 103 Drain electrode 105 Silicon support substrate 106 Silicon oxide film (buried oxide film)
107 dielectric isolation region 108 silicon active layer (n ^- type)
110 n ⁺ type high impurity concentration layer (n ⁺ source)
120 p ⁺ type high impurity concentration layer 130 n ⁺ type high impurity concentration layer (n ⁺ drain)
140 p-type channel region 160, 161, 162 field oxide film 171 silicon oxide film 172 polycrystalline silicon layer 180, 181 n-type impurity concentration layer (n-type semiconductor layer)
300 n-type impurity concentration layer 400 n ^- -type impurity concentration layer

Claims (5)

The semiconductor includes a support substrate, an insulating film stacked on the support substrate, and a first conductivity type semiconductor layer stacked on the insulating film, and a dielectric that reaches the insulating film from a main surface of the semiconductor layer. In a semiconductor device in which a high voltage MOS transistor is provided in at least one of semiconductor regions formed by separating layers,
The high-breakdown-voltage MOS transistor includes at least a part of a surface of the first semiconductor region between a first semiconductor region in which the semiconductor layer of the first conductivity type is a low-concentration drain layer and a source electrode and a drain electrode. A second semiconductor region of a second conductivity type formed in an electrically floating state, and a third impurity of a high impurity concentration of the first conductivity type that is in ohmic contact with the drain electrode in a predetermined region of the first semiconductor region. , A fourth semiconductor region having a lower impurity concentration than the third semiconductor region of the same conductivity type formed adjacent to and surrounding the third semiconductor region, and the fourth semiconductor region of the same conductivity type. And a fifth semiconductor region having a lower impurity concentration than that of the semiconductor region, wherein the fifth semiconductor region is formed so as to surround the fourth semiconductor region. The semiconductor includes a support substrate, an insulating film stacked on the support substrate, and a first conductivity type semiconductor layer stacked on the insulating film, and a dielectric that reaches the insulating film from a main surface of the semiconductor layer. In a semiconductor device in which a high voltage MOS transistor is provided in at least one of semiconductor regions formed by separating layers,
The high breakdown voltage MOS transistor includes a first semiconductor region having the first conductivity type semiconductor layer as a low concentration drain layer, and a first conductivity type and a high impurity concentration facing a predetermined region of the first semiconductor region. Second and third semiconductor regions are formed, respectively, constituting a source region and a drain region, respectively, and a source electrode and a drain electrode that are in ohmic contact with the second semiconductor region and the third semiconductor region, respectively And an electric field on the surface of the first semiconductor region, which is generated when a voltage is applied between the source electrode and the drain electrode in an off state of the element, acts individually on the source region and the drain region, respectively. At the same time, a means for realizing electric field relaxation is provided in the first semiconductor region. The semiconductor device according to claim 1 or 2,
A sixth semiconductor layer having an impurity concentration higher than that of the first semiconductor region is stacked on a region of the bottom surface of the first semiconductor region that is in contact with an insulating film provided adjacent to the support substrate. A semiconductor device. The semiconductor device according to claim 1 or 2,
Stacking sixth and seventh semiconductor layers having an impurity concentration higher than that of the first semiconductor region in a region in contact with an insulating film provided adjacent to the support substrate at a bottom surface of the first semiconductor region; The sixth semiconductor region is provided at the bottom of the source region, the seventh semiconductor region is provided at the bottom of the drain region, and the impurity concentration of the sixth semiconductor region is higher than the impurity concentration of the seventh region. A semiconductor device characterized by the above.   A step of preparing an SOI substrate in which a silicon oxide film and a silicon active layer are laminated on a silicon support substrate; a step of forming a substantially vertical dielectric isolation groove reaching the silicon oxide film from a main surface of the silicon layer; Filling the dielectric isolation trench with a thermal oxide film and polycrystalline silicon; forming a semiconductor region of the same conductivity type as the silicon active layer on the surface of the silicon active layer; and a surface of the silicon active layer Forming a semiconductor region having a conductivity type opposite to that of the silicon active layer, forming a field oxide film for separating the element active layer by selective oxidation, and forming a gate oxide film and a gate electrode on the surface of the silicon active layer. A method for manufacturing a semiconductor device, comprising: a step of forming; and a step of forming a channel layer of a high voltage MOS transistor.

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