JP2012018711A - Semiconductor device and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly stabilize an internal voltage off a desired potential at resetting at the desired potential.SOLUTION: A semiconductor device comprises an internal circuit 10 including an access control circuit 14, an internal power source generating circuit 20 for supplying an internal voltage V2 to the internal circuit 10, a reset command generating circuit 28 for resetting the access control circuit 14 by a reset signal RESET supplied from the outside, and a dummy access control circuit 26 for activating the access control circuit 14 after resetting the access control circuit 14 in a case where the reset signal RESET is supplied and in a case where an internal potential detecting circuit 24 determines that the internal voltage V2 is not a desired potential. According to the present invention, dummy access is performed under the condition that the internal voltage V2 is off the desired potential when the reset signal RESET is supplied. Hence, it is possible to rapidly stabilize the internal voltage off the desired potential at the desired potential.

Description

  The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device that executes a reset operation of an internal circuit in response to a reset signal and a control method thereof.

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory), when a reset signal is activated, an internal circuit reset operation is executed. For example, when power is turned on from the outside, a power-on reset signal is generated by a power-on reset circuit, and various internal circuits in the semiconductor device are reset. As a result, the various logic circuits included in the various internal circuits are initialized, and the indefinite state is eliminated.

  As the reset signal, there is an external reset signal supplied from the outside in addition to the power-on reset signal described above. The external reset signal is issued when the system needs to be initialized, and the semiconductor device is forcibly reset when activated. For example, Patent Document 1 discloses a method for reliably resetting a DRAM by automatically executing a precharge operation and a refresh operation when a reset signal is supplied from the outside in a state where power is supplied to the DRAM. Is disclosed. The refresh operation is an operation for accessing the memory cell array. In general, the refresh operation requires a longer time (long busy period) than the precharge operation.

JP 2007-95278 A

  However, in the semiconductor device described in Patent Document 1, when a reset signal is supplied from the outside, a series of operations of a precharge operation and a refresh operation are always performed in response to the reset signal. Even if it is not necessary to perform such operations, the semiconductor device is in a busy period until these series of operations are completed, and the memory controller cannot issue a normal command to the semiconductor device.

  A semiconductor device according to the present invention includes an internal circuit including a first circuit, an internal power generation circuit that generates an internal voltage from an external voltage supplied from an external power supply terminal, and supplies the internal voltage to the internal circuit, An internal potential detection circuit for detecting whether or not the internal voltage is a desired potential, a second circuit for resetting the first circuit by a reset signal supplied from the outside, and the reset signal being supplied And a third circuit that activates the first circuit after the reset of the first circuit when the internal potential detection circuit determines that the internal voltage is not the desired potential.

  The semiconductor device according to the present invention generates an internal voltage from a memory cell array including a plurality of memory cells, an access control circuit that performs an access operation on the memory cell array, and an external voltage supplied from an external power supply terminal, An internal power supply generation circuit for supplying the internal voltage to the memory cell array, the internal voltage supplied to the memory cell array is outside a desired range, and the first reset signal supplied from the outside has changed. In response, the access control circuit includes a dummy access control circuit that activates the access control circuit to access the memory cell array.

  According to the semiconductor device control method of the present invention, an internal voltage is generated from an external voltage supplied from the outside and supplied to the memory cell array, the internal voltage is not a desired potential, and a reset signal is supplied from the outside. In response to this, the method includes a step of activating an access signal and a step of accessing the memory cell array in response to the access signal.

  According to the present invention, when the reset signal is supplied, the access is performed on the condition that the internal voltage deviates from the desired potential. Therefore, the internal voltage deviated from the desired potential can be quickly obtained. The potential can be set. In addition, since the access is not performed when the internal voltage does not deviate from the desired potential, the time required for the reset operation is shortened. This makes it possible to issue a regular command promptly.

It is a block diagram for demonstrating the principle of this invention. 1 is a block diagram showing a configuration of a semiconductor device 100 according to a preferred embodiment of the present invention. FIG. 6 is a waveform diagram of a row access signal RRASB. FIG. 6 is a waveform diagram of a power-on reset signal PON. 3 is a circuit diagram of an internal potential detection circuit 164. FIG. 4 is a truth table of an internal potential detection circuit 164. 3 is a circuit diagram of an automatic refresh command generation circuit 200. FIG. 4 is a timing chart for explaining the operation of the semiconductor device 100. FIG. 3 is a circuit diagram showing a part of an internal power supply generation circuit 162. FIG. 3 is a circuit diagram showing a part of a sense circuit 121. FIG. It is a wave form diagram for demonstrating the problem when the internal voltage Vary is too high. It is a circuit diagram of an automatic refresh command generation circuit 200a according to a modification. It is a wave form diagram for demonstrating the problem when the selection voltage VPP is too high.

  A typical example of a technical idea (concept) for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present application are not limited to this technical idea, but are the contents described in the claims of the present application. That is, the present invention is based on the condition that the reset signal has changed while the internal voltage generated from the external voltage supplied from the outside and supplied to the internal circuit via the internal power generation circuit is outside the desired range. For example, a technical idea is to execute dummy access to a memory cell array that consumes a large amount of power in an internal circuit. As a result, a relatively large amount of power is consumed inside the semiconductor device, so that the internal voltage can be quickly stabilized within a desired range by the adjustment function of the internal power generation circuit that generates the internal voltage. It becomes possible. On the other hand, in the state where the internal voltage is within a desired range, dummy access is not performed even if the above condition is not satisfied and the reset signal changes, so the busy period of the semiconductor device viewed from the outside can be shortened. Is possible. Therefore, the dummy access means that an internal circuit (memory cell array) with large power consumption is actively operated in order to make the adjustment function of the internal power generation circuit work. When a semiconductor device is not mounted with a memory cell array, that is, when an internal circuit that consumes a large amount of power among the internal circuits is an “other circuit” other than the memory cell array, the other circuit is dummy accessed. Needless to say. Therefore, this technical idea can be applied to CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), and ASSP (Application Specific Standard Circuit).

  FIG. 1 is a block diagram for explaining the principle of the present invention.

  The present invention is a semiconductor device including an internal circuit 10 that operates with an internal voltage V2. The internal circuit 10 includes a memory cell array 12 (fourth circuit) that consumes a large amount of power, for example, and an access control circuit 14 (first circuit) that performs an access operation on the memory cell array 12. Although not particularly limited, the memory cell array 12 is a cell array including a plurality of DRAM memory cells. The internal voltage V2 is supplied from the internal power supply generation circuit 20. The internal power supply generation circuit 20 generates the internal voltage V2 by stepping down or boosting the external voltage V1 supplied from the outside via the power supply terminal 22, and supplies this to the internal circuit 10.

  The internal voltage V2 is also supplied to the internal potential detection circuit 24. The internal potential detection circuit 24 is a circuit that detects whether or not the internal voltage V2 is a desired potential, and the detection result is supplied to a dummy access control circuit (third circuit) 26. The dummy access control circuit 26 is supplied with a reset signal R1 supplied from the outside via the command terminal 30.

  The reset signal R1 is also supplied to a reset command generation circuit (second circuit) 28. The reset command generation circuit 28 is a circuit that executes a reset of the access control circuit 14 in response to the activation of the reset signal R1. When the access control circuit 14 is reset, various logic circuits constituting the access control circuit 14 are initialized, and the indefinite state is eliminated.

  Further, the dummy access control circuit 26 resets the access control circuit 14 when the reset signal R1 is supplied and the internal potential detection circuit 24 determines that the internal voltage V2 is not a desired potential. After that, the access control circuit 14 is activated. As described above, since the access control circuit 14 is a circuit that performs an access operation on the memory cell array 12, when the access control circuit 14 is activated by the dummy access control circuit 26, the access control circuit 14 is connected to the memory cell array 12. Dummy access is performed.

  When dummy access is performed by the access control circuit 14, a relatively large amount of power is consumed in the internal circuit 10, so that the adjustment function of the internal power supply generation circuit 20 works and the internal voltage V2 is quickly stabilized within a desired range. It becomes possible to make it.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a block diagram showing a configuration of the semiconductor device 100 according to the preferred embodiment of the present invention.

  As shown in FIG. 2, the semiconductor device 100 according to the present embodiment includes a memory cell array 110 (internal circuit) including a plurality of memory cells MC. In the memory cell array 110, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at these intersections. FIG. 2 shows only one memory cell MC arranged at the intersection of one word line WL and one bit line BL.

  Selection of the word line WL is performed by the row decoder 120. Each bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 121, and the sense amplifier SA selected by the column decoder 122 is connected to the data input / output circuit 123. The data input / output circuit 123 is connected to the data input / output terminal DQ and outputs read data read from the memory cell array 110 to the outside via the data input / output terminal DQ during the read operation, and during the write operation. Supplies write data input to the data input / output terminal DQ from the outside to the memory cell array 110. A circuit block including at least the row decoder 120 and the sense circuit 121 constitutes a dummy access control circuit in the present invention.

  The row address supplied to the row decoder 120 is supplied from the row address control circuit 131 via the multiplexer 130. The operation of the row decoder 120 is controlled by the row control circuit 132. The row address control circuit 131 is a circuit to which a row address is supplied among addresses (external addresses) input to the address input circuit 133 via the address terminal ADD. When the command input to the command input circuit 140 via the command terminal CMD is an active command (ACT command), the active command generation circuit 141 activates the active command IACT and supplies it to the row control circuit 132. To do. The active command IACT is also supplied to the multiplexer 130. When the active command IACT is activated, the multiplexer 130 selects the input node a. Thus, when an active command and a row address are input from the outside, the row decoder 120 activates the word line WL indicated by the externally input row address. When the word line WL is activated, information of all memory cells selected by the word line WL is read and amplified by the sense amplifier SA.

  On the other hand, the column address supplied to the column decoder 122 is supplied from the column address control circuit 134. The operation of the column decoder 122 is controlled by the column control circuit 135. The column address control circuit 134 is a circuit to which a column address is supplied among addresses (external addresses) input to the address input circuit 133 via the address terminal ADD. If the command input to the command input circuit 140 via the command terminal CMD is a column command (read command or write command), the column command generation circuit 142 activates the read / write command ICOL, This is supplied to the control circuit 135. Thus, when a column command and a column address are input from the outside, the column decoder 122 selects the sense amplifier SA indicated by the column address input from the outside. As a result, read data amplified by the selected sense amplifier SA is output to the data input / output circuit 123 during the read operation, and selected by the write data supplied from the data input / output circuit 123 during the write operation. The information of the sense amplifier SA is overwritten.

  Commands input to the command terminal CMD include an auto refresh command REF, a self refresh entry command SRE, a self refresh exit command SRX, and a reset command RESET in addition to an active command and a column command.

  When the auto-refresh command REF is issued, the refresh command generation circuit 143 activates the refresh instruction IREF. When the refresh instruction IREF is activated, the count value of the refresh address counter 150 is updated (incremented or decremented), and the refresh address REFA that is the count value is supplied to the input node b of the multiplexer 130. More precisely, the information of the refresh address counter 150 before counting is supplied to the multiplexer 130 corresponding to the refresh command IREF, and then the refresh address counter 150 is counted corresponding to the refresh command IREF. The refresh command IREF described above is also supplied to the multiplexer 130. When the refresh command IREF is activated, the multiplexer 130 selects the input node b. As described above, when the auto-refresh command REF is issued, the refresh address REFA output from the refresh address counter 150 is supplied to the row decoder 120, and the word line WL indicated by the refresh address REFA is activated. As described above, when the word line WL is activated, information of all the memory cells selected by the word line WL is read and amplified by the sense amplifier SA, so that these memory cells are refreshed. . The refresh instruction IREF is also supplied to the row control circuit 132, and activates the row decoder 120.

  When self-refresh entry command SRE is issued, self-refresh command generating circuit 144 is activated. When the self-refresh command generating circuit 144 is activated, the operation of the oscillator 145 is started, and a self-refresh signal SR (self-refresh request signal) is generated in synchronization with a signal OSC supplied from the oscillator 145 at a predetermined cycle asynchronous with the outside. Activate. The self-refresh signal SR is supplied to the refresh command generation circuit 143, whereby a refresh operation is performed in the same manner as when the auto-refresh command REF is issued. When self-refresh exit command SRX is issued, self-refresh command generating circuit 144 is deactivated and the operation of oscillator 145 is stopped.

  Further, when the reset command RESET is issued, the reset command generation circuit 146 (second circuit) activates the reset signal RST. The reset signal RST is supplied to various circuit blocks and initializes these circuit blocks. The reset signal RST is also supplied to the automatic refresh command generation circuit 200.

  The automatic refresh command generating circuit 200 (third circuit) is a circuit block corresponding to the dummy access control circuit 26 shown in FIG. 1, and a dummy auto refresh command REF (dummy access signal) is supplied to the refresh command generating circuit 143 ( This is a circuit to be supplied to the first circuit. Therefore, when auto-refresh command REF is generated by automatic refresh command generating circuit 200, refresh command generating circuit 143 activates refresh instruction IREF. Therefore, the same operation as when the auto-refresh command REF is issued from the outside is performed. The circuit configuration of the automatic refresh command generation circuit 200 will be described later. The refresh command generation circuit 143 is an example of a first circuit and is a part of the first circuit.

  As shown in FIG. 2, in addition to the reset signal RST, the automatic refresh command generation circuit 200 is supplied with a row access signal RRASB, a power-on reset signal PON, and a potential detection signal Vdetect.

  The row access signal RRASB is a signal generated by the row control circuit 132. As shown in FIG. 3, the row access signal RRASB changes to the low level in response to the active command IACT being activated to the high level, and the precharge command IPRE Returns to the high level in response to the activation of the high level. The precharge command IPRE is an internal signal that is activated when a precharge command is issued from the outside. The row access signal RRASB also changes to a low level even when the refresh command IREF is activated to a high level, and a pseudo precharge command SIPRE (not shown) that is automatically generated inside the semiconductor device 100 after a predetermined time has elapsed. To return to high level. Therefore, the period during which the row access signal RRASB is at a high level is a period during which no row access is performed.

  The power-on reset signal PON is a signal generated by the power-on reset circuit 161. As shown in FIG. 4, when the external voltage VDD is input, the power-on reset signal PON rises in conjunction therewith. When the external voltage VDD reaches a predetermined value VDDa, the power-on reset signal PON changes to a low level. The external voltage VDD is a power supply voltage supplied from the outside via the power supply terminal VDDT shown in FIG. Therefore, the power-on reset signal generates a one-shot pulse immediately after the power is turned on, and thereafter maintains the low level. The power-on reset signal PON does not generate a one-shot pulse unless the supply of the external voltage VDD is interrupted and then supplied again. The power-on reset signal PON is supplied not only to the automatic refresh command generation circuit 200 but also to various circuit blocks in the same manner as the reset signal RST, and initializes these circuit blocks. In other words, the power-on reset signal PON is a reset signal automatically generated internally in response to power-on, and the reset signal RST is a reset signal generated based on an instruction from the outside.

  The external voltage VDD is also supplied to the internal power supply generation circuit 162 and the reference potential generation circuit 163. The internal power supply generation circuit 162 is a circuit that generates the internal voltage Vary by stepping down the external voltage VDD, and the generated internal voltage Vary is supplied to the sense circuit 121 and is stored in the memory cell array 110 via the sense amplifier SA. Supplied to the bit line.

  The internal voltage Vary is also supplied to the internal potential detection circuit 164. The internal potential detection circuit 164 monitors the level of the internal voltage Vary and detects whether it is within the desired range or outside the desired range. Such detection is performed with reference to two reference potentials VrayRef 1 and VaryRef 2 supplied from the reference potential generation circuit 163. The reference potential VrayRef1 is a potential indicating the upper limit of the internal voltage Vary, and the reference potential VrayRef2 is a potential indicating the lower limit of the internal voltage Vary.

  FIG. 5 is a circuit diagram of the internal potential detection circuit 164, and FIG. 6 is a truth table of the internal potential detection circuit 164.

  As shown in FIG. 5, the internal potential detection circuit 164 includes two comparators 164a and 164b and a NAND gate circuit 164c that receives outputs S1 and S2 of these comparators. The reference potential VaryRef1 is input to the non-inverting input node (+) of the comparator 164a, and the internal voltage Vary is input to the inverting input node (−). Thereby, as shown in the truth table of FIG. 6, when the internal voltage Vary becomes higher than the reference potential VaryRef1, the output S1 becomes a low level. On the other hand, the internal voltage Vary is input to the non-inverting input node (+) of the comparator 164b, and the reference potential VaryRef2 is input to the inverting input node (−). Thereby, as shown in the truth table of FIG. 6, when the internal voltage Vary becomes lower than the reference potential VaryRef2, the output S2 becomes a low level.

  As a result, the potential detection signal Vdetect output from the internal potential detection circuit 164 is at a low level when the internal voltage Vary is within the range of the reference potentials VrayRef1 to VaryRef2, and the internal voltage Vary is within the range of the reference potentials VrayRef1 to VaryRef2. High level when outside.

  FIG. 7 is a circuit diagram of the automatic refresh command generation circuit 200.

  As shown in FIG. 7, the automatic refresh command generation circuit 200 includes a set reset circuit 210 and a counter circuit 220. The set / reset circuit 210 has a configuration in which two NAND gate circuits 211 and 212 are circularly connected. The two NAND gate circuits 211 and 212 are set and reset circuits in a narrow sense. The power-on reset signal PON inverted by the inverter 213 and the output N4 of the counter circuit 220 are supplied to the input node R of the NAND gate circuit 211 on the reset side. The output node N3 of the NAND gate circuit 214 that receives the reset signal RST and the potential detection signal Vdetect is supplied to the input node S of the set-side NAND gate circuit 212.

  The outputs N2 and N3 of the NAND gate circuits 212 and 214 are supplied to the AND gate circuit 230, and the output N5 is supplied to the AND gate circuit 240 together with the row access signal RRASB. The output of the AND gate circuit 240 is used as the refresh command REF and is supplied to the refresh command generation circuit 143 shown in FIG. The refresh command REF is further fed back to the counter circuit 220, and the number of occurrences is counted. The counter circuit 220 is reset by the power-on reset signal PON and the reset signal RST and sets its output N4 to high level. When the number of occurrences of the refresh command REF reaches a predetermined number, the output N4 is changed to a low level.

  The above is the overall configuration of the semiconductor device 100 according to the present embodiment. Next, the operation of the semiconductor device 100 according to the present embodiment will be explained.

  FIG. 8 is a timing chart for explaining the operation of the semiconductor device 100 according to the present embodiment.

  As shown in FIG. 8, when the power-on reset signal PON is activated in response to power-on (time t1), the set reset circuit 210 shown in FIG. 7 is reset, so that the output N1 is at the high level and the output N2 Becomes low level. Thereafter, the reset signal RST is activated in response to the issue of a reset command from the outside (time t2). In the example shown in FIG. 8, since the potential detection signal Vdetect is at the high level at the time of activation of the reset signal RST, that is, the internal voltage Vary is outside the range of the reference potentials VrayRef1 to VaryRef2, the output N3 of the NAND gate circuit 214 is low. Change to level. As a result, the set / reset circuit 210 is set, and the output N1 changes to low level and the output N2 changes to high level.

  As a result, when at least one of the reset signal RST and the potential detection signal Vdetect returns to the low level, the output N5 of the AND gate circuit 230 becomes the high level. At this time, no row access is performed, and the row access signal RRASB is at a high level. Therefore, when the output N5 is at a high level, the refresh command REF that is the output of the AND gate circuit 240 is activated (time t3). ). As a result, the same operation as when an auto-refresh command is issued from the outside is started, and the row access signal RRASB changes to a low level and the memory cell array 110 becomes active as described with reference to FIG. The sense circuit 121 that consumes the most current also operates.

  Then, the row access signal RRASB becomes high level again after a certain period of time has elapsed from the activation of the memory cell array 110 by the well-known active timeout function (generation of the pseudo precharge instruction SIPRE) that the row control circuit 132 has. In response, the refresh command REF is activated again (time t4). When such an operation is repeated and the number of executions reaches the number preset in the counter circuit 220, the output N4 of the counter circuit 220 changes to a low level, and the set reset circuit 210 is reset. In the example shown in FIG. 8, the number of times preset in the counter circuit 220 is 3, and when the third refresh command REF is issued at time t5, the set reset circuit 210 is reset.

  When the set / reset circuit 210 is reset, the output N2 becomes low level, so the output N5 of the AND gate circuit 230 is also fixed at low level, and the refresh command REF is not automatically generated.

  As described above, in this embodiment, when the potential detection signal Vdetect is at a high level at the time of activation of the reset signal RST, the refresh command REF is automatically generated a plurality of times. As a result, the same operation as when the auto-refresh command is issued a plurality of times from the outside is automatically performed, so that a load is applied to the internal power generation circuit 162 and the level of the internal voltage Vary is set to a desired range by the adjustment function. That is, it quickly converges within the range of the reference potentials VrayRef1 to VaryRef2.

  More specifically, as shown in FIG. 9, the internal power generation circuit 162 includes a driver transistor M0 that supplies the internal voltage Vary from the external voltage VDD, and a comparator 162a that controls on / off of the driver transistor M0. When the level of the power supply wiring 162b to which the internal voltage Vary is supplied falls below the reference value VaryR, the comparator 162a turns on the driver transistor M0. As a result, when the level of the power supply wiring 162b reaches the reference value VaryR, the comparator 162a turns off the driver transistor M0.

  That is, the internal power supply generation circuit 162 has a function of increasing the level of the internal voltage Vary supplied to the power supply wiring 162b, but does not have a function of decreasing it. Therefore, in the case where the level of the internal voltage Vary is outside the desired range, in order to converge this within the range of the reference potentials VrayRef1 to VaryRef2, it is effective to consume power by the memory cell array 110. In order to realize this, a dummy refresh operation is performed in the present embodiment.

  When the refresh operation is performed, a large number of sense amplifiers in the sense circuit 121 are activated, so that a relatively large current flows and the level of the internal voltage Vary decreases. As a result, the driver transistor M0 is turned on. Therefore, even when the internal voltage Vary is lower than the reference potential VrayRef2, the internal voltage Vary is quickly raised to the reference potential VrayRef2 or higher. On the other hand, if the internal voltage Vary is higher than the reference potential VrayRef1 before the refresh operation, the internal voltage Vary is quickly lowered to the reference potential VrayRef1 or less due to the level reduction (power consumption) of the internal voltage Vary.

  As described above, in this embodiment, the level of the internal voltage Vary can be quickly converged within a desired range by performing a dummy refresh operation regardless of whether the level of the internal voltage Vary is too low or too high. it can.

  FIG. 10 is a circuit diagram showing a part of the sense circuit 121.

  As shown in FIG. 10, the sense amplifier SA included in the sense circuit 121 has a flip-flop configuration in which inverters are circularly connected, and a pair of input / output nodes c1 and c2 are respectively connected to bit line pairs BT and BN. Connected to one and the other. The sense power supply SA has a high power supply node d1 connected to the high power supply wiring SAP, and a low power supply node d2 connected to the low power supply wiring SAN. Internal voltages Vary and VSS are applied to the high-level power supply line SAP and the low-level power supply line SAN when the sense amplifier SA is activated. On the other hand, when the sense amplifier SA is inactivated when the equalize signal SAEQ is at a high level, the equalize circuit EQ equalizes both the high-potential power supply line SAP and the low-potential power supply line SAN to the intermediate potential VBLP. The intermediate potential VBLP is an intermediate potential between the internal voltages Vary and VSS.

  The input / output nodes c1 and c2 of the sense amplifier SA are connected to the data lines DT and DN via the column switch YS when the column selection signal YSW0 is activated. Therefore, when data opposite to the write data is latched in the sense amplifier SA during the write operation, the sense amplifier SA must be forcibly inverted by the driver that drives the data lines DT and DN. For example, assuming that the transistors M12 and M13 are turned on and the high level is written to the bit line BT and the low level is written to the bit line BN, the transistors M10 and M11 in the sense amplifier SA immediately before the column selection signal YSW0 is activated. When BT = L and BN = H are latched by this, the bit line BN must be driven to a low level by the transistor M13. However, if the internal voltage Vary is too high, the sense amplifier SA As a result of the driving capability of the included transistor M10 becoming stronger than the design value, the sense amplifier SA may not be inverted.

  FIG. 11 is a waveform diagram for explaining this. When the internal voltage Vary is in an appropriate range, the levels of the bit lines BT and BN can be inverted as indicated by a broken line, but the internal voltage Vary is too high. As shown by the solid line, the levels of the bit lines BT and BN cannot be inverted.

  As described above, such a problem is solved by performing power consumption by executing a dummy refresh operation and thereby reducing the level of the internal voltage Vary to a proper level.

  FIG. 12 is a circuit diagram of an automatic refresh command generation circuit 200a according to a modification.

  The automatic refresh command generation circuit 200a shown in FIG. 12 is different from the automatic refresh command generation circuit 200 shown in FIG. 7 in that the potential detection signal Vdetect is input to the AND gate circuit 240a instead of the set reset circuit 210. ing. Accordingly, the NAND gate circuit 214 is replaced with an inverter 214a, and the 2-input AND gate circuit 240 is replaced with a 3-input AND gate circuit 240a. Since the other points are the same as those of the automatic refresh command generation circuit 200 shown in FIG. 7, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  Even when the automatic refresh command generating circuit 200a according to the present example is used, substantially the same operation as in the above embodiment can be realized.

  The case where the detection target of the potential detection signal Vdetect is the internal voltage Vary has been described above as an example. However, in the present invention, the detection target of the potential detection signal Vdetect is not limited to this. For example, the selection voltage VPP of the word line WL driven by the row decoder 120 with high power consumption may be detected. In this case, as shown in FIG. 13, if the selection voltage VPP is in the proper range, the word line is reset at time t11 as shown by the broken line, so that the levels of the bit lines BT and BN amplified by the sense amplifier SA are It is written in the memory cell. On the other hand, when the selection voltage VPP is too high, as shown by the solid line, the time for resetting the word line is shifted until time t12, so that the cell transistor CT (see FIG. 10) of the memory cell is preliminarily turned off. There is a possibility that the charging operation is started. In this case, the correct level cannot be written in the memory cell. Such a problem can also be solved by reducing the level of the selection voltage VPP to an appropriate level by performing the dummy access already described. Further, a power source that supplies an internal power source to the generation circuit of the equalize signal SAEQ disclosed in FIG. Furthermore, at least a combination of these may be used.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  The technical idea of the present application is not limited to the dummy refresh operation as long as it is a dummy access, but can be replaced with various operations that operate the load circuit in an AC manner, such as a dummy read operation and a dummy write operation. . Furthermore, the circuit format in each circuit block disclosed in the drawings and other circuits for generating control signals are not limited to the circuit format disclosed in the embodiments.

  The technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. For example, in general semiconductor devices such as CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), ASSP (Application Specific Standard Circuit), and memory (Memory), The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), POP (package on package), and the like. The present invention can be applied to a semiconductor device having any of these product forms and package forms.

  Further, when a field effect transistor (FET) is used as a transistor, it can be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). Furthermore, some bipolar transistors may be included in the device.

  Further, the PMOS transistor (P-type channel MOS transistor) is a second conductivity type transistor, and the NMOS transistor (N-type channel MOS transistor) is a typical example of the first conductivity type transistor.

  Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 10 Internal circuit 12 Memory cell array 14 Access control circuit 20 Internal power supply generation circuit 22 Power supply terminal 24 Internal potential detection circuit 26 Dummy access control circuit 28 Reset command generation circuit 30 Command terminal 100 Semiconductor device 110 Memory cell array 120 Row decoder 121 Sense circuit 122 Column Decoder 123 Data input / output circuit 130 Multiplexer 131 Row address control circuit 132 Row control circuit 133 Address input circuit 134 Column address control circuit 135 Column control circuit 140 Command input circuit 141 Active command generation circuit 142 Column command generation circuit 143 Refresh command generation circuit 144 Self-refresh command generation circuit 145 Oscillator 146 Reset command Generation circuit 150 Refresh address counter 161 Power-on reset circuit 162 Internal power supply generation circuit 163 Reference potential generation circuit 164 Internal potential detection circuit 200 Automatic refresh command generation circuit 210 Set reset circuit 220 Counter circuit

Claims (17)

An internal circuit including a first circuit;
An internal power generation circuit that generates an internal voltage from an external voltage supplied from an external power supply terminal and supplies the internal voltage to the internal circuit;
An internal potential detection circuit for detecting whether or not the internal voltage is a desired potential;
A second circuit that resets the first circuit by a reset signal supplied from the outside;
A third circuit that activates the first circuit after the reset of the first circuit, when the reset signal is supplied and the internal potential detection circuit determines that the internal voltage is not the desired potential; And a semiconductor device. The operation of the internal circuit is controlled by the first circuit,
The semiconductor device according to claim 1, wherein the internal circuit includes a fourth circuit whose power consumption is larger than that of the first circuit.   The semiconductor device according to claim 1, wherein the third circuit further includes a counter circuit that activates the first circuit a plurality of times in response to one reset signal. The counter circuit counts the number of times the first circuit is activated in response to the one reset signal;
The semiconductor device according to claim 3, wherein the third circuit repeatedly activates the first circuit until the counter circuit counts a predetermined number of times. Furthermore, a power-on reset circuit that detects the input of an external power supply voltage supplied from the outside to the internal power generation circuit,
The third circuit further includes a set reset circuit having a set terminal and a reset terminal,
The semiconductor device according to claim 1, wherein the reset signal is connected to the set terminal, and an output signal of the power-on reset circuit is supplied to the reset terminal. The internal circuit includes a memory cell array whose operation is controlled by the first circuit and which consumes more power than the first circuit,
The semiconductor device according to claim 3, wherein the first circuit includes an access control circuit that accesses the memory cell array. The access control circuit includes a row decoder for selecting a word line included in the memory cell array,
The semiconductor device according to claim 6, wherein the third circuit activates at least the row decoder. The access control circuit further includes a sense circuit for driving a bit line included in the memory cell array,
8. The semiconductor device according to claim 7, wherein the third circuit refreshes memory cells included in the memory cell array by activating at least the row decoder and the sense circuit. A memory cell array including a plurality of memory cells;
An access control circuit for performing an access operation on the memory cell array;
An internal power generation circuit that generates an internal voltage from an external voltage supplied from an external power supply terminal and supplies the internal voltage to the memory cell array;
The memory is activated by activating the access control circuit in response to the internal voltage supplied to the memory cell array being outside a desired range and a first reset signal supplied from the outside being changed. And a dummy access control circuit for accessing the cell array.   10. The semiconductor device according to claim 9, wherein the dummy access control circuit refreshes memory cells included in the memory cell array by supplying a refresh signal to the access control circuit.   The semiconductor device according to claim 10, wherein the dummy access control circuit supplies the refresh signal to the access control circuit a plurality of times.   The dummy access control circuit is initialized in response to a change in a second reset signal automatically generated in the semiconductor device, and is activated in response to a change in the first reset signal. The semiconductor device according to claim 11, wherein the semiconductor device is characterized in that: In addition, a power-on reset circuit that detects the input of an external power supply voltage supplied from the outside,
The semiconductor device according to claim 12, wherein the power-on reset circuit generates the second reset signal. The dummy access control circuit is:
Reset in response to activation of the second reset signal; and
14. The semiconductor device according to claim 12, wherein the semiconductor device is set in response to the internal voltage being outside a desired range and the first reset signal being activated.   15. The access control circuit according to claim 9, wherein the access control circuit is reset through the dummy access control circuit after being reset in response to the first reset signal. Semiconductor device. Generating an internal voltage from an external voltage supplied from the outside and supplying the internal voltage to the memory cell array;
Activating the access signal in response to the internal voltage not being a desired potential and a reset signal supplied from the outside;
And a step of accessing the memory cell array in response to the access signal.   The semiconductor device according to claim 16, further comprising a step of resetting an access control circuit that controls access to the memory cell array in response to the reset signal before activating the access signal. Control method.

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