JP2012015722A - Semiconductor integrated circuit and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and an operation method of the same which saves memory capacity of an external memory in which moving image data is stored.SOLUTION: A semiconductor integrated circuit 1 comprises: a reception interface 11 for receiving TS packets of MPEG; a CPU 13; an MPEG decoder 18; a memory interface 17; a bus 15; and a DMAC 12. The TSIF 11 comprises: a buffer 111; a reception interval calculation section 114 and a PES header detection section 116. In the buffer 111, TS packets are accumulated, the calculation section 114 calculates reception intervals of the TS packets. The detection section 116 detects the PES header. The DMAC 12 executes DMA transfer of the PES header and the first section of a PES payload in response to detection of the PES header by the detection section 116. The DMAC 12 executes DMA transfer of subsequent sections in response to calculation of the reception intervals by the calculation section 114.

Description

  The present invention relates to a semiconductor integrated circuit and an operating method thereof, and more particularly to a technique effective for saving the memory capacity of an external memory for storing moving image data.

  On April 1, 2006, a one-segment partial reception service “One Seg” for digital terrestrial television broadcasting, which mainly targets mobile terminals in Japan, was started. In 1Seg, the amount of information is minimized by broadcasting using one segment obtained by dividing the frequency band of 6 MHz of physical channels from 13 channels to 62 channels of digital terrestrial television broadcasting into 13 segments. Restricted. Therefore, even a terminal having a relatively small information processing capability such as a mobile terminal can be appropriately received. As a feature, data broadcasting can be received simultaneously in addition to video and audio.

  Next-generation one-segment broadcasting called ISDB-Tmm aims to realize new services such as video content download and services, as well as high-quality and high-quality stream broadcasting, compared to one-segment broadcasting. ISDB-Tmm is an abbreviation for Integrated Service Digital Broadcasting-Terrestrial for mobile multimedia.

  In digital terrestrial television broadcasting for mobile terminals, a transport stream TS (Transport Steam) compliant with the MPEG-2 international standard for moving picture coding is used, and one of the transport streams TS compliant with MPEG-2 is used. The packet is composed of 188-byte bit stream data.

  On the other hand, as described in Non-Patent Document 1 below, an audio signal and a video signal are converted into an audio elementary stream and a video elementary stream by an audio encoder and a video encoder, respectively. The audio elementary stream and the video elementary stream are respectively converted into an audio packetized elementary stream and a video packetized elementary stream by an audio packetizer and a video packetizer. An audio packetized elementary stream and a video packetized elementary stream are supplied to two inputs of the transport stream multiplexer, thereby generating a transport stream TS from the output of the transport stream multiplexer. An audio packetized elementary stream and a video packetized elementary stream are supplied to two inputs of the program stream multiplexer, thereby generating a program stream PS from the output of the program stream multiplexer.

  Program stream (PS) is assumed to be applied to data transmission and storage in an error-free environment, and since the redundancy can be reduced, digital using a powerful error correction code such as DVD Used in storage media. On the other hand, a transport stream (TS) is assumed to be applied to an environment in which data transmission errors occur, such as broadcasting and communication networks, and the redundancy is higher than that of the program stream PS. Since the transport stream can configure a plurality of programs in one stream, it can also cope with broadcasting. The program stream can have a variable rate, whereas the transport stream is used in a communication path with a fixed transmission rate.

  On the other hand, a packetized elementary stream is a basic element constituting two types of streams, a transport stream TS and a program stream PS constituting the MPEG-2 system, and an intermediate state for enabling mutual conversion. (PES: Packetized Elementary Stream) packet. The PES packet is a packet of single media information in a certain presentation unit, and is a unit for executing time management of media playback. For example, in the case of video, encoded data for one image frame is often used as one PES packet. The PES packet is a variable-length packet, and the PES header information includes a PES packet length, a PES header data length, a time stamp, scramble information, copyright information, a cyclic redundancy check (CRC), and the like. The time stamp includes a decoding time stamp (DTS) and a presentation time stamp (PTS). The decoding time stamp DTS is time information for performing a decoding operation, and the presentation time stamp PTS is time information for performing reproduction.

  A PES packet is a variable-length packet, whereas a transport stream TS used in a real-time transmission / communication system such as digital broadcasting is composed of 188-byte fixed-length TS packets. Each TS packet has a fixed header of 4 bytes, and the remaining 184 bytes are composed of an adaptation field and a payload. The most important information of the 4-byte packet header of the transport stream TS is a packet identifier (PID), which enables identification of approximately 8000 type packets by a 13-bit field. A TS packet having a packet identifier PID value of 0, 1, or 2 is a special packet including program specific information (PSI). The program specifying information PSI includes a program map table (PMT: Program Map Table) indicating packet identifiers PID of a plurality of streams constituting the program, and a program related table (corresponding to the program number and the program map table PMT). A PAT (Program Association Table), a limited access table (PAT) indicating limited reception information, and the like are included.

  One variable-length PES packet to be transferred is divided into a plurality of TS packets having the same packet identifier PID value. The start of the PES packet coincides with the start of the payload section of the TS packet in which the payload unit start indicator bit is set to “1”. The TS packet includes a 2-bit adaptation field control signal in the header of a 4-byte fixed packet. 2-bit adaptation field control values “00”, “01”, “10”, and “11” are “reserved for future use”, “remaining 184 bytes are payload only”, and “remaining”, respectively. 184 bytes of "only the adaptation field" means "the remaining 184 bytes are the adaptation field and payload".

  The adaptation field includes a program clock reference (PCR) and a stuffing byte. The program time base reference value PCR is a clock that serves as a reference for time synchronization between the MPEG-2 transmitter and the receiver. For example, when it is faster than the clock on the transmitter side than the clock on the receiver side, data overflow occurs in the primary storage buffer on the receiver side, resulting in a lack of received data. Conversely, if the clock on the receiver side is faster than the clock on the receiver side, data underflow occurs in the primary storage buffer on the receiver side, and smooth playback operation on the receiver side is impossible. It becomes.

Toshihiro Yoshimura, “Overview of MPEG-2 Systems”, Technology and Services on Broadcasting (5), Broadcast Technology no. 11, Summer 2002. PP. 16-23. (C) NHK STRLhttp: // www. nhk. or. jp / strl / publica / bt / en / le0011. pdf [Search May 23, 2010]

  Prior to the present invention, the present inventors engaged in the development of a semiconductor integrated circuit called an application processor mounted on a mobile phone terminal capable of receiving the next-generation one-segment broadcasting called ISDB-Tmm described above.

  In the next-generation one-seg broadcasting called ISDB-Tmm, it is necessary to support a video content download service. Therefore, compared to standard one-seg broadcasting, the bit rate of MPEG2-TS for next-generation one-seg broadcasting is very high. Expected to be higher.

  On the other hand, in the application processor studied by the present inventors in the development prior to the present invention, the incorporation of a direct memory access controller (DMAC) was studied. The built-in DMAC executes data transfer between the external digital TV tuner and the external memory in a low load state of the built-in CPU. When data transfer of one MPEG2-TS packet from the external digital television tuner to the external memory is completed, a direct memory access controller (DMAC) supplies a DMAC transfer completion interrupt to the built-in CPU. Therefore, the built-in CPU responds to the DMAC transfer completion interrupt, and the built-in CPU starts the analysis process of the transport stream of the received data stored in the external memory. In this way, the built-in CPU is freed from the burden of data transfer between the external digital TV tuner and the external memory, so the load on the built-in CPU can be reduced.

  On the other hand, since the bit rate of MPEG2-TS of next-generation one-seg broadcasting becomes very high compared to standard one-seg broadcasting, the present inventors have studied the problem that the amount of received data stored in the external memory is remarkably increased. It was revealed by

  That is, in the received data stored in the external memory, the audio data, video signal, and payload data such as captions of the television broadcast are information necessary for reproducing the television broadcast. However, after storing the payload data of the TS packet in which the payload unit start indicator bit is set to “1” in the external memory, the fixed number of 4 bytes of the subsequent TS packets not including the payload unit start indicator are fixed. It has been found that storing the TS header in external memory is wasteful memory and power consumption.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to save the memory capacity of an external memory for storing moving image data.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a semiconductor integrated circuit (1) according to a typical embodiment of the present invention includes a reception interface (11), a central processing unit (13), an MPEG decoder (18), a memory interface (17), a bus (15), A direct memory access controller (12) is provided.

  The reception interface (11), the central processing unit (13), the MPEG decoder (18), the memory interface (17), and the direct memory access controller (12) are connected to the bus (15).

  The memory interface (17) is connected to an external memory (7).

  The receiving interface (11) receives a number of TS packets included in an MPEG transport stream, the number of TS packets including a plurality of TS packets having the same bucket identifier (PID), and the same bucket The plurality of TS packets having an identifier (PID) constitute one packetized elementary stream packet.

  The reception interface (11) includes a buffer (111), a reception interval calculation unit (113), and a PES header detection unit (116), and the buffer stores at least one TS packet included in the plurality of TS packets. The reception interval calculation unit calculates reception intervals of the plurality of TS packets received by the reception interface, and the PES header detection unit calculates the PES included in the one packetized elementary stream packet. Detect headers.

  First TS packets of the plurality of TS packets are stored in the buffer, and in response to the detection of the PES header by the PES header detection unit (116), the reception interface first transmits to the direct memory access controller (12). Request DMA transfer.

  By the first DMA transfer by the direct memory access controller, the data of the PES header and the data of the first section of the PES payload subsequent to the PES header are transferred from the buffer (111) of the reception interface to the bus (15 ) And the memory interface (17) to the external memory (7).

  Subsequent TS packets of the plurality of TS packets are accumulated in the buffer, and in response to the calculation of the reception interval by the reception interval calculation unit (113), the reception interface follows the direct memory access controller (12). Request DMA transfer.

  Due to the subsequent DMA transfer by the direct memory access controller, data of the subsequent section of the first section of the PES payload from the buffer of the receiving interface is transferred to the external memory (via the bus and the memory interface). 7), which can be transferred (see FIG. 2).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, the memory capacity of the external memory for storing moving image data can be saved.

FIG. 1 is a diagram showing a configuration of an application processor as a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2 is a diagram showing a configuration of the transport stream interface (TSIF) 11 included in the application processor 1 shown in FIG. FIG. 3 is a diagram for explaining the DMA transfer operation executed by TSIF 11 and DMAC 12 included in application processor 1 configured as the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 4 is a diagram showing a structure of a TS packet of the MPEG-2 transport stream TS including a 4-byte fixed-length header analyzed by the TS header analysis unit 118 of the TSIF 11 shown in FIG. FIG. 5 is a diagram showing a configuration of an MPEG-2 PES packet including a PES header detected by the PES header detection unit 116 of the TSIF 11 shown in FIG. FIG. 6 shows a PES header detector 116 for measuring the data rate of MPEG2-TS supplied to the TSIF 11 included in the application processor 1 as the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. FIG. 7 is a diagram showing a configuration of a mobile phone according to the second embodiment of the present invention on which the application processor 1 according to the first embodiment of the present invention shown in FIG. 1 is mounted.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical embodiment of the present invention includes a reception interface (11), a central processing unit (13), an MPEG decoder (18), a memory interface (17), a bus (15), a direct A semiconductor integrated circuit (1) including a memory access controller (12).

  The bus (15) is connected to the receiving interface (11), the central processing unit (13), the MPEG decoder (18), the memory interface (17), and the direct memory access controller (12). Yes.

  The memory interface (17) can be connected to an external memory (7).

  The reception interface (11) is capable of receiving a number of TS packets included in an MPEG transport stream, and the number of TS packets includes a plurality of TS packets having the same bucket identifier (PID). The plurality of TS packets having a bucket identifier (PID) can constitute one packetized elementary stream packet.

  The reception interface (11) includes a buffer (111), a reception interval calculation unit (113), and a PES header detection unit (116), and the buffer stores at least one TS packet included in the plurality of TS packets. The reception interval calculation unit can calculate reception intervals of the plurality of TS packets received by the reception interface, and the PES header detection unit is included in the one packetized elementary stream packet. Detected PES header.

  In response to the first TS packet of the plurality of TS packets being stored in the buffer of the reception interface and the PES header detection unit (116) of the reception interface detecting the PES header, the reception interface Request the first DMA transfer to the direct memory access controller (12).

  By the first DMA transfer by the direct memory access controller, the data of the PES header and the data of the first section of the PES payload subsequent to the PES header are transferred from the buffer (111) of the reception interface to the bus (15 And the memory interface (17) can be transferred to the external memory (7).

  Subsequent TS packets of the plurality of TS packets are accumulated in the buffer of the reception interface, and in response to the reception interval calculation unit (113) of the reception interface (11) calculating the reception interval, The reception interface requests the direct memory access controller (12) for a subsequent DMA transfer.

  Due to the subsequent DMA transfer by the direct memory access controller, data of the subsequent section of the first section of the PES payload from the buffer of the receiving interface is transferred to the external memory (via the bus and the memory interface). 7), which can be transferred (see FIG. 2).

  According to the embodiment, it is possible to save the memory capacity of the external memory that stores moving image data.

  In a preferred embodiment, the reception interface (11) further includes a time stamp adding unit (113) for adding a plurality of reception time stamps to the plurality of TS packets received by the reception interface.

  The reception interval calculation unit (113) calculates the reception interval by detecting a difference between the plurality of reception time stamps added to the plurality of TS packets (see FIG. 2).

  In another preferred embodiment, after the completion of the first DMA transfer by the direct memory access controller, the central processing unit (13) passes the bus (15) and the memory interface (17) through the memory interface (17). The external memory (7) can be accessed.

  The access enables the central processing unit to obtain decoding time stamp (DTS) information and presentation time stamp (PTS) information included in the PES header from the external memory. (See FIG. 1).

  In still another preferred embodiment, the central processing unit can supply the information of the decoding time stamp obtained from the external memory to the MPEG decoder (18). (See Figure 1).

  The semiconductor integrated circuit (1) according to a more preferred embodiment further comprises an image display control unit (14) and an audio output control unit (19) connected to the bus (15).

  The central processing unit can supply the information of the presentation time stamp acquired from the external memory to the image display control unit and the audio output control unit (see FIG. 1). .

  In another more preferred embodiment, the reception interface (11) further includes a TS header analysis unit (118) capable of receiving the multiple TS packets.

  The TS header analysis unit of the reception interface can detect whether or not a payload unit start indicator is included in each TS header of the multiple TS packets.

  In response to the detection of the payload unit start indicator by the TS header analysis unit, the TS header analysis unit starts the detection operation of the PES header by the PES header detection unit (116). Is.

  In still another more preferred embodiment, the TS header analysis unit of the reception interface includes a value of a packet identifier (PID) included in a TS header of one TS packet including the detected payload unit start indicator. Can be stored.

  The TS header analysis unit of the reception interface includes a subsequent packet identifier included in a subsequent TS header of a subsequent TS packet of the one TS packet including the payload unit start indicator and the stored packet identifier. Can be compared with the above value.

  The TS header analysis unit of the reception interface can generate a PID match detection output signal when the stored value of the packet identifier matches the subsequent packet identifier of the subsequent TS packet.

  In response to the PID match detection output signal generated from the TS header analysis unit and the reception interval calculated by the reception interval calculation unit, the reception interface sends the direct memory access controller (12) the subsequent It is characterized by requesting DMA transfer.

  In a specific embodiment, the PES header detection unit (116) of the reception interface can detect the PES header data length included in the PES header.

  The PES header detection unit is controlled to be in a sleep state after the detection operation by the PES header detection unit of the PES header having the PES header data length detected by the PES header detection unit is completed. Is.

  In a more specific embodiment, the PES header detection unit (116) of the reception interface can detect the PES packet length included in the PES header.

  Based on the PES packet length detected by the PES header detection unit, the PES header detection unit determines the number of DMA transfers necessary for transferring the data of the subsequent section from the data of the first section of the PES payload. It is characterized by being calculated.

  In the most specific embodiment, the memory interface (17) can be connected to a DRAM as the external memory (7). The semiconductor chip of the semiconductor integrated circuit (1) and the semiconductor chip of the DRAM are It is characterized in that it is built in a system-in package or a sealed package of a multi-chip module.

  [2] A typical embodiment according to another aspect of the present invention includes a reception interface (11), a central processing unit (13), an MPEG decoder (18), a memory interface (17), and a bus (15 ) And a direct memory access controller (12).

  The bus (15) is connected to the receiving interface (11), the central processing unit (13), the MPEG decoder (18), the memory interface (17), and the direct memory access controller (12). Yes.

  The memory interface (17) can be connected to an external memory (7).

  The reception interface (11) is capable of receiving a number of TS packets included in an MPEG transport stream, and the number of TS packets includes a plurality of TS packets having the same bucket identifier (PID). The plurality of TS packets having a bucket identifier (PID) can constitute one packetized elementary stream packet.

  The reception interface (11) includes a buffer (111), a reception interval calculation unit (113), and a PES header detection unit (116), and the buffer stores at least one TS packet included in the plurality of TS packets. The reception interval calculation unit can calculate reception intervals of the plurality of TS packets received by the reception interface, and the PES header detection unit is included in the one packetized elementary stream packet. Detected PES header.

  In response to the first TS packet of the plurality of TS packets being stored in the buffer of the reception interface and the PES header detection unit (116) of the reception interface detecting the PES header, the reception interface Request the first DMA transfer to the direct memory access controller (12).

  By the first DMA transfer by the direct memory access controller, the data of the PES header and the data of the first section of the PES payload subsequent to the PES header are transferred from the buffer (111) of the reception interface to the bus (15 And the memory interface (17) can be transferred to the external memory (7).

  Subsequent TS packets of the plurality of TS packets are accumulated in the buffer of the reception interface, and in response to the reception interval calculation unit (113) of the reception interface (11) calculating the reception interval, The reception interface requests the direct memory access controller (12) for a subsequent DMA transfer.

  Due to the subsequent DMA transfer by the direct memory access controller, data of the subsequent section of the first section of the PES payload from the buffer of the receiving interface is transferred to the external memory (via the bus and the memory interface). 7), which can be transferred (see FIG. 2).

  According to the embodiment, it is possible to save the memory capacity of the external memory that stores moving image data.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of semiconductor integrated circuit>
FIG. 1 is a diagram showing a configuration of an application processor as a semiconductor integrated circuit according to the first embodiment of the present invention.

  1 includes a transport stream interface (hereinafter referred to as TSIF) 11, a direct memory access controller (hereinafter referred to as DMAC) 12, a central processing unit (hereinafter referred to as CPU) 13, and a liquid crystal display. A control unit 14 (hereinafter referred to as LCD), a data bus 15, a timer 16, a memory interface 17, an MPEG decoder 18, and an audio output control unit 19 are included.

  As shown in FIG. 1, a mobile phone terminal equipped with an application processor 1 includes a digital TV antenna 2, a digital TV tuner 3, a system clock generator 4, a liquid crystal display (hereinafter referred to as LCD) 5, and a speaker 6. And an external memory 7 are mounted.

  Next-generation one-segment broadcasting of ISDB-Tmm is received by the digital television antenna 2, and MPEG2-TS packet data is supplied from the output terminal of the external digital television tuner 3 to the input terminal of the TSIF 11 of the application processor 1. Furthermore, a system clock signal as a reference clock is supplied from the system clock generator 4 to the TSIF 11.

  The MPEG2-TS packet data supplied to the TSIF 11 is transferred to the external memory 7 via the data bus 15 and the memory interface 17 by DMA transfer executed by the built-in DMAC 12. As the external memory 7, a high-speed and large-capacity synchronous DRAM can be used.

  The built-in CPU 13 controls the internal operation of the application processor 1. The MPEG2-TS packet data stored in the external memory 7 is separated into a video elementary stream and an audio elementary stream by controlling the demultiplexing (DEMUX) processing by the built-in CPU 13. The separated video elementary stream and audio elementary stream are decoded by the MPEG decoder 18 into a video reproduction signal and an audio reproduction signal. Output synchronization of the video reproduction signal is executed by the LCD control unit 14, and output synchronization of the audio reproduction signal is executed by the audio output control unit 19, and the video display and the audio output can be performed by the LCD 5 and the speaker 6.

<< Structure of TSIF >>
FIG. 2 is a diagram showing a configuration of the transport stream interface (TSIF) 11 included in the application processor 1 shown in FIG.

  2 includes a time stamp adding unit 110, a TS (transport stream) buffer 111, a DMAC control unit 112, a time stamp buffer 113, a reception interval calculation unit 114, a reception interval buffer 115, and a PES. The header detection unit 116, the PES header length calculation unit 117, and the TS header analysis unit 118 are configured.

  The time stamp adding unit 110 of the TSIF 11 shown in FIG. 2 is generated from the system clock signal as the reference clock supplied from the system clock generator 4 to the MPEG2-TS packet data supplied from the output terminal of the digital television tuner 3. An operation for adding a time stamp is executed. The time stamp generated from one output terminal of the time stamp adding unit 110 is stored in the time stamp buffer 113 and further supplied to one input terminal of the reception interval calculation unit 114. On the other hand, since the previous time stamp is supplied from the output terminal of the time stamp buffer 113 to the other input terminal of the reception interval calculation unit 114, the reception interval calculation unit 114 is connected to the current time stamp of one input terminal. The reception interval of the MPEG2 TS packet is calculated by calculating a difference from the previous time stamp of the other input terminal. TS packet reception interval information generated from the output terminal of the reception interval calculation unit 114 is supplied to one input terminal of the DMAC control unit 112 via the reception interval buffer 115.

  Further, in the TSIF 11 shown in FIG. 2, the MPEG2-TS packet data supplied from the output terminal of the digital television tuner 3 is supplied to the input terminal of the PES header detection unit 116. The PES header included in the packet data can be detected. Further, the PES header detection unit 116 can detect the PES packet length and the PES header data length included in the PES header. Further, the PES header length calculation unit 117 can calculate the PES payload length by calculating the difference between the PES packet length supplied from the PES header detection unit 116 and the PES header data length. The PES header detection output signal from the PES header detection unit 116 is supplied to the other input terminal of the DMAC control unit 112 via the PES header length calculation unit 117. The other input terminal of the DMAC control unit 112 is also supplied with a PID match detection signal of a TS packet generated from the TS analysis unit 118 as described below. As a result, the DMAC control unit 112 responds to the TS packet reception interval information supplied to one input terminal, the PES header detection output signal supplied to the other input terminal, and the PID match detection signal information of the TS packet. Then, a DMA transfer request output having a DMA transfer size of 184 bytes is generated and output to the DMAC control unit 112.

  In the TSIF 11 shown in FIG. 2, the TS header analysis unit 118 analyzes the payload unit start indicator and the packet identifier PID included in the TS header of the MPEG2 TS packet supplied from the output terminal of the digital television tuner 3. When the TS header analysis unit 118 detects a payload unit start indicator in which the bit included in the TS header is set to “1”, the PES header detection unit 116 responds to the output signal of the TS header analysis unit 118 and the MPEG2- The detection operation of the PES header included in the TS packet data is started. Further, the TS header analysis unit 118 stores the value of the packet identifier PID included in the TS header of the TS packet in which the bit of the payload unit start indicator is set to “1”. Thereafter, the value of the packet identifier PID included in the TS header of a number of subsequent TS packets not including the payload unit start indicator whose bit is set to “1” is stored in the TS header analysis unit 118. When the values match, the PID match detection output signal of the TS header analysis unit 118 is supplied to the other input terminal of the DMAC control unit 112 via the PES header length calculation unit 117.

  The time stamp added by the time stamp adding unit 110 of the TSIF 11 shown in FIG. 2 is, for example, 4-byte time stamp information. Therefore, the memory capacity of the time stamp buffer 113 to which the time stamp is supplied from one output terminal of the time stamp adding unit 110 is 4 bytes. On the other hand, the MPEG2 TS packet supplied from the output terminal of the digital TV tuner 3 is composed of 188 bytes. Accordingly, the TS buffer 111 has a memory capacity of 192 bytes, which is a total of 188-byte TS packets and 4-byte time stamps. In the preferred embodiment, the TS buffer 111 is composed of two internal RAMs with a memory capacity of 192 bytes. The two internal RAMs perform an interleaving operation so that data is written from the internal RAM on the second surface with a 192-byte memory capacity while data is being written to the internal RAM on the first surface with a 192-byte memory capacity. Reading is possible. At the next timing, while data is being read from the internal RAM on the first surface having a memory capacity of 192 bytes, data can be written to the internal RAM on the second surface having a memory capacity of 192 bytes. In a more preferred embodiment, the TS buffer 111 is constituted by four or more built-in RAMs having a memory capacity of 192 bytes capable of executing an interleave operation.

<< DMA transfer operation >>
FIG. 3 is a diagram for explaining the DMA transfer operation executed by TSIF 11 and DMAC 12 included in application processor 1 configured as the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  As shown in the upper part of FIG. 3, the MPEG2 188-byte fixed-length TS packet supplied from the output terminal of the digital television tuner 3 includes a 4-byte fixed-length TS header (TS header). Each TS header of a plurality of TS packets includes a packet identifier PID, and a bit is set to “1” in the TS header of a TS packet including a payload unit section first in a plurality of TS packets having the same packet identifier PID value. A payload unit start indicator is included.

  As shown in the middle part of FIG. 3, time stamp information is added to the head of the TS header of each TS packet in the time stamp adding part 110 of the TSIF 11 shown in FIG. That is, the time stamp information added to the head of the TS header of each TS packet indicates the reception timing of each TS packet at the TSIF 11. Thus, a 4-byte fixed-length time stamp and a 4-byte fixed-length TS header are added to the head of each 184-byte fixed-length TS payload (TS payload).

  Therefore, the difference between the time stamps at the beginning of the TS headers of a plurality of TS packets is the TS packet reception interval. This TS packet reception interval can be calculated by the reception interval calculation unit 114 of the TSIF 11 shown in FIG.

  3, the TSIF 11 included in the application processor 1 configured as a semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1 after being temporarily stored in the TS buffer 111 of the TSIF 11 shown in FIG. One PES packet transferred to the external memory 7 by the DMA transfer operation executed by the DMAC 12 is shown.

  A PES header is added to the head of the PES payload included in one PES packet. This PES header includes important information of the decoding time stamp DTS and the presentation time stamp PTS. That is, the decoding time stamp DTS determines the timing of the video decoding operation and the audio decoding operation in the MPEG decoder 18 included in the application processor 1 of FIG. The presentation time stamp PTS determines the timing of the video output of the LCD control unit 14 and the audio output of the audio output control unit 19 included in the application processor 1 of FIG. Also, the information of the PES header (PES header) and the first section of the PES payload (PES payload) included in one PES packet is a total of 184 bytes, and the payload unit start with the bit set to “1” It is generated from the information of a fixed-length TS payload of 184 bytes of the first TS packet including the indicator.

<< First PES packet transfer by DMA >>
As described above, when the TS header analysis unit 118 detects the payload unit start indicator in which the bit included in the TS header is set to “1”, the PES header detection unit 116 outputs the output signal of the TS header analysis unit 118 to the output signal. In response, the PES header detection operation included in the payload data of the first TS packet is started. Accordingly, the PES header detection unit 116 detects the PES header included in the PES packet, and the PES packet detection output signal is supplied to the other input terminal of the DMAC control unit 112 via the PES header length calculation unit 117. When the detection operation of the PES header having the PES header data length detected by the PES header detection unit 116 is completed by the PES header detection unit, the PES header detection unit 116 is set in the sleep state after that, as shown in FIG. The power consumption of the TSIF 11 is reduced.

  As a result, the DMAC control unit 112 supplies the first DMA transfer request output to the built-in DMAC 12 included in the application processor 1 shown in FIG. That is, by the first DMA transfer request output, the information of the PES header (PES header) and the information of the first section of the PES payload included in one PES packet are shown in FIG. The data is transferred from the TS buffer 111 of the TSIF 11 shown in FIG. 2 to the external memory 7 via the data bus 15 and the memory interface 17 by the built-in DMAC 12. Therefore, by the first DMA transfer of the PES packet by the built-in DMAC 12, the PES header (PES header) including important information of the decoding time stamp DTS and the presentation time stamp PTS and the PES payload (PES payload including the video information and audio information) are stored. information of the first section of the payload) is DMA-transferred from the TS buffer 111 of the TSIF 11 to the external memory 7 by the built-in DMAC 12.

<< Transfer of PES packet for the second and subsequent times by DMA >>
As described above, the reception interval calculation unit 114 of the TSIF 11 shown in FIG. 2 detects the difference between the first time stamp and the second time stamp, thereby obtaining the reception timing of the first TS packet. A reception interval is calculated between the reception timing of the subsequent second TS packet. The reception interval information calculated by the reception interval calculation unit 114 is supplied to one input terminal of the DMAC control unit 112.

  On the other hand, when the value of the packet identifier PID included in the TS header of the subsequent second TS packet matches the value of the packet identifier PID stored in the TS header analysis unit 118, the TS header analysis unit 118 outputs a PID match detection output signal. Is generated and supplied to the other input terminal of the DMAC control unit 112.

  As a result, the DMAC control unit 112 supplies the second DMA transfer request output to the built-in DMAC 12 included in the application processor 1 shown in FIG. 1 in response to the reception interval information and the PID match detection output signal. That is, by the second DMA transfer request output, a total of 184 bytes of PES not including the 4-byte time stamp information and the 4-byte fixed-length TS header from the timing of the reception interval calculated by the reception interval calculation unit 114. Data of only the information of the second section of the payload (PES payload) is transferred from the TS buffer 111 of the TSIF 11 shown in FIG. 2 to the external memory 7 via the data bus 15 and the memory interface 17 by the built-in DMAC 12. Accordingly, the data of the first section of the PES header (PES header) and the PES payload (PES payload) transferred by the first DMA transfer and the PES payload (PES payload) of 2 transferred by the second DMA transfer. There is no need to include unnecessary 4-byte fixed-length TS header information or PES header (PES header) information between the data of the second section. In this way, unnecessary memory and power consumption in the external memory 7 can be avoided.

  Similarly, there is no need between the data in the second section of the PES payload transferred by the second DMA transfer and the data in the third section of the PES payload transferred by the third DMA transfer. 4 bytes of fixed-length TS header information and PES header information are not included. Similarly, between the data of the Nth section of the PES payload transferred by the Nth DMA transfer and the data of the N + 1th section of the PES payload transferred by the (N + 1) th DMA transfer, Unnecessary 4-byte fixed-length TS header information and PES header information are not included.

《Video and audio decoding operation》
When the transfer operation of the first PES packet from the TS buffer 111 of the TSIF 11 to the external memory 7 by the internal DMAC 12 is completed, a DMAC transfer completion interrupt signal generated from the internal DMAC 12 is supplied to the internal CPU 13. In response to the DMAC transfer completion interrupt signal, the built-in CPU 13 acquires information important for video and audio decoding operations such as the decoding time stamp DTS and presentation time stamp PTS of the PES header stored in the external memory 7.

  The built-in CPU 13 performs the (N + 1) th DMA from the first section of the PES payload transferred by the first DMA transfer so that the video or audio decoding operation of the MPEG decoder 18 is executed at the timing of the decoding time stamp DTS. The built-in DMAC 12 is instructed to DMA-transfer data from the external memory 7 to the MPEG decoder 18 up to the (N + 1) th section of the PES payload transferred. Accordingly, the built-in DMAC 12 DMA-transfers data from the first section to the N + 1-th section of the PES payload from the external memory 7 to the MPEG decoder 18 by N + 1 DMA transfers. In this way, the MPEG decoder 18 can accurately execute the video or audio decoding operation at the timing of the decoding time stamp DTS supplied from the built-in CPU 13.

  The built-in CPU 13 performs LCD control in advance on the presentation time stamp PTS information acquired via the bus 15 so that the LCD control unit 14 or the audio output control unit 19 executes video display or audio output at the timing of the presentation time stamp PTS. To the unit 14 or the audio output control unit 19.

<< Configuration of TS packet >>
FIG. 4 is a diagram showing a structure of a TS packet of the MPEG-2 transport stream TS including a 4-byte fixed-length header analyzed by the TS header analysis unit 118 of the TSIF 11 shown in FIG.

  As shown in FIG. 4, a 188-byte fixed-length TS packet is composed of a 4-byte fixed-length packet header, a remaining 184-byte adaptation field (Adaptation filed) and / or a payload (payload). The

  The packet header with a fixed length of 4 bytes includes an 8-bit synchronization byte, a 1-bit transport error indicator, a 1-bit payload unit start indicator, and 1 bit. Transport priority, 13-bit packet identifier PID, 2-bit transfer scrambling control, 2-bit adaptation field control, 4-bit continuity index ) Is included.

  As described above, the value “00”, the value “01”, the value “10”, and the value “11” of the 2-bit adaptation field control are “reserved for future use” and “remaining 184 bytes are payloads”, respectively. "Only", "remaining 184 bytes are adaptation field only" and "remaining 184 bytes are adaptation field and payload". Further, the adaptation field includes a program time base reference value PCR.

<< Configuration of TS packet >>
FIG. 5 is a diagram showing a configuration of an MPEG-2 PES packet including a PES header detected by the PES header detection unit 116 of the TSIF 11 shown in FIG.

  As shown in FIG. 5, the variable-length PES packet includes a PES header (PES header) and a PES payload. The PES payload includes a plurality of sections as described above. As described above, the PES header is added only to the head of the first section of the PES payload included in one PES packet.

  PES header includes 24-bit packet start code prefix, 8-bit stream ID, 16-bit PES packet length, PES header option, stuffing Contains a byte (Stuffing byte). What is important in this PES header is the 16-bit PES packet length.

Although various information is included in the PES header option of the PES header, what is important is the PES header data length. Furthermore, various information is also included in the option field of the PES header option (PES header option) of the PES header. What is important is information on the decoding time stamp DTS and the presentation time stamp PTS.
Further, the PES header detection unit 116 included in the TSIF 11 shown in FIG. 2 detects the PES packet length included in the PES header (PES header) shown in FIG. It is possible to calculate the number of DMA transfers necessary for DMA data transfer of all data included in one PES packet shown in the lower part to the external memory 7. That is, when the PES header is detected by the PES header detection unit 116, the length of the PES packet included in the PES header is detected, and the number of DMA transfers calculated by the PES header detection unit 116 is the DMAC control of the TSIF 11 shown in FIG. The unit 112 is set.

<< Configuration of PES Header Detection Unit >>
FIG. 6 shows a PES header detector 116 for measuring the data rate of MPEG2-TS supplied to the TSIF 11 included in the application processor 1 as the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG.

  For example, if it is assumed that a moving image of one-segment broadcasting includes 15 image frames per second, the encoded data for one image frame corresponds to one PES packet, so 15 frames per second. The PES packet is supplied to the TSIF 11.

  Therefore, the register 1161 of the PES header detection unit 116 shown in FIG. 6 includes 15 memory areas. In each memory area of the 15 memory areas of the register 1161 of the PES header detection unit 116, a 16-bit (2 bytes) PES packet length (PES packet length) included in the PES header of the PES packet shown in FIG. The value of is shown.

  The first value PES packet length 0, the second value PES packet length 1, ... the fourteenth value PES packet length 13 and the fifteenth value PES packet length 14 were included in one second. The length of the PES packet corresponding to the first image frame of the 15 image frames, the length of the PES packet corresponding to the second image frame, and the length of the PES packet corresponding to the 14th image frame are 15 The PES packet length corresponding to the first image frame is shown.

  The 15 PES packet length values stored in the 15 memory areas of the register 1161 are supplied to the 15 input terminals of the adder 1164, so that they are included in 1 second from the output terminal 1163 of the adder 1164. A total value of data lengths of 15 PES packets corresponding to 15 image frames is generated.

  Since the bit rate of the transport stream TS compliant with MPEG2 of next-generation one-segment broadcasting called ISDB-Tmm is very high, the PES packet length generated from the output terminal 1163 of the adder 1164 of the PES header detection unit 116 in this case The total value of becomes a large value. Therefore, in response to the large value of the total sum of the PES packet lengths exceeding the predetermined threshold, the operation mode of the application processor 1 according to the first embodiment of the present invention shown in FIG. The operation mode is set. By setting the operation mode of the application processor 1 to the first operation mode, as shown in the lower part of FIG. 3, between the first DMA transfer and the second DMA transfer, Unnecessary information is not included between the first DMA transfer and the third DMA transfer, and between the Nth DMA transfer and the (N + 1) th DMA transfer.

  On the other hand, when a one-segment broadcast transport stream TS having a bit rate lower than the bit rate of the next-generation one-segment broadcast transport stream TS called ISDB-Tmm is received, the adder of the PES header detection unit 116 The total value of the PES packet lengths generated from the output terminal 1163 of 1164 is a small value. Accordingly, in response to the fact that the small sum of the PES packet lengths does not exceed the predetermined threshold, the operation mode of the application processor 1 according to the first embodiment of the present invention shown in FIG. Set to mode. Accordingly, when the operation mode of the application processor 1 is set as the second operation mode, information on the 4-byte TS header, information on the PES header, and the like in the intermediate period of a plurality of DMA transfers for a plurality of PES payloads. And other information can be DMA-transferred.

[Embodiment 2]
《Mobile phone with application processor》
FIG. 7 is a diagram showing a configuration of a mobile phone according to the second embodiment of the present invention on which the application processor 1 according to the first embodiment of the present invention shown in FIG. 1 is mounted.

  That is, the cellular phone according to the second embodiment of the present invention shown in FIG. 7 is one in which the application processor 1 according to the first embodiment of the present invention described in FIG. 1 is installed.

  The mobile phone of FIG. 7 includes an antenna 40, a duplexer 50, an RF analog signal processing integrated circuit 60, an RF power amplifier 70, a baseband processor 80, and an application processor 300 in order to realize the functions of the mobile phone. Actually, the media processor 33 included in the application processor 300 shown in FIG. 7 corresponds to the application processor 1 according to the first embodiment of the present invention shown in FIG.

  In addition, the mobile phone of FIG. 7 has a rod antenna 100, a one-segment terrestrial digital broadcast / tuner module 200, and an application processor 300 in order to enable one-seg terrestrial digital broadcast viewing and recording to an external nonvolatile semiconductor storage device. Is included. In other words, the one-segment terrestrial digital broadcast / tuner module 200 receives the one-segment terrestrial digital broadcast.

  Further, the LCD display device 116 connected to the application processor 300 and the audio integrated circuit 119 connected to the baseband processor 80 are used to enable the function of a mobile phone and the viewing of one-segment digital terrestrial broadcasting. The

  Although not shown, an operation device having operation keys and operation buttons is connected to the application processor 300, so that an end user operates the operation device to make a call using a mobile phone, watch a one-segment terrestrial digital broadcast, and make a reservation recording. Is possible.

《Mobile phone functions》
When the end user operates the operation device, a mobile phone call is started. The RF reception signal from the base station received by the antenna 40 is supplied to the reception signal processing unit inside the RFIC 60 via the duplexer 50. The RF reception signal is down-converted into an analog reception baseband signal by the reception signal processing unit of the RFIC 60, and the analog reception baseband signal is converted into a digital reception baseband signal by an A / D converter (not shown) inside the RFIC 60. .

  A digital reception baseband signal supplied from an A / D converter (not shown) of the RFIC 60 is subjected to demodulated signal processing by a baseband processor 80, and received audio output by D / A conversion by a D / A converter 82. A signal is generated. The received audio output signal is amplified by the audio IC 119 and then supplied to the speaker 110.

  The transmission audio input signal of the microphone 111 is amplified by the audio IC 119 and then converted into a digital signal by A / D conversion by the A / D converter 83 of the baseband processor 80, and further the modulation signal processing of the baseband processor 80 is performed. Then, it is converted into a digital transmission baseband signal. This digital transmission baseband signal is converted into an analog transmission baseband signal by D / A conversion by a D / A converter (not shown) of the RFIC 60, and the analog transmission baseband signal is RF-transmitted by the reception signal processing unit of the RFIC 60. Upconverted to signal. The RF transmission signal is amplified by the RF power amplifier 70 and then transmitted to the base station via the duplexer 50 and the antenna 40.

  An application processor 300 is connected to the one-segment digital terrestrial broadcast / tuner module 200, the baseband processor 80, and the audio IC 119.

<Application processor configuration>
The application processor 300 includes a central processing unit (CPU) 31, an external memory interface unit 32, a media processor 33, and the LCD controller 14.

  The CPU 31 includes a CPU core 311, an instruction cache memory 312, a data cache memory 313, and a built-in SRAM 314.

  The external memory interface unit 32 is connected to a first external memory interface 322 connected to a flash memory as the first external nonvolatile semiconductor storage device 112 and a synchronous dynamic random access memory as the first external volatile storage device 113. The second external memory interface 323 is included.

  The flash memory 112 can store operating system (OS) software for the basic operation of a mobile phone as a mobile terminal, and the SDRAM 113 can operate during the operation of the mobile phone and to view and listen to a one-segment terrestrial digital broadcast. Various data of the receiver that enables recording can be stored.

  The external memory interface unit 32 is further inserted into a mobile phone as a mobile terminal as a third external memory interface 324 connected to a flash memory as the second external nonvolatile semiconductor memory device 114 and an extended external nonvolatile semiconductor memory device 115. An extended external memory interface 325 connected to the connected flash memory card is included.

  The flash memory 114 can store software for various application programs of a mobile phone and a one-segment terrestrial digital broadcast receiver that can be constructed on the OS stored in the flash memory 112. The flash memory card 115 can store various data and contents that the end user designates non-volatile storage and stores in a non-volatile manner in relation to the operation of the mobile phone and the one-segment terrestrial digital broadcast receiver.

  The media processor 33 includes a transport stream interface 331 and an MPEG decoder 332. In particular, the transport stream interface 331 and the MPEG decoder 332 built in the media processor 33 correspond to the TSIF 11 and the MPEG decoder 18 built in the application processor 1 according to Embodiment 1 of the present invention shown in FIG. It is.

  On the other hand, the transport stream TS from the one-segment terrestrial digital broadcasting / tuner module 200 is digitized and multiplexed of the digital broadcasting program received by the tuner module 200, and includes MPEG compressed video information, audio information, and accompanying transmission information. Contains. The accompanying information includes an event information table in which start time, program length, program name, performer, program genre, and the like are described for each program as program identification information or program arrangement information.

《Viewing 1Seg digital terrestrial broadcast programs》
Before viewing, a one-segment digital terrestrial broadcast program can be selected by the end user operating the operation device while viewing the display of the event information table on the LCD display device 116.

  One-seg terrestrial digital broadcast program viewing is enabled by execution of the broadcast program viewing program, which is one of the application programs that can be built on the OS stored in the flash memory 112, by the application processor 300. In response to the broadcast program viewing setting, the CPU 31 of the application processor 300 instructs the one-segment digital terrestrial broadcast / tuner module 200 to receive a transport stream of the one-segment digital terrestrial broadcast program selected to be viewed.

  The transport stream TS of the one seg terrestrial digital broadcast that has been received by the selection of the program is supplied from the one seg terrestrial digital broadcast / tuner module 200 to the MPEG decoder 332 via the transport stream interface 331. The moving picture decoding process of the transport stream TS is performed by the MPEG decoder 332, the decoded moving picture data is supplied to the LCD display device 116 via the LCD controller 14, and the decoded voice data is supplied to the speaker 110 via the voice interface 19 and the audio IC 119. To be supplied. In this way, the end user can view a one-segment terrestrial digital broadcast program.

《One-segment digital terrestrial broadcast recording to external non-volatile semiconductor storage device》
Reserving recording of one-segment digital terrestrial broadcasting to an external non-volatile semiconductor storage device is one-segment digital terrestrial broadcasting in which recording is performed by operating an operation device by an end user while viewing the display of the event information table on the LCD display 116. It becomes possible by determining the program. This one-segment digital terrestrial broadcast reservation recording can also be performed by the application processor 300 executing a reservation recording program that is one of the application programs that can be constructed on the OS stored in the flash memory 112.

  When the recording reservation is set, the arrival of the start time of the program for which the recording reservation is set can be known by using a watchdog timer (not shown) of the CPU core 311 of the CPU 31 of the application processor 300 that is executing the program. .

  When the start time of the program for which the recording reservation is set is reached, the CPU 31 starts the reception of the one-seg terrestrial digital broadcast of the program for which the recording reservation is set in the one-segment terrestrial digital broadcasting / tuner module 200, and sends TS data to the transport stream interface 331. To start receiving. At the same time, the CPU 31 instructs the start of nonvolatile storage to the flash memory card 115 via the extended external memory interface 325 of the transport stream of the program whose recording reservation is set in the transport stream interface 331. With the start of non-volatile storage in the flash memory card 115, the reservation recording operation is started.

  After the reserved recording operation is started, the end time of the program for which recording reservation is set is set in a watchdog timer (not shown) of the CPU core 311 of the CPU 31 of the application processor 300 by executing the program. The program end time is calculated by adding the start time of the event information table and the program length by the CPU 31. After reaching the end time of the program for which the recording reservation is set, the CPU 31 ends the reception of the one-segment terrestrial digital broadcast of the program for which the recording reservation is set in the one-segment terrestrial digital broadcasting / tuner module 200 and the transport stream interface 331. Instructs the end of reception of TS data. At the same time, the CPU 31 instructs the transport stream interface 331 to end nonvolatile storage of the write data to the flash memory card 115 via the extended external memory interface 325.

  In addition, after the scheduled recording is completed, the flash memory card 115 is pulled out from the extended external memory interface 325 and inserted into a memory slot of a personal computer or the like outside the mobile phone, thereby using a large display screen of a personal computer or the like. You can watch videos.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the system LSI semiconductor chip of the application processor 1 and the SDRAM semiconductor chip of the external memory 7 shown in FIG. 1 are incorporated in a sealed package of a system-in-package (SIP) or multi-chip module (MCP). It is possible.

  Further, in the mobile phone shown in FIG. 7, the baseband processor 80 and the application processor 300 can be integrated in a single integrated single-chip ultra large-scale semiconductor integrated circuit.

DESCRIPTION OF SYMBOLS 1 ... Application processor 2 ... Digital television antenna 3 ... External digital television tuner 11 ... Transport stream interface 12 ... Direct memory access controller (DMAC)
13. Central processing unit (CPU)
DESCRIPTION OF SYMBOLS 14 ... LCD control part 15 ... Data bus 16 ... Timer 17 ... Memory interface 18 ... MPEG decoder 19 ... Audio | voice output control part 110 ... Time stamp addition part 111 ... TS (transport stream) buffer 112 ... DMAC control part 113 ... Time stamp Buffer 114: Reception interval calculation unit 115 ... Reception interval buffer 116 ... ES header detection unit 117 ... PES header length calculation unit 118 ... TS header analysis unit

Claims (20)

A semiconductor integrated circuit comprising a receiving interface, a central processing unit, an MPEG decoder, a memory interface, a bus, and a direct memory access controller,
The bus is connected to the reception interface, the central processing unit, the MPEG decoder, the memory interface, and the direct memory access controller.
The memory interface can be connected to an external memory,
The reception interface is capable of receiving a large number of TS packets included in an MPEG transport stream, the multiple TS packets including a plurality of TS packets having the same bucket identifier, and the plurality of TS packets having the same bucket identifier. The TS packet can constitute one packetized elementary stream packet,
The reception interface includes a buffer, a reception interval calculation unit, and a PES header detection unit. The buffer is capable of storing at least one TS packet included in the plurality of TS packets, and the reception interval calculation unit is configured to receive the reception interval. The reception interval of the plurality of TS packets received by the interface can be calculated, and the PES header detection unit can detect a PES header included in the one packetized elementary stream packet,
In response to the first TS packet of the plurality of TS packets being accumulated in the buffer of the reception interface and the PES header detection unit of the reception interface detecting the PES header, the reception interface Request the first DMA transfer to the access controller,
By the first DMA transfer by the direct memory access controller, the data of the PES header and the data of the first section of the PES payload following the PES header from the buffer of the receiving interface are transferred to the bus and the memory interface. Can be transferred to the external memory via
In response to the fact that TS packets subsequent to the plurality of TS packets are accumulated in the buffer of the reception interface, and the reception interval calculation unit of the reception interface calculates the reception interval, the reception interface receives the direct memory. Request the access controller for a subsequent DMA transfer,
By the subsequent DMA transfer by the direct memory access controller, the data of the subsequent section of the first section of the PES payload from the buffer of the receiving interface is transferred to the external memory through the bus and the memory interface. A semiconductor integrated circuit characterized in that transfer is possible. In claim 1,
The reception interface further includes a time stamp adding unit that adds a plurality of reception time stamps to the plurality of TS packets received by the reception interface,
The semiconductor integrated circuit, wherein the reception interval calculation unit calculates the reception interval by detecting a difference between the plurality of reception time stamps added to the plurality of TS packets. In claim 2,
After completion of the first DMA transfer by the direct memory access controller, the central processing unit is allowed to access the external memory via the bus and the memory interface;
The semiconductor integrated circuit according to claim 1, wherein the access enables the central processing unit to acquire information on a decoding time stamp and information on a presentation time stamp included in the PES header from the external memory. In claim 3,
The semiconductor integrated circuit according to claim 1, wherein the central processing unit can supply the information of the decoding time stamp acquired from the external memory to the MPEG decoder. In claim 4,
The semiconductor integrated circuit further comprises an image display control unit and an audio output control unit connected to the bus,
The semiconductor integrated circuit according to claim 1, wherein the central processing unit can supply the information of the presentation time stamp acquired from the external memory to the image display control unit and the audio output control unit. In claim 5,
The reception interface further includes a TS header analysis unit capable of receiving the multiple TS packets,
The TS header analysis unit of the reception interface can detect whether or not a payload unit start indicator is included in each TS header of the multiple TS packets.
In response to detection of the payload unit start indicator by the TS header analysis unit, the TS header analysis unit starts detection of the PES header by the PES header detection unit. . In claim 6,
The TS header analysis unit of the reception interface can store a value of a packet identifier included in a TS header of one TS packet including the detected payload unit start indicator,
The TS header analysis unit of the reception interface includes a subsequent packet identifier included in a subsequent TS header of a subsequent TS packet of the one TS packet including the payload unit start indicator and the stored packet identifier. Can be compared with the value of
The TS header analysis unit of the reception interface can generate a PID match detection output signal when the stored value of the packet identifier matches the subsequent packet identifier of the subsequent TS packet,
In response to the PID match detection output signal generated from the TS header analysis unit and the reception interval calculated by the reception interval calculation unit, the reception interface performs the subsequent DMA transfer to the direct memory access controller. A semiconductor integrated circuit characterized by the demand. In claim 7,
The PES header detection unit of the reception interface can detect a PES header data length included in the PES header,
The PES header detection unit is controlled to be in a sleep state after the detection operation by the PES header detection unit of the PES header having the PES header data length detected by the PES header detection unit is completed. Semiconductor integrated circuit. In claim 7,
The PES header detection unit of the reception interface is capable of detecting a PES packet length included in the PES header;
Based on the PES packet length detected by the PES header detection unit, the PES header detection unit determines the number of DMA transfers necessary for transferring the data of the subsequent section from the data of the first section of the PES payload. A semiconductor integrated circuit characterized by being calculated. In claim 6,
The memory interface can be connected to a DRAM as the external memory,
A semiconductor integrated circuit, wherein the semiconductor chip of the semiconductor integrated circuit and the semiconductor chip of the DRAM are built in a system-in-package or a sealed package of a multi-chip module. A method of operating a semiconductor integrated circuit comprising a receiving interface, a central processing unit, an MPEG decoder, a memory interface, a bus, and a direct memory access controller,
The bus is connected to the reception interface, the central processing unit, the MPEG decoder, the memory interface, and the direct memory access controller.
The memory interface can be connected to an external memory,
The reception interface is capable of receiving a large number of TS packets included in an MPEG transport stream, the multiple TS packets including a plurality of TS packets having the same bucket identifier, and the plurality of TS packets having the same bucket identifier. The TS packet can constitute one packetized elementary stream packet,
The reception interface includes a buffer, a reception interval calculation unit, and a PES header detection unit. The buffer is capable of storing at least one TS packet included in the plurality of TS packets, and the reception interval calculation unit is configured to receive the reception interval. The reception interval of the plurality of TS packets received by the interface can be calculated, and the PES header detection unit can detect a PES header included in the one packetized elementary stream packet,
In response to the first TS packet of the plurality of TS packets being accumulated in the buffer of the reception interface and the PES header detection unit of the reception interface detecting the PES header, the reception interface Request the first DMA transfer to the access controller,
By the first DMA transfer by the direct memory access controller, the data of the PES header and the data of the first section of the PES payload following the PES header from the buffer of the receiving interface are transferred to the bus and the memory interface. Can be transferred to the external memory via
In response to the fact that TS packets subsequent to the plurality of TS packets are accumulated in the buffer of the reception interface, and the reception interval calculation unit of the reception interface calculates the reception interval, the reception interface receives the direct memory. Request the access controller for a subsequent DMA transfer,
By the subsequent DMA transfer by the direct memory access controller, the data of the subsequent section of the first section of the PES payload from the buffer of the receiving interface is transferred to the external memory through the bus and the memory interface. A method for operating a semiconductor integrated circuit, wherein transfer is possible. In claim 11,
The reception interface further includes a time stamp adding unit that adds a plurality of reception time stamps to the plurality of TS packets received by the reception interface,
The operation method of a semiconductor integrated circuit, wherein the reception interval calculation unit calculates the reception interval by detecting a difference between the plurality of reception time stamps added to the plurality of TS packets. In claim 12,
After completion of the first DMA transfer by the direct memory access controller, the central processing unit is allowed to access the external memory via the bus and the memory interface;
The operation method of a semiconductor integrated circuit, wherein the access enables the central processing unit to acquire information on a decoding time stamp and information on a presentation time stamp included in the PES header from the external memory. . In claim 13,
The method of operating a semiconductor integrated circuit, wherein the central processing unit can supply the information of the decoding time stamp acquired from the external memory to the MPEG decoder. In claim 14,
The semiconductor integrated circuit further comprises an image display control unit and an audio output control unit connected to the bus,
The operation method of a semiconductor integrated circuit, wherein the central processing unit can supply the information of the presentation time stamp acquired from the external memory to the image display control unit and the audio output control unit. In claim 15,
The reception interface further includes a TS header analysis unit capable of receiving the multiple TS packets,
The TS header analysis unit of the reception interface can detect whether or not a payload unit start indicator is included in each TS header of the multiple TS packets.
In response to detection of the payload unit start indicator by the TS header analysis unit, the TS header analysis unit starts detection of the PES header by the PES header detection unit. How it works. In claim 16,
The TS header analysis unit of the reception interface can store a value of a packet identifier included in a TS header of one TS packet including the detected payload unit start indicator,
The TS header analysis unit of the reception interface includes a subsequent packet identifier included in a subsequent TS header of a subsequent TS packet of the one TS packet including the payload unit start indicator and the stored packet identifier. Can be compared with the value of
The TS header analysis unit of the reception interface can generate a PID match detection output signal when the stored value of the packet identifier matches the subsequent packet identifier of the subsequent TS packet,
In response to the PID match detection output signal generated from the TS header analysis unit and the reception interval calculated by the reception interval calculation unit, the reception interface performs the subsequent DMA transfer to the direct memory access controller. A method for operating a semiconductor integrated circuit, comprising: In claim 17,
The PES header detection unit of the reception interface can detect a PES header data length included in the PES header,
The PES header detection unit is controlled to be in a sleep state after the detection operation by the PES header detection unit of the PES header having the PES header data length detected by the PES header detection unit is completed. A method of operating a semiconductor integrated circuit. In claim 17,
The PES header detection unit of the reception interface is capable of detecting a PES packet length included in the PES header;
Based on the PES packet length detected by the PES header detection unit, the PES header detection unit determines the number of DMA transfers necessary for transferring the data of the subsequent section from the data of the first section of the PES payload. A method for operating a semiconductor integrated circuit, characterized by being calculated. In claim 17,
The memory interface can be connected to a DRAM as the external memory,
A method of operating a semiconductor integrated circuit, wherein the semiconductor chip of the semiconductor integrated circuit and the semiconductor chip of the DRAM are built in a system-in-package or a sealed package of a multi-chip module.

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