JP2012015351A - Semiconductor device - Google Patents

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JP2012015351A
JP2012015351A JP2010150958A JP2010150958A JP2012015351A JP 2012015351 A JP2012015351 A JP 2012015351A JP 2010150958 A JP2010150958 A JP 2010150958A JP 2010150958 A JP2010150958 A JP 2010150958A JP 2012015351 A JP2012015351 A JP 2012015351A
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material layer
insulating material
wire
chip
semiconductor chip
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Ken Iwakura
健 岩倉
Mitsuaki Katagiri
光昭 片桐
Satoshi Isa
聡 伊佐
Masaru Sasaki
大 佐々木
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

PROBLEM TO BE SOLVED: To provide a chip lamination type semiconductor device which can suppress capacity increase of a bonding wire extending between chips, and can prevent deterioration of high-speed operation characteristics.SOLUTION: A semiconductor device has: a first semiconductor chip 1 having a bonding pad on a front surface; an insulation material layer 3 provided on the front surface; a wire 6 that extends from a bonding pad 4 toward an outer side from a peripheral edge 1a of the first semiconductor chip while contacting with a top face of the insulation material layer 3; and a second semiconductor chip 2 whose rear surface is adhered to the front surface of the chip 1 via an adhesive material. The adhesive material consists of a DAF (Die Attach Film) 13 provided on the rear surface, and an FOW (Film Over Wire) 10 filled between the DAF 13 and the front surface of the chip 1 and the insulation material layer 3. A thickness hof the insulation material layer 3 is decided so that the capacity of the bonding wire 6 becomes the minimum value.

Description

本発明は、積層された複数の半導体チップを有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device having a plurality of stacked semiconductor chips and a method for manufacturing the same.

近年、パッケージの面積を小さくし、コストを低減する技術として複数の半導体チップを積層するマルチチップ積層パッケージ（ＭＣＰ）が注目されている。すなわち、二つの半導体チップが積層されたＭＣＰを例にとると、先ず、パッケージ基板上に第１の半導体チップがマウントされ、当該半導体チップの電極とパッケージ基板の電極とがワイヤで接続される。そして、第２の半導体チップが第１の半導体チップ上に接着剤でマウントされ、第２の半導体チップの電極とパッケージ基板の電極とがワイヤで接続される。   In recent years, a multi-chip stacked package (MCP) in which a plurality of semiconductor chips are stacked has attracted attention as a technique for reducing the area of the package and reducing the cost. That is, taking an MCP in which two semiconductor chips are stacked as an example, first, a first semiconductor chip is mounted on a package substrate, and an electrode of the semiconductor chip and an electrode of the package substrate are connected by a wire. Then, the second semiconductor chip is mounted on the first semiconductor chip with an adhesive, and the electrode of the second semiconductor chip and the electrode of the package substrate are connected by a wire.

ここで問題となるのが、下層側の半導体チップの電極から引き出されたワイヤの当該半導体チップの表面への接触である。   The problem here is the contact of the wire drawn from the electrode of the lower semiconductor chip with the surface of the semiconductor chip.

特許文献１（特開２００４−３１２００８公報）には、下層側の半導体チップの上面端部に絶縁用構造物を設けて、ワイヤと半導体チップとの間の不所望な接触を防止する技術が提案されている。   Patent Document 1 (Japanese Patent Laid-Open No. 2004-312008) proposes a technique for preventing an undesired contact between a wire and a semiconductor chip by providing an insulating structure at an upper surface end of a lower semiconductor chip. Has been.

特開２００４−３１２００８公報JP 2004-312008 A

ところで、近年の半導体装置では益々その動作スピードが増大されており、ワイヤの寄生等は可能な限り低減することが求められている。特に上記のようなＭＣＰでは、下層側の半導体チップからのワイヤは二つの半導体チップ間を通過することから寄生容量が増大し得る構成となっている。しかしながら、特許文献１はボンディングワイヤと半導体チップ間の寄生容量については全く関知していない。   By the way, the operation speed of semiconductor devices in recent years is increasing more and more, and it is required to reduce the parasitics of wires as much as possible. In particular, the MCP as described above has a configuration in which the parasitic capacitance can be increased because the wire from the lower semiconductor chip passes between the two semiconductor chips. However, Patent Document 1 is completely unaware of the parasitic capacitance between the bonding wire and the semiconductor chip.

本発明の一つの態様として、次のような半導体装置が提供される。   As one aspect of the present invention, the following semiconductor device is provided.

すなわち、この態様は、
おもて面にボンディングパッドを有する第１の半導体チップと、
前記おもて面に設けられた第１の絶縁材層と、
前記ボンディングパッドから、前記第１の絶縁材層の上面と接しながら前記第１の半導体チップの周辺エッジより外側へ延びているワイヤと、
裏面が前記おもて面と接着材を介して接着された第２の半導体チップと、を有する半導体装置であって、
該接着材が、前記裏面に設けられた第２の絶縁材層と、該第２の絶縁材層と前記おもて面および前記第１の絶縁材層との間に充填された第３の絶縁材層と、からなる半導体装置である。 That is, this aspect is
A first semiconductor chip having a bonding pad on the front surface;
A first insulating material layer provided on the front surface;
A wire extending from the bonding pad to the outside of the peripheral edge of the first semiconductor chip while being in contact with the upper surface of the first insulating material layer;
A second semiconductor chip having a back surface bonded to the front surface via an adhesive,
A second insulating material layer provided on the back surface; and a third insulating material layer filled between the second insulating material layer, the front surface, and the first insulating material layer. A semiconductor device comprising an insulating material layer.

こうした態様の半導体装置において、本発明は、
前記ワイヤを前記第１の半導体チップに投影した第１の線分の内、前記ボンディングパッドから前記第１の半導体チップの前記周辺エッジまでの長さをＬ、前記ワイヤの延在方向における前記第１の絶縁材層の一端から他端までの長さをＷ、前記第１の絶縁材層の前記周辺エッジに近い側の端から前記第１の半導体チップの前記周辺エッジまでの長さをＩｓとし、且つ、
前記第１の絶縁材層の厚さをｈs、前記第２の絶縁材層の厚さをｈf、前記第１の半導体チップのおもて面から前記第２の半導体チップの裏面までの高さをｈd、
前記ボンディングパッドにおける前記ワイヤの高さをｈ0、前記周辺エッジにおける前記第１の半導体チップのおもて面から前記ワイヤまでの高さをｈe、前記第１の絶縁材層の比誘電率をε1、前記第２の絶縁材層の比誘電率をε3、前記第３の絶縁材層の比誘電率をε2、前記ワイヤの直径をＤ、とするとき、
前記第１及び第２の半導体チップに関する前記ワイヤの容量Ｃを式（１）で定義し、 In such a semiconductor device, the present invention provides:
Of the first line segment in which the wire is projected onto the first semiconductor chip, the length from the bonding pad to the peripheral edge of the first semiconductor chip is L, and the length in the wire extending direction is the first. The length from one end of one insulating material layer to the other end is W, and the length from the end of the first insulating material layer close to the peripheral edge to the peripheral edge of the first semiconductor chip is Is. And
The thickness of the first insulating material layer is h s , and the thickness of the second insulating material layer is h f , from the front surface of the first semiconductor chip to the back surface of the second semiconductor chip. Height to h d ,
Dielectric constant of the height of the wire in the bonding pad h 0, the first semiconductor chip height h e from the front surface to the wire in the peripheral edge, said first insulating material layer Ε 1 , the relative dielectric constant of the second insulating material layer is ε 3 , the relative dielectric constant of the third insulating material layer is ε 2 , and the diameter of the wire is D,
The capacitance C of the wire relating to the first and second semiconductor chips is defined by equation (1),

Figure 2012015351
Figure 2012015351

且つ、
前記第１の絶縁材層の厚さｈsを変数とした場合の前記式（１）における前記容量Ｃが最小値から当該最小値に対して１０％増加した値までの範囲内となるように、前記第１の絶縁材層の厚さｈsが設定されていることを特徴とする。 and,
When the thickness h s of the first insulating material layer is a variable, the capacitance C in the equation (1) is in a range from a minimum value to a value increased by 10% with respect to the minimum value. The thickness h s of the first insulating material layer is set.

ここで、上記のような構造を有する半導体装置において、式（１）中の第１の絶縁材層の厚さｈｓ以外の値（チップ間距離ｈｄ等）は、製品等の規格によりほぼ決まっているケースが多い。その中で発明者は、第１の絶縁材層の厚さ、つまりボンディングワイヤの高さがどこに位置しているのかが、ボンディングワイヤに関する寄生容量に大きな影響を与えると考えたため、式（１）のｈｓを変数として、第１及び第２の半導体チップに関するボンディングワイヤの容量値Ｃの最小値を求めるに至った。   Here, in the semiconductor device having the structure as described above, values other than the thickness hs of the first insulating material layer in the formula (1) (interchip distance hd, etc.) are almost determined by the standard of the product or the like. There are many cases. The inventor considered that the position of the thickness of the first insulating material layer, that is, the height of the bonding wire, greatly affects the parasitic capacitance related to the bonding wire. The minimum value of the capacitance value C of the bonding wire related to the first and second semiconductor chips has been obtained using hs as a variable.

このように本願発明は、チップ積層型デバイスにおいて、第１の半導体チップ（下層チップ）上に絶縁材層が設けられていることにより、ボンディングワイヤのたるみ等によるワイヤ変形を防止することができる。それだけでなく本願発明は、該絶縁材層の厚さが、第１及び第２の半導体チップに関するボンディングワイヤの容量を表す数式を用いて該容量が該数式で求めた最小値に対して１０％増加した値までの範囲内となる厚さにされていることで、ボンディングワイヤに関する容量増大を抑制でき、高速動作特性の悪化を防止できる。   Thus, according to the present invention, in the chip stack type device, the insulating material layer is provided on the first semiconductor chip (lower layer chip), so that wire deformation due to slack of the bonding wire or the like can be prevented. In addition, according to the present invention, the thickness of the insulating material layer is 10% of the minimum value obtained by the mathematical formula using the mathematical formula representing the capacitance of the bonding wire with respect to the first and second semiconductor chips. By setting the thickness within the range up to the increased value, it is possible to suppress an increase in capacity related to the bonding wire and prevent deterioration of high-speed operation characteristics.

本発明の第１実施形態による半導体装置を示す側断面図。1 is a side sectional view showing a semiconductor device according to a first embodiment of the present invention. 図１の配線基板と第１のチップをワイヤボンディングした状態を表した平面図。The top view showing the state which wire-bonded the wiring board of FIG. 1, and the 1st chip | tip. 図２のＡ−Ａ’線で切断した半導体装置の断面拡大図。FIG. 3 is an enlarged cross-sectional view of the semiconductor device taken along line A-A ′ of FIG. 2. 本発明の半導体装置において、ボンディングワイヤの容量Ｃを規定する式（１）の絶縁材層の厚さｈsを変数として、式（１）に表１の値を代入し、計算した結果を示すグラフ。In the semiconductor device of the present invention, the calculation results obtained by substituting the values in Table 1 into Equation (1) using the thickness h s of the insulating material layer of Equation (1) defining the capacitance C of the bonding wire as a variable are shown. Graph.

図１を参照すると、本発明の第１の実施形態による半導体装置は、積層された二つの半導体チップ１、２（以下、単に、チップと呼ぶ。）を有するＭＣＰとして示されている。特に本実施形態では、両チップ１、２とも、ＤＲＡＭチップである。下層側の第１のチップ１は、配線基板５上に接着材により接着（マウント）されている。図２は配線基板５と第１のチップ１をワイヤボンディングした状態での平面図を表すもので、チップ１上面の中央領域に、２列に配列されたボンディングパッド（電極）４を有している。各ボンディングパッ４は対応するボンディングワイヤ６の一端に接続され、その他端は、配線基板５上の対応する端子７上に接続されている。端子７はボンディングパッドとして使用される電極である。配線基板５の裏面には、プリント基板等のマザーボードに搭載接続するためのバンプ電極９（例えば半田ボール）が設けられている。   Referring to FIG. 1, the semiconductor device according to the first embodiment of the present invention is shown as an MCP having two stacked semiconductor chips 1 and 2 (hereinafter simply referred to as chips). In particular, in this embodiment, both chips 1 and 2 are DRAM chips. The first chip 1 on the lower layer side is bonded (mounted) on the wiring substrate 5 with an adhesive. FIG. 2 is a plan view showing a state in which the wiring substrate 5 and the first chip 1 are wire-bonded, and has bonding pads (electrodes) 4 arranged in two rows in the central region of the upper surface of the chip 1. Yes. Each bonding pad 4 is connected to one end of a corresponding bonding wire 6, and the other end is connected to a corresponding terminal 7 on the wiring substrate 5. The terminal 7 is an electrode used as a bonding pad. Bump electrodes 9 (for example, solder balls) for mounting and connecting to a mother board such as a printed circuit board are provided on the back surface of the wiring board 5.

そして、本発明の特徴の一つに従って、第１のチップ１の上面にはワイヤ位置を規定する一対の絶縁材層３が形成されており、図１および図２に示すように、この絶縁材層３の上面と接しながら絶縁材層３上を通るようにボンディングワイヤ６がボンディングされている。これにより、ボンディングされたワイヤのたるみが防止され、ワイヤ位置が所定の高さに設定される。ここで、ボンディングワイヤ６は例えばＡｕやＣｕが用いられる。絶縁材層３としては例えばエラストマーの絶縁膜が用いられる。チップ１上に絶縁材層３を形成するには、所定厚さのエラストマーのテープ又はフィルムをチップに貼り付けたり、エラストマーのペースト材をチップ上に所定厚み塗布して硬化したりする。   In accordance with one of the features of the present invention, a pair of insulating material layers 3 for defining the wire position are formed on the upper surface of the first chip 1, and as shown in FIG. 1 and FIG. A bonding wire 6 is bonded so as to pass over the insulating material layer 3 while being in contact with the upper surface of the layer 3. Thereby, sagging of the bonded wire is prevented, and the wire position is set to a predetermined height. Here, for example, Au or Cu is used for the bonding wire 6. As the insulating material layer 3, for example, an elastomer insulating film is used. In order to form the insulating material layer 3 on the chip 1, an elastomer tape or film having a predetermined thickness is attached to the chip, or an elastomer paste material is applied to the chip with a predetermined thickness and cured.

第１のチップ１は、多層配線構造とされており、複数層の配線および、それらの配線とボンディングパッド４とを接続する複数のビアを有する。各ビアはビアホールをメタル等で充填してなる。   The first chip 1 has a multilayer wiring structure and has a plurality of layers of wirings and a plurality of vias that connect the wirings and the bonding pads 4. Each via is formed by filling a via hole with metal or the like.

第１のチップ１は、第２のチップ２も同様であるが、その上面（おもて面）が、デバイス回路を形成するべき面であり、チップ構造において最も広い面である。したがって、チップ１およびチップ２の上面はボンディングパッド４を露出する開口を有するパッシベーション膜（不図示）で覆われている。ボンディングワイヤ６はボンディングパッド４の露出面にボンディングされるが、本実施形態では、リバースボンディング方式を用いている。すなわち、チップ１の各ボンディングパッド４に、予め、ボンディングワイヤ６となる金線または銅線の先端部分を用いてバンプを設けておく。そして、ボンディングワイヤ６を配線基板５の端子７に最初にボンディングし、その後、絶縁材層３上を通過するようにボンディングワイヤ６を延長して、各ボンディングパッド４上のバンプにボンディングさせて切断している。かくして、絶縁材層３とボンディングパッド４および端子７との距離を小さく出来、面積の縮小も果たしている。上層側の第２のチップ２に対するワイヤボンディングも同様にリバースボンディング方式が用いられている。   The first chip 1 is the same as the second chip 2, but its upper surface (front surface) is a surface on which a device circuit is to be formed, and is the widest surface in the chip structure. Therefore, the upper surfaces of the chip 1 and the chip 2 are covered with a passivation film (not shown) having an opening for exposing the bonding pad 4. The bonding wire 6 is bonded to the exposed surface of the bonding pad 4. In this embodiment, a reverse bonding method is used. That is, bumps are provided in advance on the bonding pads 4 of the chip 1 by using the tips of gold wires or copper wires to be the bonding wires 6. Then, the bonding wire 6 is first bonded to the terminal 7 of the wiring board 5, and then the bonding wire 6 is extended so as to pass over the insulating material layer 3 and bonded to the bumps on the bonding pads 4 and cut. is doing. Thus, the distance between the insulating material layer 3, the bonding pad 4 and the terminal 7 can be reduced, and the area can be reduced. Similarly, reverse bonding is used for wire bonding to the second chip 2 on the upper layer side.

こうしたワイヤボンディング時には、ボンディングワイヤ６を絶縁材層３の上面と接触するように、ボンディングする必要はない。それは、チップ１にチップ２を積層した際の荷重により、ボンディングワイヤ６は結果的に絶縁材層３の上面に接触するからである。   During such wire bonding, it is not necessary to perform bonding so that the bonding wire 6 is in contact with the upper surface of the insulating material layer 3. This is because the bonding wire 6 comes into contact with the upper surface of the insulating material layer 3 as a result of the load when the chip 2 is stacked on the chip 1.

すなわち、第２のチップ２の裏面には絶縁性樹脂のＤＡＦ（ダイアタッチフィルム）１３が設けられ、その上に絶縁性樹脂でなるフィルム・オーバー・ワイヤ（Film Over Wire：ＦＯＷ）１０が塗布され、そして、ＦＯＷ１０が複数の絶縁材層３間のギャップを埋めるように、第２のチップ２が第１のチップ１に積層される。このとき、第１のチップ１の上面と第２のチップ２の裏面との間が所望の間隔になるように、ＦＯＷ１０とＤＡＦ１３の厚さが調整される。かくして、ボンディングワイヤ６は絶縁材層３の上面に接触して、両チップ１，２の間の所定の高さに位置することが可能となる。なお、絶縁材層３とＦＯＷ１０は、大きな意味ではお互いに樹脂ではあるが、その材質は互いに異なるものである。   That is, an insulating resin DAF (die attach film) 13 is provided on the back surface of the second chip 2, and a film over wire (FOW) 10 made of an insulating resin is applied thereon. Then, the second chip 2 is stacked on the first chip 1 so that the FOW 10 fills the gaps between the plurality of insulating material layers 3. At this time, the thicknesses of the FOW 10 and the DAF 13 are adjusted so that a desired distance is formed between the upper surface of the first chip 1 and the back surface of the second chip 2. Thus, the bonding wire 6 can contact the upper surface of the insulating material layer 3 and be positioned at a predetermined height between the two chips 1 and 2. Insulating material layer 3 and FOW 10 are resins in a large sense, but their materials are different from each other.

上側の第２のチップ２にも、同様に、ボンディングワイヤ１２を支持する部材としてのコーティング材８が設けられている。このコーティング材８は、チップ２のボンディングパッド１４と配線基板５上の端子７とをボンディングワイヤ１２によって接続した後に、溶融状態でボンディングワイヤ１２の上方から塗布される。塗布後、硬化することで、ボンディングワイヤ１２は、コーティング材８内にその一部が埋設されるようにして固定保持される。   Similarly, the upper second chip 2 is provided with a coating material 8 as a member for supporting the bonding wire 12. The coating material 8 is applied from above the bonding wire 12 in a molten state after the bonding pad 14 of the chip 2 and the terminal 7 on the wiring substrate 5 are connected by the bonding wire 12. By curing after application, the bonding wire 12 is fixed and held so that a part of the bonding wire 12 is embedded in the coating material 8.

最後に、積層された二つのチップ１，２の周りにモールドレジン１１が施され、ＭＣＰとして半導体装置が完成する。   Finally, a mold resin 11 is applied around the two stacked chips 1 and 2 to complete a semiconductor device as an MCP.

このように本実施形態の半導体装置は、配線基板５と、第１のチップ１と、第２のチップ２とを有する。第１のチップ１は配線基板５上に積層され、第２のチップ２は第１のチップ１上に積層されている。第１のチップ１はダイボンド材により配線基板５上に接合されている。第２のチップ２の裏面には絶縁膜のＤＡＦ１３が設けられており、第１のチップ１とＤＡＦ１３との間には絶縁膜を成すＦＯＷ１０が充填されている。第１のチップ１の上面には絶縁材層３が設けられており、絶縁材層３の上面と接するように、第１のチップ１のボンディングパッド４と配線基板５の端子７とを接続するボンディングワイヤ６が延在している。   As described above, the semiconductor device of the present embodiment includes the wiring substrate 5, the first chip 1, and the second chip 2. The first chip 1 is stacked on the wiring substrate 5, and the second chip 2 is stacked on the first chip 1. The first chip 1 is bonded onto the wiring substrate 5 with a die bond material. An insulating film DAF 13 is provided on the back surface of the second chip 2, and a FOW 10 forming an insulating film is filled between the first chip 1 and the DAF 13. An insulating material layer 3 is provided on the upper surface of the first chip 1, and the bonding pad 4 of the first chip 1 and the terminal 7 of the wiring substrate 5 are connected so as to be in contact with the upper surface of the insulating material layer 3. The bonding wire 6 extends.

第１のチップ１上面の、複数のボンディングパッド４からなるパッド列は、２列に限られない。これらパッド列は千鳥配列としてもよい。また、ボンディングワイヤ６が接続されたチップ１の上面は、回路が形成されている半導体チップの面である。   The pad row composed of the plurality of bonding pads 4 on the upper surface of the first chip 1 is not limited to two rows. These pad rows may have a staggered arrangement. Further, the upper surface of the chip 1 to which the bonding wires 6 are connected is the surface of the semiconductor chip on which a circuit is formed.

上記した本実施形態の半導体装置はボンディングワイヤ６がチップ１上を通過しているためボンディングワイヤ６にはある容量が寄生している。このワイヤ６の寄生容量の増大は半導体装置の高速動作特性の悪化に繋がる。   In the semiconductor device of the present embodiment described above, since the bonding wire 6 passes over the chip 1, a certain capacitance is parasitic on the bonding wire 6. This increase in the parasitic capacitance of the wire 6 leads to deterioration of the high-speed operation characteristics of the semiconductor device.

そこで、本実施形態の半導体装置において、以下のような条件で、両チップ１及び２に関するボンディングワイヤ６の容量を最小にしている。   Therefore, in the semiconductor device of this embodiment, the capacity of the bonding wire 6 relating to both the chips 1 and 2 is minimized under the following conditions.

すなわち、図３に図２のＡ−Ａ’線で切断した半導体装置の断面拡大図を示すが、この図３において、符号Ｌはボンディングパッド４から、ボンディングワイヤ６が通過する第１のチップ１の周辺エッジ１ａまでの長さを指し、符号Ｗはワイヤ延在方向での絶縁材層３の幅を指し、符号ｌsは絶縁材層３の、第１のチップ１の周辺エッジ１ａに近い側の端からその周辺エッジ１ａまでの長さを指す。さらに、符号ｈdは第１のチップ１と第２のチップ２との間隔を指し、符号ｈsは絶縁材層３の厚さ（高さ）を指し、符号ｈfはダイアタッチフィルム１３の厚さを指し、符号ｈ0はボンディングワイヤ６がボンディングパッド４に接続している接続部位におけるボンディングワイヤの高さを指し、符号ｈeは第１のチップ１の周辺エッジ１ａにおける第１のチップ１からボンディングワイヤ６までの高さを指す。さらに、符号ε1は絶縁材層３の比誘電率を指し、符号ε2はＦＯＷ１０の比誘電率を指し、符号ε3はダイアタッチフィルム１３の比誘電率を指し、符号Ｄはボンディングワイヤ６の直径を指すものとする。このとき、両チップ１及び２に関するボンディングワイヤ６の容量Ｃを表す数式は、下記の式（１）のようになる。 That is, FIG. 3 shows an enlarged cross-sectional view of the semiconductor device cut along the line AA ′ in FIG. 2. In FIG. 3, reference numeral L denotes the first chip 1 through which the bonding wire 6 passes from the bonding pad 4. , W indicates the width of the insulating material layer 3 in the wire extending direction, and l s indicates that the insulating material layer 3 is close to the peripheral edge 1a of the first chip 1. The length from the side edge to the peripheral edge 1a is indicated. Further, the symbol h d indicates the distance between the first chip 1 and the second chip 2, the symbol h s indicates the thickness (height) of the insulating material layer 3, and the symbol h f indicates the die attach film 13. refers to thickness, reference numeral h 0 refers to the height of the bonding wire in the connecting portion where the bonding wire 6 is connected to the bonding pad 4, reference numeral h e first chip in the first chip 1 around the edge 1a The height from 1 to the bonding wire 6 is indicated. Further, symbol ε 1 indicates the relative dielectric constant of the insulating material layer 3, symbol ε 2 indicates the relative dielectric constant of the FOW 10, symbol ε 3 indicates the relative dielectric constant of the die attach film 13, and symbol D indicates the bonding wire 6. The diameter of At this time, a mathematical expression representing the capacitance C of the bonding wire 6 with respect to both the chips 1 and 2 is represented by the following expression (1).

Figure 2012015351
Figure 2012015351

式（１）から、絶縁材層３の厚さｈsを変数としてボンディングワイヤ６の容量が最小値となる絶縁材層３の厚さｈsを決定する。こうして求めた厚さｈsの絶縁材層３をチップ１の上面に設けることで、両チップ１及び２に関するボンディングワイヤ６の容量増大を抑制して、高速動作特性の悪化を防止することができる。 From the equation (1), the thickness h s of the insulating material layer 3 at which the capacitance of the bonding wire 6 becomes the minimum value is determined using the thickness h s of the insulating material layer 3 as a variable. By providing the insulating material layer 3 having the thickness h s thus obtained on the upper surface of the chip 1, it is possible to suppress an increase in the capacity of the bonding wire 6 with respect to both the chips 1 and 2, and to prevent deterioration of high-speed operation characteristics. .

また、両チップ１及び２に関するボンディングワイヤ６の容量値Ｃを最小にするためには、絶縁材層３の比誘電率ε1およびＦＯＷ１０の比誘電率ε2に応じて絶縁材層３の幅Ｗを決定してから、式（１）を用いて絶縁材層３の厚さｈsを決定しても良い。 Further, in order to minimize the capacitance value C of the bonding wire 6 with respect to both the chips 1 and 2, the width of the insulating material layer 3 according to the relative dielectric constant ε 1 of the insulating material layer 3 and the relative dielectric constant ε 2 of the FOW 10 After determining W, the thickness h s of the insulating material layer 3 may be determined using Equation (1).

例えば、ε1＜ε2の場合には、絶縁材層３の幅Ｗをより大きく設けることで、両チップ１及び２に関するボンディングワイヤ６の容量値Ｃがより小さくなり、一方、ε1＞ε2の場合には、絶縁材層３の幅Ｗをより小さく設けることで、両チップ１及び２に関するボンディングワイヤ６の容量値Ｃがより小さくなる。つまり、絶縁材層３の幅Ｗは、絶縁材層３の幅Ｗの上限をＷmax＝Ｌ−（α＋ｌs min）、絶縁材層３の幅Ｗの下限をＷmin（Ｗminは、ワイヤ位置を規定する役割を果たせられる絶縁材層の幅の最小値）としたとき、ε1、ε2の違い及び製造上の制約を考慮して、Ｗmin＜Ｗ＜Ｗmaxの範囲内において最適な幅Ｗである。
ここで、ε1＜ε2の場合はＷ＞ Ｌ／２を満たすこと、ε1＞ε2の場合はＷ＝Ｗminを満たすことが、両チップ１及び２に関するボンディングワイヤ６の容量値Ｃを最小化するうえで望ましい。なお、αは、図３の断面図において、絶縁材層３の幅をＷmaxにしたときの、ボンディングパッド４の位置から絶縁材層３までの長さのことである。また、ワイヤ位置を規定する役割を果たせられる絶縁材層３の幅の最小値Ｗmin は、より明確に言うと、絶縁材層３の製造上の最小加工寸法よりも大きくＬ／２よりも小さい長さである。 For example, in the case of ε 1 <ε 2 , the capacitance value C of the bonding wire 6 with respect to both the chips 1 and 2 becomes smaller by providing a larger width W of the insulating material layer 3, while ε 1 > ε. In the case of 2 , the capacitance value C of the bonding wire 6 relating to both the chips 1 and 2 becomes smaller by providing the width W of the insulating material layer 3 smaller. In other words, the width W of the insulating material layer 3 is set such that the upper limit of the width W of the insulating material layer 3 is W max = L− (α + l s min ), and the lower limit of the width W of the insulating material layer 3 is W min (W min is the wire (Minimum value of the width of the insulating material layer that can play a role of defining the position), considering the difference between ε 1 and ε 2 and manufacturing restrictions, it is optimal within the range of W min <W <W max Width W.
Here, when ε 1 <ε 2 , W> L / 2 is satisfied, and when ε 1 > ε 2 , W = W min is satisfied. The capacitance value C of the bonding wire 6 with respect to both the chips 1 and 2 It is desirable to minimize Here, α is the length from the position of the bonding pad 4 to the insulating material layer 3 when the width of the insulating material layer 3 is W max in the cross-sectional view of FIG. Further, the minimum value W min of the width of the insulating material layer 3 that can play the role of defining the wire position is more clearly stated and is larger than the minimum processing dimension in manufacturing the insulating material layer 3 and smaller than L / 2. Length.

さらに、ボンディングワイヤをボンディングする製造工程において、ボンディングワイヤ６の高さがワイヤ径（２０μｍ前後）程度のばらつきを生じることがある。従って、この点を考慮すると、両チップ１及び２に関するボンディングワイヤ６の容量値Ｃは最小値の±１０％程度の誤差が発生する。   Further, in the manufacturing process for bonding bonding wires, the height of the bonding wire 6 may vary by about the wire diameter (around 20 μm). Therefore, considering this point, the capacitance value C of the bonding wire 6 relating to both the chips 1 and 2 has an error of about ± 10% of the minimum value.

図４は、絶縁材層３の厚さｈsを変数として、式（１）に下記の表１の値（式（１）の値を仮定した値）を代入し、計算した結果を示すグラフである。絶縁材層３、ＦＯＷ１０およびダイアタッチフィルム１３の比誘電率をそれぞれ４．０として計算した場合、両チップ１及び２に関するボンディングワイヤ６の容量値が最小になる絶縁材層３の厚さｈsは、４０μｍになる。 FIG. 4 is a graph showing the calculation results obtained by substituting the values in Table 1 below (values assuming the values of Equation (1)) into Equation (1) using the thickness h s of the insulating material layer 3 as a variable. It is. When the relative dielectric constants of the insulating material layer 3, the FOW 10 and the die attach film 13 are calculated as 4.0, the thickness h s of the insulating material layer 3 at which the capacitance value of the bonding wire 6 with respect to both the chips 1 and 2 is minimized. Becomes 40 μm.

従って、表１のような条件下において、絶縁材層３、ＦＯＷ１０およびダイアタッチフィルム１３の比誘電率がそれぞれ４．０の場合には、４０μｍの厚さの絶縁材層３をチップ１の上面に設けることによって、両チップ１及び２に関するボンディングワイヤ６の容量値を最小値に抑えることができる。   Therefore, under the conditions shown in Table 1, when the dielectric constant of the insulating material layer 3, the FOW 10 and the die attach film 13 is 4.0, the insulating material layer 3 having a thickness of 40 μm is formed on the upper surface of the chip 1. By providing in, the capacitance value of the bonding wire 6 regarding both the chips 1 and 2 can be suppressed to the minimum value.

Figure 2012015351
Figure 2012015351

上で説明した本実施形態によれば、両チップ１及び２に関するボンディングワイヤ６の容量値を最小にすることができるので、信号系ボンディングワイヤで信号劣化を起こさない製品が得られる。   According to the present embodiment described above, since the capacitance value of the bonding wire 6 with respect to both the chips 1 and 2 can be minimized, a product that does not cause signal deterioration with the signal system bonding wire can be obtained.

以上、本発明の実施形態について図面をもとに説明したが、本発明の技術思想を逸脱しない範囲において、図示した構造、形に限定することなく、上記の実施形態を適宜変更し又は組み合わせて実施することは可能である。例えば、半導体チップを３つ以上で積層した場合でも、同様に適用できる。   As mentioned above, although embodiment of this invention was described based on drawing, in the range which does not deviate from the technical idea of this invention, without limiting to the illustrated structure and form, said embodiment is changed or combined suitably. It is possible to implement. For example, the present invention can be similarly applied even when three or more semiconductor chips are stacked.

１ 第１の半導体チップ
１ａ 第１の半導体チップの周辺エッジ
２ 第２の半導体チップ
３ 絶縁材層（第１の絶縁材層）
４ ボンディングパッド
５ 配線基板
６、１２ ボンディングワイヤ
７ 端子
８ コーティング材
９ 半田ボール
１０ ＦＯＷ（第３の絶縁材層）
１１ モールドレジン
１３ ＤＡＦ（第２の絶縁材層） DESCRIPTION OF SYMBOLS 1 1st semiconductor chip 1a The peripheral edge 2 of a 1st semiconductor chip 2 The 2nd semiconductor chip 3 Insulation material layer (1st insulation material layer)
4 Bonding pad 5 Wiring boards 6 and 12 Bonding wire 7 Terminal 8 Coating material 9 Solder ball 10 FOW (third insulating material layer)
11 Mold resin 13 DAF (second insulating material layer)

Claims (5)

おもて面にボンディングパッドを有する第１の半導体チップと、
前記おもて面に設けられた第１の絶縁材層と、
前記ボンディングパッドから、前記第１の絶縁材層の上面と接しながら前記第１の半導体チップの周辺エッジより外側へ延びているワイヤと、
裏面が前記おもて面と接着材を介して接着された第２の半導体チップと、を有し、
前記接着材が、前記裏面に設けられた第２の絶縁材層と、該第２の絶縁材層と前記おもて面および前記第１の絶縁材層との間に充填された第３の絶縁材層と、からなる半導体装置であって、
前記ワイヤを前記第１の半導体チップに投影した第１の線分の内、前記ボンディングパッドから前記第１の半導体チップの前記周辺エッジまでの長さをＬ、前記ワイヤの延在方向における前記第１の絶縁材層の一端から他端までの長さをＷ、前記第１の絶縁材層の前記周辺エッジに近い側の端部から前記第１の半導体チップの前記周辺エッジまでの長さをＩｓとし、且つ、
前記第１の絶縁材層の厚さをｈs、前記第２の絶縁材層の厚さをｈf、前記第１の半導体チップのおもて面から前記第２の半導体チップの裏面までの高さをｈd、
前記ボンディングパッドにおける前記ワイヤの高さをｈ0、前記周辺エッジにおける前記第１の半導体チップのおもて面から前記ワイヤまでの高さをｈe、前記第１の絶縁材層の比誘電率をε1、前記第２の絶縁材層の比誘電率をε3、前記第３の絶縁材層の比誘電率をε2、前記ワイヤの直径をＤ、とするとき、
前記第１及び第２の半導体チップに関する前記ワイヤの容量Ｃを式（１）で定義し、
Figure 2012015351
 且つ、
前記第１の絶縁材層の厚さｈsを変数とした場合の前記式（１）における前記容量Ｃが最小値から当該最小値に対して１０％増加した値までの範囲内となるように、前記第１の絶縁材層の厚さｈsが設定されていることを特徴とする半導体装置。 A first semiconductor chip having a bonding pad on the front surface;
A first insulating material layer provided on the front surface;
A wire extending from the bonding pad to the outside of the peripheral edge of the first semiconductor chip while being in contact with the upper surface of the first insulating material layer;
A second semiconductor chip having a back surface bonded to the front surface via an adhesive, and
A second insulating material layer provided on the back surface; and a third insulating material layer filled between the second insulating material layer, the front surface and the first insulating material layer. An insulating material layer, and a semiconductor device comprising:
Of the first line segment in which the wire is projected onto the first semiconductor chip, the length from the bonding pad to the peripheral edge of the first semiconductor chip is L, and the length in the wire extending direction is the first. The length from one end to the other end of one insulating material layer is W, and the length from the end portion of the first insulating material layer closer to the peripheral edge to the peripheral edge of the first semiconductor chip is Is, and
The thickness of the first insulating material layer is h s , and the thickness of the second insulating material layer is h f , from the front surface of the first semiconductor chip to the back surface of the second semiconductor chip. Height to h d ,
Dielectric constant of the height of the wire in the bonding pad h 0, the first semiconductor chip height h e from the front surface to the wire in the peripheral edge, said first insulating material layer Ε 1 , the relative dielectric constant of the second insulating material layer is ε 3 , the relative dielectric constant of the third insulating material layer is ε 2 , and the diameter of the wire is D,
The capacitance C of the wire relating to the first and second semiconductor chips is defined by equation (1),
Figure 2012015351
 and,
When the thickness h s of the first insulating material layer is a variable, the capacitance C in the equation (1) is in a range from a minimum value to a value increased by 10% with respect to the minimum value. The semiconductor device is characterized in that a thickness h s of the first insulating material layer is set. 前記第１の絶縁材層の比誘電率ε1が前記第３の絶縁材層の比誘電率ε2よりも小さいと、前記ワイヤの延在方向における前記第１の絶縁材層の一端から他端までの長さＷは、Ｗ＞ Ｌ/２ となっている、請求項１に記載の半導体装置。 When the relative dielectric constant ε 1 of the first insulating material layer is smaller than the relative dielectric constant ε 2 of the third insulating material layer, the other end of the first insulating material layer in the extending direction of the wire The semiconductor device according to claim 1, wherein a length W to the end is W> L / 2. 前記第１の絶縁材層の比誘電率ε1が前記第３の絶縁材層の比誘電率ε2よりも大きいと、前記ワイヤの延在方向における前記第１の絶縁材層の一端から他端までの長さＷは、前記第１の絶縁材層の製造上の最小加工寸法よりも大きくＬ／２よりも小さい長さとなっている、請求項１に記載の半導体装置。 When the relative dielectric constant ε 1 of the first insulating material layer is larger than the relative dielectric constant ε 2 of the third insulating material layer, the other end of the first insulating material layer in the extending direction of the wire 2. The semiconductor device according to claim 1, wherein a length W to an end is larger than a minimum processing dimension in manufacturing the first insulating material layer and smaller than L / 2. 前記ボンディングパッドは前記第１の半導体チップのおもて面の中央領域に配設されている、請求項１乃至３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the bonding pad is disposed in a central region of the front surface of the first semiconductor chip. 5. おもて面に第２のボンディングパッドを有し、該第２のボンディングパッドが設けられていない前記おもて面の一部分に前記第１の半導体チップの裏面が接着された基板をさらに備えており、
前記ワイヤは前記第２のボンディングパッドと前記第１の半導体チップのボンディングパッドとを接続している、請求項１乃至４のいずれか１項に記載の半導体装置。 And a substrate having a second bonding pad on the front surface, the back surface of the first semiconductor chip being bonded to a portion of the front surface on which the second bonding pad is not provided. And
5. The semiconductor device according to claim 1, wherein the wire connects the second bonding pad and the bonding pad of the first semiconductor chip. 6.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171819B2 (en) 2013-10-15 2015-10-27 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171819B2 (en) 2013-10-15 2015-10-27 Samsung Electronics Co., Ltd. Semiconductor package

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