JP2012014820A - Nonvolatile semiconductor memory device and data read method for the nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve power consumption by reducing current flowing a bit line when reading is performed and to avoid operation defect due to concentration of charged/discharged current.SOLUTION: A memory cell array 1 has a hierarchical structure where bit lines BL are split from a main data line MDL and an inverting sense circuit 10 is inserted between the main data line MDL and the bit lines BL. The inverting sense circuit 10 senses data of the bit lines BL when reading the data and sets so that current does not flow in either the main data line MDL on the upper layer side or the bit line BL on the lower layer side when the current flows in the other. Thus, parasitic capacitance of the bit line reduces, power consumption when reading is reduced, parasitic capacitance for charging/discharging in the case of data "1" and parasitic capacitance for charging/discharging in the case of data "0" are flattened, peak of the current is offset, and unevenness in peak current decreases.

Description

  The present invention relates to a non-volatile semiconductor memory device and a data reading method of the non-volatile semiconductor memory device, and in particular, relates to improvement of power consumption and operation failure at the time of data reading.

  A NAND flash memory is composed of a NAND string in which a plurality of memory cells having floating gates are connected in series, and selection transistors are connected to both ends thereof (for example, Non-Patent Document 1).

  FIG. 19 is a diagram showing a configuration of a NAND string arranged in such a NAND flash memory. In FIG. 19, memory cells M1, M2,..., Mn having floating gates are connected in series, and selection transistors SGD and SGS are connected to both ends thereof. The drain of the selection transistor SGD is connected to the bit line BL, and the source of the selection transistor SGS is connected to the common source line Vss.

  The gates of the memory cells M1, M2,..., Mn are connected to the word lines WL1, WL2,. The gate of the selection transistor SGD is connected to the selection signal line SELD. The gate of the selection transistor SGS is connected to the selection signal line SELS.

  The threshold value Vt of the memory cells M1, M2,..., Mn is low when the data is “1” and high when the data is “0”. At the time of data reading, the bit line BL is precharged, and among the memory cells M1, M2,..., Mn, all the unselected memory cells are turned on, and a predetermined voltage is applied to the gate of the selected memory cell. Further, the selection transistors SGD and SGS are turned on. If the selected memory cell is data “1”, the selected memory cell is turned on, a current flows through the bit line BL, and the precharged charge is discharged. As a result, the voltage of the bit line BL decreases. If the selected memory cell is data “0”, the selected memory cell is turned off, no current flows through the bit line BL, and the voltage of the bit line BL is maintained at a high level. Therefore, data can be read by sensing the voltage of the bit line BL.

“A high density NAND Flash memory technology for a silicon movie era” Sakui Toshiba Corporation Semiconductor Company

  In recent years, the parasitic capacitance of the bit line BL tends to increase as the memory capacity increases. As described above, in the conventional NAND flash memory, the bit line BL is precharged and data is read out. Therefore, when the capacity of the bit line increases, the charge / discharge current when reading the data also increases. , Power consumption increases.

  In the conventional NAND flash memory, as described above, when data is read, the current flows through the bit line BL when the data in the memory cell is “1” and the data in the memory cell is “0”. ", No current flows through the bit line BL. Thus, the current flowing through the bit line BL is unbalanced between the data “1” and the data “0”. For this reason, in the conventional NAND flash memory, when “1” data is continuous, the power consumption is remarkably increased, and the charge / discharge current of the bit line BL is concentrated, which may cause an operation failure. is there.

  In the conventional NAND flash memory, data of all memory cells is initialized to “1” at the time of shipment. For this reason, statistically, the frequency of reading data with continuous “1” is high.

  In view of the above-described problems, the present invention reduces a current flowing through a bit line at the time of reading, improves power consumption, and avoids a malfunction due to concentration of charge / discharge current and a nonvolatile semiconductor memory device It is an object of the present invention to provide a data reading method for a conductive semiconductor memory device.

  In order to solve the above problems, a nonvolatile semiconductor memory device according to the present invention includes a bit line hierarchical structure including a main data line of an upper layer and a bit line of a lower layer branched from the main data line, When reading data stored in the memory cell connected to the bit line and data stored in the memory cell, the current flow is prevented so that current does not flow in the other when the current flows in one of the main data line and the bit line. And an inverting sense circuit to be set.

  In the nonvolatile semiconductor memory device data read method according to the present invention, the bit line has a hierarchical structure including a main data line in an upper layer and a bit line in a lower layer branched from the main data line. A method of reading data from a nonvolatile semiconductor memory device in which memory cells are connected to a hierarchical bit line, wherein a phase of a current flowing through the main data line and a phase of a current flowing through the bit line are paired during data reading. It is characterized by that.

  According to the present invention, the bit line has a hierarchical structure, and when reading data, the inverting sense circuit is set so that current does not flow to the other when the current flows to the upper layer and the lower layer. As a result, the parasitic capacitance of the bit line is reduced, and the power consumption during reading can be reduced. Further, the current that is charged / discharged in the case of data “1” and the current that is charged / discharged in the case of data “0” are flattened. As a result, current peaks are canceled out, and current variations are reduced. In addition, malfunction due to voltage drop due to concentration of charge / discharge current can be avoided.

1 is a diagram showing an overall configuration of a NAND flash memory according to a first embodiment of the present invention. 1 is a diagram illustrating a configuration of a memory cell array 1 according to a first embodiment of the present invention. It is a figure which shows the structure of the main latch 6 in the 1st Embodiment of this invention. 1 is a diagram illustrating a configuration of an inverting sense circuit 10 according to a first embodiment of the present invention. FIG. 6 is a diagram showing timing waveforms at the time of reading data “1” of the NAND flash memory according to the first embodiment of the present invention. FIG. 6 is a diagram showing timing waveforms at the time of reading data “0” of the NAND flash memory according to the first embodiment of the present invention. It is explanatory drawing of the parasitic capacitance of the conventional NAND flash memory and the NAND flash memory of the 1st Embodiment of this invention. It is explanatory drawing of the charging / discharging electric current at the time of the data reading in the conventional structure which connected the NAND string to the bit line BL. It is explanatory drawing of the charging / discharging electric current at the time of the data reading in the conventional structure (however, it does not discharge in the case of data "0") which connected the NAND string to the bit line BL. It is explanatory drawing of the charging / discharging electric current at the time of the data reading in the structure which made the main data line MDL of the upper layer and the bit line BL of the lower layer hierarchical structure. Charging at the time of data reading in a structure in which the upper main data line MDL and the lower bit line BL have a hierarchical structure (however, current does not flow to the other when the current flows to one of the upper layer and the lower layer). It is explanatory drawing of a discharge current. It is explanatory drawing of the 2nd Embodiment of this invention. It is explanatory drawing of the 3rd Embodiment of this invention. It is a figure which shows the whole structure of the NAND type flash memory in the 4th Embodiment of this invention. It is a connection diagram which shows the structure of the main latch 106 in the 4th Embodiment of this invention. It is a connection diagram which shows the structure of the inversion sense circuit 100 in the 4th Embodiment of this invention. It is a figure showing an example of the internal structure of the elliptical area A of FIG. It is explanatory drawing of the parasitic capacitance of the conventional NAND type flash memory and the NAND type flash memory of the 4th Embodiment of this invention. It is a figure which shows the structure of the NAND string arrange | positioned in the conventional NAND type flash memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The case where the nonvolatile semiconductor memory device of the present invention is a NAND flash memory will be described below. However, the present invention is not limited to this, and the present invention is applied to other memories (for example, NOR flash memory) as much as possible. Such can be applied and such are also within the scope of the present invention.

<First Embodiment>
FIG. 1 is a diagram showing an overall configuration of a NAND flash memory according to the first embodiment of the present invention. The NAND flash memory according to the first embodiment of the present invention includes a memory cell array 1, a command decoder 2, an X decoder and word line driver 3, a Y decoder 4, a timing controller 5, a main latch 6, and an input. / The output controller 7 is provided at least.

  In FIG. 1, the memory cell array 1 is assumed to have NAND strings 11 arranged in a matrix. As shown in FIG. 2, NAND strings 11 arranged in the same column direction are connected to the same bit line BL branched from the main data line MDL. The main data line MDL (upper layer) and the bit line BL (lower layer) in the present invention have a structure in which conventional bit lines are hierarchized. A sub-select transistor SSEL (not shown) controls connection between the main data line MDL (upper layer) and the bit line BL (lower layer).

  The memory cells, selection transistors, and sub-select transistors SSEL in the NAND string 11 arranged in the same row have a common word line WL, a selection signal line (signal lines SELD and SELS corresponding to the selection transistor, and sub-select transistor SSEL. Is connected to the signal line SSel). In the memory cell array 1, an inversion sense circuit 10 is inserted between the main data line MDL and the bit line BL. Specifically, the output of the inversion sense circuit 10 is connected to the main data line MDL. The input of the inverting sense circuit 10 is connected to the connection node CN. The connection node CN is connected to the bit line BL via a subselect transistor SSEL (not shown).

  As shown in FIG. 1, the NAND unit including the NAND string 11, the bit line BL, the sub-select transistor SSEL (not shown), the connection node CN, and the inverting sense circuit 10 is branched from the main data line MDL. Be placed. A plurality of main data lines MDL branched from a plurality of NAND units are arranged in the row direction.

  Various commands such as a chip enable signal / CE, a write enable signal / WE, and a read enable signal / RE are input to the command decoder 2. The command decoder 2 decodes these commands and outputs them to each unit to control each unit.

  The X decoder and word line driver 3 controls the control lines in the row direction such as word lines WL and selection signal lines (signal lines SELD and SELS corresponding to selection transistors, signal lines SSEL corresponding to sub-select transistors SSEL). Do. Among the X decoder and the word line driver 3, the X decoder selects, for example, a word line WL or a selection signal line corresponding to the memory cell to be read. Among the X decoder and the word line driver 3, the word line driver supplies the word line voltage corresponding to the selection to the word line WL at the time of selection and the word line voltage at the time of non-selection to the selection signal line.

  The Y decoder 4 controls the control lines in the column direction such as the main data line MDL. At the time of data reading, for example, the main data line MDL and the bit line BL selected by the Y decoder 4 are precharged by a precharge circuit (not shown), and the data of the memory cell selected by the X decoder and the word line driver 3 are read out. It is. The precharge circuit that performs the precharge may be included in the Y decoder 4 or may be included in the inverting circuit 10, for example. The timing controller 5 generates and outputs various timing signals including the enable signal SLE of the inverting sense circuit 10. This timing signal is generated based on the command decoded by the command decoder 2, for example.

  The main latch 6 senses read data output through the main data line MDL when reading data from the memory cell array 1. The input / output controller 7 inputs / outputs data with the outside.

  FIG. 2 is a diagram for explaining the configuration of the memory cell array 1 in the first embodiment of the present invention. As shown in FIG. 2, the memory cell array 1 in the NAND flash memory according to the first embodiment of the present invention has a hierarchical structure in which a bit line BL is branched from a main data line MDL. There may be a plurality of branched bit lines BL as shown in FIG. The upper layer main data line MDL and the lower layer bit line BL are connected to each other through the inversion sense circuit 10. Specifically, the output of the inversion sense circuit 10 is connected to the main data line MDL. The input of the inverting sense circuit 10 is connected to the connection node CN. Further, as shown in FIG. 2, the connection node CN is connected to the bit line BL via the sub-select transistors SSEL0 and SSEL1.

  The inversion sense circuit 10 senses the data on the bit line BL when reading data, and when a current flows between the upper layer main data line MDL and the lower layer bit line BL, a current flows to the other side. Set the current flow so that it does not flow. In other words, the inversion sense circuit 10 inverts the current state in the bit line BL and changes the current state in the main data line MDL to the inverted state. In the present invention, inversion means that a current does not flow when a current flows, and a current flows when a current does not flow. In the present invention, the state in which no current flows is regarded as a state in which no current flows even if a slight leakage current flows. That is, it can be said that inversion is achieved in the present invention if a paired state can be created between the bit line BL and the main data line MDL. In this case, it can be said that the current flow can be set so that when the current flows through one of the main data line MDL and the bit line BL, the current does not flow through the other. Further, it can be said that the phase of the current flowing through the main data line MDL and the phase of the current flowing through the bit line BL are paired.

  Further, in the present invention, inversion means that the voltage level is low when the voltage level is high, and the high voltage level when the voltage level is low. In addition, the high level and low level of the voltage level are also in a complete sense, and the voltage level does not have to be high level and low level, but may be sensed as a paired state. In this case, in a complete sense, the main latch 6 and the inverting circuit 10 having a configuration in which a voltage level that is not a high level or a low level can be allowed and sensed as a high level or a low level may be used. In such a case as well, it can be said that the current flow can be set so that when the current flows through one of the main data line MDL and the bit line BL, no current flows through the other. Further, it can be said that the phase of the current flowing through the main data line MDL and the phase of the current flowing through the bit line BL are paired.

  The NAND string 11 is configured by connecting memory cells M1,..., Mn having floating gates in series and connecting select transistors SGD and SGS at both ends thereof. Such NAND strings 11 are arranged in a matrix in the memory cell array 1. Then, by connecting the drain of the selection transistor SGD in each NAND string 11 arranged in the same column direction to the same bit line BL, each NAND string 11 arranged in the same column direction and the bit line BL are connected. Is done. On the other hand, the source of the selection transistor SGS in each NAND string 11 arranged in the same column direction is connected to, for example, the ground voltage line Vss.

  Further, the gates of the memory cells M1,..., Mn arranged in the same row are connected to a common word line WL (word lines WL1,..., WLn), respectively. The gates of the selection transistors SGD and SGS arranged in the same row are connected to the common selection signal lines SELD and SELS, respectively. The sub-select transistors SSEL0 and SSEL1 are connection control transistors that connect / disconnect the bit line BL and the main data line MDL, which are connected to each other. By turning on one of the sub-select transistors SSEL0 and SSEL1, the corresponding bit line BL and the main data line MDL are connected via the connection node CN and the inverting circuit 10. Although not shown in FIG. 2, the gates of the sub-select transistors SSEL arranged in the same row are also connected to a common selection signal line SSel (selection signal lines SSel0, SSel1) in the same manner as described above.

  The configuration of the two bit lines BL branched from the main data line MDL as described above, the plurality of NAND strings 11 connected to the two bit lines BL, the connection node CN, and the inverting sense circuit 10 as one NAND unit is illustrated. As shown in FIG. 2, a large number can be provided on one main data line MDL. The NAND unit is not limited to the above configuration. The NAND unit may be composed of one bit line BL, a plurality of NAND strings 11 corresponding to one bit line BL, a connection node CN, and an inverting sense circuit 10, or three or more bit lines BL, three A plurality of NAND strings 11 corresponding to the bit lines BL, the connection node CN, and the inverting sense circuit 10 may be used. The memory cell array 1 in the NAND flash memory according to the first embodiment of the present invention has a configuration in which a plurality of main data lines MDL are arranged in the row direction, and a NAND unit is provided for each main data line MDL. It has become.

  As shown in FIG. 1, the enable signal MLE of the main latch 6, the enable signal SLE of the inverting sense circuit 10, and the select signal of the sub-select transistor SSEL are supplied from the timing controller 5. However, the present invention is not limited to this. It may be supplied from other parts.

  FIG. 3 is a diagram showing a configuration of the main latch 6 in the first embodiment of the present invention. As shown in FIG. 3, the main latch 6 includes a latch circuit composed of inverters 31 and 32 that sense data, and a MOS transistor 33 that captures data from the main data line MDL. The inverters 31 and 32 are connected so that their outputs are input to each other.

  The enable signal MLE is supplied from the timing controller 5 to the gate of the MOS transistor 33. When the enable signal MLE is supplied from the timing controller 5, the MOS transistor 33 is turned on. Data from the main data line MDL is sensed and latched by a latch circuit. The data inverted by the inverter 31 is output to the input / output controller 7 as data DATAB.

  FIG. 4 is a diagram showing a configuration of the inverting sense circuit 10 according to the first embodiment of the present invention. As shown in FIG. 4, the inverting sense circuit 10 includes a latch circuit composed of inverters 51 and 52 that sense data, a P-channel MOS transistor 53 that resets the latch circuit, and an N-channel that controls the enable of the latch circuit. A MOS transistor 54 and a MOS transistor 55 that outputs a signal corresponding to the voltage level of the bit line BL are configured.

  A MOS transistor 57 is provided for controlling the output of data latched by the latch circuit to the main data line MDL. The enable signal SLE is supplied to the gates of the MOS transistors 53, 54 and 57. Further, a precharge P channel MOS transistor 56 connected to a precharge power supply line (not shown) is connected to the bit line BL. The bit line BL is precharged through the precharge P channel MOS transistor 56. If the precharge P-channel MOS transistor 56 connected to the precharge power supply line is used, it is not necessary to precharge the bit line BL which is not related to the data read, so that current consumption associated with precharge can be reduced. it can.

  5 and 6 are diagrams showing timing waveforms at the time of data reading of the NAND flash memory according to the first embodiment of the present invention.

  FIG. 5 shows a case where data “1” is read. As shown in FIG. 5B, when data reading is started, the bit line BL is precharged and the voltage of the bit line BL is at a high level. Similarly, as shown in FIG. 5D, the main data line MDL is precharged, and the voltage of the main data line MDL is at a high level. Thereafter, as shown in FIG. 5A, a predetermined voltage is applied to the word line WL of the selected memory cell. At this time, when the data in the selected memory cell is “1”, the threshold value Vt of the memory cell is low, so that the selected memory cell is turned on, and as shown in FIG. As a result, the voltage of the bit line BL decreases.

  In the inverting sense circuit 10 in FIG. 4, when the enable signal SLE is at a low level, the P-channel MOS transistor 53 is turned on, and the latch circuit composed of the inverters 51 and 52 is reset. When the enable signal SLE (FIG. 5C) becomes high level, the MOS transistor 54 is turned on, and the voltage level of the bit line BL is sensed by the latch circuit including the inverters 51 and 52 via the MOS transistor 54. .

  Here, when the data in the selected memory cell is “1”, a current flows through the bit line BL, the gate voltage of the MOS transistor 55 decreases, and the MOS transistor 55 is turned off. For this reason, when the MOS transistor 54 is turned on by the enable signal SLE, a high level signal is supplied to the latch circuit composed of the inverters 51 and 52 via the MOS transistor 54, and this high level signal is sensed by the inverters 51 and 52. The The sensed high level signal is output to the main data line MDL via the MOS transistor 57. Therefore, when a current flows through the bit line BL and the voltage level of the bit line BL decreases, as shown in FIG. 5D, the main data line MDL is maintained at a high level. When the inversion sense circuit 10 is not provided, the main data line MDL has the same current when the current flows through the bit line BL as shown by the dotted line in FIG. 5D and the voltage level of the bit line BL decreases. Current flows and the voltage level drops.

  In the main latch 6 in FIG. 3, when the enable signal MLE becomes high level (FIG. 5E), the state (high level) of the main data line MDL is input to the MOS transistor 33, and a latch circuit composed of inverters 31 and 32 is provided. Sensed at. Data DATAB output to the input / output controller 7 is data obtained by further inverting the state of the main data line MDL by the inverter 31. As a result, as shown in FIG. 5F, the data DATAB output to the outside via the input / output controller 7 is fixed at the low level.

  FIG. 6 shows a case where data “0” is read. When data reading is started, as shown in FIG. 6B, the bit line BL is precharged and the voltage of the bit line BL is at a high level. Similarly, as shown in FIG. 6D, the main data line MDL is precharged, and the voltage of the main data line MDL is at a high level. Thereafter, as shown in FIG. 6A, a predetermined voltage is applied to the word line WL of the selected memory cell. At this time, when the data of the selected memory cell is “0”, the threshold value Vt of the memory cell is high, so the selected memory cell is turned off, and the voltage of the bit line BL is as shown in FIG. Maintained at a high level.

  In the inverting sense circuit 10 in FIG. 4, when the enable signal SLE is at a low level, the P-channel MOS transistor 53 is turned on, and the latch circuit composed of the inverters 51 and 52 is reset. When the enable signal SLE (FIG. 6C) becomes high level, the MOS transistor 54 is turned on, and the voltage level of the bit line BL is sensed by the latch circuit including the inverters 51 and 52 via the MOS transistor 54. .

  Here, when the data of the selected memory cell is “0”, the selected memory cell is turned off and the bit line BL is maintained at the high level, so that the MOS transistor 55 is turned on. Therefore, when the MOS transistor 54 is turned on by the enable signal SLE, a low level signal is supplied to the latch circuit composed of the inverters 51 and 52 via the MOS transistor 54, and this low level signal is sensed by the inverters 51 and 52. The The sensed low level signal is output to the main data line MDL via the MOS transistor 57. Therefore, when no current flows through the bit line BL and the voltage level of the bit line BL is maintained, as shown in FIG. 6D, the main data line MDL becomes low level. When the inversion sense circuit 10 is not provided, the main data line MDL does not flow through the bit line BL like the dotted line in FIG. 6D, and the main data line MDL is maintained when the voltage level of the bit line BL is maintained. Similarly, in MDL, no current flows and the voltage level is maintained.

  In the main latch 6 in FIG. 3, when the enable signal MLE becomes high level (FIG. 6E), the state (low level) of the main data line MDL is input to the MOS transistor 33, and the latch circuit including the inverters 31 and 32 is provided. Sensed at. Data DATAB output to the input / output controller 7 is data obtained by further inverting the state of the main data line MDL by the inverter 31. As a result, as shown in FIG. 6F, the data DATAB is fixed at the high level.

  As is apparent from the description of FIGS. 5 and 6, in the NAND flash memory according to the first embodiment of the present invention, the read data inverted in the inverting circuit 10 is further re-inverted in the main latch 6 to restore the original data. The data is returned to the read data and output. The re-inversion means for performing the re-inversion is not limited to the inverter 31 of the latch circuit in the main latch 6, and a configuration corresponding to the inverter 31 may be provided at another position. That is, the present invention includes all configurations that can perform the re-inversion.

  As described above, in the first embodiment of the present invention, the bit line structure is a hierarchical structure including the upper layer (main data line MDL) and the lower layer (bit line BL). Thereby, the parasitic capacitance of the bit line BL is reduced, and the power consumption can be reduced.

  Furthermore, in the first embodiment of the present invention, as shown in FIGS. 5 and 6, one of the upper layer (main data line MDL) and the lower layer (bit line BL) is detected by the inverting sense circuit 10. It is set so that no current flows to the other when a current flows to the other. That is, when data “1” is read, as shown in FIG. 5B, a current flows through the bit line BL, and the voltage level of the bit line BL decreases. On the other hand, when data “1” is read, as shown in FIG. 5D, no current flows through the main data line MDL, and the voltage level of the main data line MDL is maintained at a high level. When reading data “0”, as shown in FIG. 6B, no current flows through the bit line BL, and the voltage level of the bit line BL is maintained at a high level. On the other hand, when data “0” is read, as shown in FIG. 6D, a current flows through the main data line MDL, and the voltage level of the main data line MDL decreases.

  In the first embodiment of the present invention, as described above, when current flows in one of the upper layer (main data line MDL) and the lower layer (bit line BL), no current flows in the other. Therefore, it is possible to flatten the charge / discharge current between the hierarchies to reduce power consumption, and to avoid an operation failure due to concentration of the charge / discharge current.

  Next, the charge / discharge current at the time of reading in the NAND flash memory according to the first embodiment of the present invention will be considered with reference to FIG.

  In the conventional NAND type memory, as shown in FIG. 7A, a bit line BL is extended from the main latch 6, and a NAND string is connected to the bit line BL. In the example of FIG. 7A, 2048 NAND strings are connected to one bit line BL.

  FIG. 7B to FIG. 7D are examples in which the NAND type flash memory according to the first embodiment of the present invention is configured equivalently. In this configuration, as shown in FIG. 7D, the main data line MDL is extended from the main latch 6, and as shown in FIGS. 7C and 7B, a plurality of main data lines MDL are provided. Bit lines BL are branched, and a plurality of inversion sense circuits 10 are provided between the main data line MDL and each bit line BL.

  In this example, the main data line MDL is divided into four areas, and eight bit lines BL are branched from the main data line MDL in each area. The eight bit lines BL are branched so as to be nested in the upward and downward directions, respectively. As shown in FIG. 7B, 64 NAND strings are connected to each bit line BL. By adopting such a configuration, (64 × 8 × 4 = 2048) is obtained, which is equivalent to the configuration shown in FIG.

  In such a configuration, as shown in FIG. 7B, one bit line BL has 64 NAND strings. On the other hand, conventionally, as shown in FIG. 7A, one bit line BL has 2048 NAND strings. Therefore, compared to the conventional configuration, the length of the lower bit line BL can be shortened to (64/2048 = 1/32), and the parasitic capacitance is reduced accordingly.

  The upper main data line MDL has a wiring length equivalent to that of the conventional bit line BL. In the conventional configuration, the number of junctions is 2048, whereas in the first embodiment of the present invention, the main data line MDL. The number of junctions is 36, and the number of junctions is (36 / 2048≈1 / 57). Similarly, the parasitic capacitance of the junction can be reduced.

  In the first embodiment of the present invention, the inversion sense circuit 10 sets the current so that no current flows in one of the bit line BL and the main data line MDL when the current flows in the other. The parasitic capacitances before and after the inverting sense circuit 10 are compared. On the bit line BL side from the inverting sense circuit 10, the number of junctions is 64, and from the inverting sense circuit 10 to the main data line MDL side, the number of junctions is 36. Therefore, the ratio of the parasitic capacitance before and after the inverting sense circuit 10 is (64: 36 = 1.8: 1) when the parasitic capacitance of the junction is considered. Further, when comparing the wiring capacitance before and after the inverting sense circuit 10, it is (1:32). From this, the ratio of the parasitic capacitance before and after the inverting sense circuit 10 is expressed between (1.8: 1) (junction capacitance is dominant) to (1:32) (wiring capacitance is dominant). The

If the relative parasitic capacitance of the conventional bit line BL and the relative junction capacitance of the bit line BL are both defined as 32C, the relative parasitic capacitance on the bit line BL side from the inversion sense circuit 10 is the relative junction capacitance (32C / 32) of the bit line BL. And the relative wiring capacity (32C / 32) of the bit line BL. That is, the relative parasitic capacitance from the inverting sense circuit 10 to the bit line BL side is
(32C / 32) + (32C / 32) = 2C
It becomes.

The relative parasitic capacitance on the main data line MDL side from the inverting sense circuit 10 is the sum of the relative junction capacitance (32C / 57) of the main data line MDL and the relative wiring capacitance (32C / 4) of the main data line MDL. Therefore, the relative parasitic capacitance from the inverting sense circuit 10 to the main data line MDL side is
(32C / 57) + (32C / 4) = 8.5625C
It becomes. The reason why the relative wiring capacity of the main data line MDL is ¼ is that the wiring capacity is equivalent to ¼ because the main data line MDL can be arranged at a pitch of ¼ of the conventional bit line BL. From the above results, the parasitic capacitance ratio between the bit line BL and the main data line MDL in the NAND flash memory according to the first embodiment of the present invention can be considered as (1: 4).

  Next, the charge / discharge current accompanying the read operation of the NAND flash memory is compared between the conventional configuration and the configuration of the first embodiment of the present invention. Here, the configurations shown in FIGS. 8 to 11 will be compared.

  FIG. 8 shows a conventional configuration in which a NAND string is connected to the bit line BL. FIG. 9 shows a configuration in which no discharge is performed in the case of data “0” in the conventional configuration in which a NAND string is connected to the bit line BL. FIG. 10 shows a structure in which the upper layer main data line MDL and the lower layer bit line BL have a hierarchical structure. FIG. 11 shows a configuration in which the upper main data line MDL and the lower bit line BL have a hierarchical structure, and when current flows in one of the upper layer and the lower layer, no current flows in the other.

  In the following description, the relative capacitance with the parasitic capacitance of the conventional bit line BL being 32C will be described. The ratio of the parasitic capacitance between the bit line BL and the main data line MDL is (1: 4) as described above.

  As shown in FIG. 8A, in the case of the conventional configuration in which a NAND string is connected to the bit line BL, when the relative parasitic capacitance of the bit line BL is 32C, as shown in FIG. ", The charge corresponding to the relative parasitic capacitance 32C is charged / discharged. In the case of data" 0 ", the charge corresponding to the relative parasitic capacitance 32C is charged / discharged. Therefore, as shown in FIG. 8C, when the data is all “1”, a current having a charge amount corresponding to the relative parasitic capacitance 32C flows at the time of reading, and when the data is all “0”. In addition, a current having a charge amount corresponding to the relative parasitic capacitance 32C flows, and even when the data “1” and the data “0” are averaged, a current having a charge amount corresponding to the relative parasitic capacitance 32C flows.

  As shown in FIG. 9A, when the discharge is not performed with the data “0”, as shown in FIG. 9B, the charge corresponding to the relative parasitic capacitance 32C is generated in the case of the data “1”. When charging / discharging and data “0”, charging / discharging is not performed. Therefore, as shown in FIG. 9C, when the data is all “1”, a current having a charge amount corresponding to the relative parasitic capacitance 32C flows at the time of reading. Further, as shown in FIG. 9C, when the data is all “0”, no current flows, and when the data of “1” and the data of “0” are averaged (even), relative parasitics are generated. A current having a charge amount corresponding to the capacitor 16C flows.

  As shown in FIG. 10A, when the bit line has a hierarchical structure (a configuration in which no discharge is performed with data “0”), as shown in FIG. 10B, data “1”. In this case, the charge corresponding to 5C in total is added to the parasitic capacitance (1C) of the bit line BL and the parasitic capacitance (4C) of the main data line MDL, and in the case of data “0”. Charging / discharging is not performed. Therefore, as shown in FIG. 10C, when the data is all “1”, a current of a charge amount corresponding to the relative parasitic capacitance 5C flows at the time of reading, and when the data is all “0”. No current flows, and when the data of “1” and the data of “0” are averaged, a current having a charge amount corresponding to the relative parasitic capacitance of 2.5 C flows.

  As shown in FIG. 11A, when the bit line has a hierarchical structure, and when the inversion sense circuit 10 prevents current from flowing in one of the upper layer and the lower layer, no current flows in the other. As shown in FIG. 11B, in the case of data “1”, the charge corresponding to the relative parasitic capacitance 1C is charged / discharged in the bit line BL during reading, and charging / discharging is not performed in the main data line MDL. . In the case of data “0”, at the time of reading, the charge corresponding to the relative parasitic capacitance 4C is charged / discharged on the main data line MDL, and charging / discharging is not performed on the bit line BL. Therefore, as shown in FIG. 11C, when the data is all “1”, a current having a charge amount corresponding to the relative parasitic capacitance 1C flows at the time of reading, and when the data is all “0”. A current having a charge amount corresponding to the relative parasitic capacitance 4C flows. Further, when the data “1” and the data “0” are averaged, a current having a charge amount corresponding to the relative parasitic capacitance 2.5 C flows.

  Comparing the results shown in FIGS. 8 to 11, when the bit line has a hierarchical structure (FIG. 10), the parasitic capacitance at the time of reading is significantly reduced as compared with the conventional configuration (FIGS. 8 and 9). Recognize. Therefore, if the bit line has a hierarchical structure of the upper layer main data line MDL and the lower layer bit line BL, the power consumption at the time of reading can be reduced.

  Further, as shown in FIG. 11, when current flows in one of the upper layer and the lower layer and no current flows in the other, the parasitic capacitance that is charged / discharged in the case of data “1” and the data In the case of “0”, the parasitic capacitance charged and discharged is flattened. Thereby, the peak of the current is canceled out, and the variation of the peak current is reduced. For this reason, the malfunction accompanying the voltage drop by charging / discharging current can be avoided. Further, comparing the case where the bit line has only a hierarchical structure (FIG. 10) and the case where the current does not flow to the other when the current flows to the upper layer and the lower layer (FIG. 11), all In the case of “1”, the charge / discharge current decreases. In the NAND flash memory, since the frequency of data being “1” is high, a decrease in charge / discharge current in the case of all “1” leads to a reduction in overall power consumption.

<Second Embodiment>
FIG. 12 shows a second embodiment of the present invention. In this embodiment, like the first embodiment described above, the bit line BL is branched from the main data line MDL to form a hierarchical structure, and the inversion sense circuit 10 is provided between the main data line MDL and the bit line BL. Is inserted. In the second embodiment, the amplitude of the main data line MDL and the amplitude of the bit line BL are further changed.

  That is, in the second embodiment of the present invention, as shown in FIG. 12A, the bit line BL operates with an amplitude (Δ1.5V) in which the high level is 1.5V and the low level is 0V. The data line MDL operates with an amplitude (Δ0.5V) in which the high level is 0.5V and the low level is 0V, and the amplitude in the main data line MDL is smaller than the amplitude in the bit line BL. Thus, in order to make the amplitude on the main data line MDL smaller than the amplitude on the bit line BL, in this embodiment, as shown in FIG. The pull-up means precharges the bit line BL to 1.5V and reads, and the state of the bit line BL transitioned by the selection of the word line WL is set in the inverting sense circuit 10 using a 0.5V latch circuit ( By latching with the inverters 51 and 52), the amplitude of the main data line MDL is set to 0.5V. That is, the amplitude of the voltage level is converted by driving a circuit for taking in the state of the bit line BL with a 1.5V system and driving the latch circuit with a 0.5V system.

  As described above, when the amplitude at the time of reading data is changed between the bit line BL and the main data line MDL, the charge / discharge current when the read data is “1” and the charge / discharge when the read data is “0”. The current ratio can be controlled.

  That is, as shown in FIG. 11, in the first embodiment of the present invention, when data is all “1”, charge / discharge of a charge amount corresponding to the relative parasitic capacitance 1C is applied to the bit line BL at the time of reading. When the current flows and the data is all “0”, a charge / discharge current having a charge amount corresponding to the relative parasitic capacitance 4C flows through the main data line MDL. Here, the parasitic capacitance C, the voltage V, and the charge Q have a relationship of Q = CV, and the current is a differentiated charge. Therefore, if the voltage V is reduced, charging / discharging is performed accordingly. The current becomes smaller.

  As described above, when the amplitude (Δ1.5V) of the bit line BL is converted to the amplitude (Δ0.5V) of the main data line MDL, the amplitude becomes ３, so that the current flowing through the main data line MDL is a bit. One third of the current flowing through the line BL.

  As shown in FIG. 11, in the first embodiment of the present invention, when the data is all “1”, a charge / discharge current having a charge amount corresponding to the relative parasitic capacitance 1C is applied to the bit line BL during reading. Flowing. In the first embodiment of the present invention, when the data is all “0”, a charge / discharge current having a charge amount corresponding to the relative parasitic capacitance 4C flows through the main data line MDL. Therefore, in the first embodiment of the present invention, the current ratio between the case where the data is all “1” and the case where all the data is “0” is (1: 4).

  Here, when the amplitude of the bit line BL is converted to 1/3 of the amplitude of the main data line MDL, when the data is all “1”, a charge / discharge current corresponding to the relative parasitic capacitance 1C flows through the bit line BL. When the data is all “0”, the charge / discharge current corresponding to (4C × (1/3) = 4 / 3C) flows through the main data line MDL, and the data is all “1” and all “0”. The current ratio with respect to the case of "" is (1: 1.33).

  As described above, in the second embodiment of the present invention, it is possible to reduce the variation in current between when the data is all “1” and when the data is all “0”.

  Here, the amplitude (1.5 V) of the bit line BL is converted into the amplitude (0.5 V) of the main data line MDL, but the amplitude conversion ratio is not limited to this. The conversion may be performed not only so that the amplitude of the main data line MDL is smaller than the amplitude of the bit line BL, but also so that the amplitude of the bit line BL is smaller than the amplitude of the main data line MDL.

<Third Embodiment>
FIG. 13 shows a third embodiment of the present invention. In this embodiment, as in the second embodiment described above, the amplitude when data is read is changed between the bit line BL and the main data line MDL.

  In the third embodiment, as shown in FIG. 13B, in order to make the amplitude on the main data line MDL smaller than the amplitude on the bit line BL, a pulling is performed in the inverting sense circuit 10. The bit line BL is precharged to 1.5V by the up means, and reading is performed. The state of the bit line BL transitioned by the selection of the word line WL is latched by the latch circuit (inverters 51 and 52), and the gate circuit The signal is output via the MOS transistor 60. Here, by setting the level applied to the gate of the MOS transistor 60 to a small amplitude of 0.5V system, the amplitude of the main data line MDL becomes 0.5V. For example, when the threshold value Vth of the MOS transistor 60 is about 0.5 V, a voltage corresponding to 0.5 V is output to the main data line MDL when a voltage of about 1 V is applied to the gate of the MOS transistor 60. About another structure, it is the same as that of the above-mentioned 2nd Embodiment.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. FIG. 14 shows the overall configuration of a NAND flash memory according to the fourth embodiment of the present invention. The NAND flash memory according to the fourth embodiment of the present invention includes a memory cell array 101, a command decoder 102, an X decoder and word line driver 103, a Y decoder 104, a timing controller 105, a main latch 106, and an input. Output controller 107 at least. The command decoder 102, the X decoder and word line driver 103, the Y decoder 104, the timing controller 105, and the input / output controller 107 in the fourth embodiment of the present invention are the same as those in the first embodiment of the present invention. The command decoder 2, the X decoder / word line driver 3, the Y decoder 4, the timing controller 5, and the input / output controller 7 have the same functions, and have already been described above. Is omitted.

  In the memory cell array 1 of the first embodiment described above, the bit line BL branched from the main data line MDL is connected to the main data line MDL via the sub-select transistor SSEL, the connection node CN, and the inverting sense circuit 10. It was. On the other hand, in the memory cell array 101 of the fourth embodiment, the bit line BL branched from the main data line MDL is connected to the main data line MDL via the subselect transistor SSEL (not shown) and the connection node CN ′. It was set as the structure connected with. The inversion sense circuit 100 is connected to the main data line MDL in such a manner that the main data line MDL is connected / cut off between the branch point of the predetermined bit line BL in the main data line MDL and the next branch point. Has been. That is, the input of the inversion sense circuit 100 is connected to the main data line MDL extending downstream from the branch point of the predetermined bit line BL. The output of the inversion sense circuit 100 is connected to the main data line MDL downstream from itself. For the upstream and downstream, the side from the arbitrary position of the main data line MDL toward the main latch 106 is defined as downstream, and the side away from the main latch 106 at any position of the main data line MDL is defined as upstream. .

  In the memory cell array 1 of the first embodiment, since the inverting circuit 10 is interposed between the main data line MDL and the bit line BL, the inverting circuit 10 and the bit line BL (not shown) sub-select transistor are not shown. SSEL) is required. However, in the memory cell array 101 of the fourth embodiment, the main data line MDL and the bit line BL are directly connected via a sub-select transistor SSEL (not shown). For this reason, the connection node CN ′ in the memory cell array 101 of the fourth embodiment does not have to be a separate node from the main data line MDL like the memory cell array 1 of the first embodiment. In the equivalent circuit of the memory cell array 101 of the fourth embodiment of FIG. 14, the connection node CN ′ and the main data line MDL appear as separate nodes, but the connection node CN ′ in FIG. 14 is configured by the main data line MDL. You may let them. Further, the present invention includes other modes for realizing the equivalent circuit of the NAND flash memory shown in FIG. In the following description, it is assumed that the connection node CN ′ is configured by the main data line MDL.

  The NAND unit according to the fourth embodiment of the present invention includes a sub-select transistor SSEL (not shown), a bit line BL branched from the main data line MDL via the sub-select transistor SSEL (not shown), and the bit This is a combination of the NAND string 111 connected to the line BL and the inverting sense circuit 100 provided in such a manner as to connect / cut off the main data line MDL. In the fourth embodiment of the present invention, as shown in FIG. 14, a plurality of such NAND units are provided on the main data line MDL. This is the difference between the memory cell array 1 in the first embodiment of the present invention and the memory cell array 101 in the fourth embodiment of the present invention. In other points, the memory cell array 1 and the memory cell array 101 Is the same.

  FIG. 15 shows the configuration of the main latch 106 in the fourth embodiment of the present invention. As shown in FIG. 15, the main latch 106 includes a latch circuit including inverters 131 and 132 that sense data, and a MOS transistor 133 that captures data. This configuration is the same as that of the first embodiment described above.

  The operation is the same as that of the first embodiment. That is, in the NAND flash memory according to the fourth embodiment of the present invention, the read data inverted by the inverting circuit 100 is further re-inverted by the main latch 106 to return to the original read data and output. The re-inversion means for performing the re-inversion is not limited to the inverter 131 of the latch circuit in the main latch 106, and a configuration corresponding to the inverter 131 may be provided at another position. That is, the present invention includes all configurations that can perform the re-inversion.

  FIG. 16 shows a configuration of the inverting sense circuit 100 according to the fourth embodiment of the present invention. As shown in FIG. 16, the inversion sense circuit 100 includes a latch circuit composed of inverters 151 and 152 that sense data, a P-channel MOS transistor 153 that resets the latch circuit, and an N-channel that controls the latch circuit to be enabled. The MOS transistor 154 includes a MOS transistor 155 that outputs a signal corresponding to the signal level. This configuration is the same as that of the first embodiment described above. The inverting sense circuit 100 further includes a precharge P-channel MOS transistor 156, a MOS transistor 157 for controlling the output of data latched by the latch circuit to the main data line MDL, and the main data line MDL. A MOS transistor 161 which is a connection control transistor for controlling connection / cutoff and a MOS transistor 162 which is an input control transistor for controlling input of data on the main data line MDL to the inversion sense circuit 100 are provided.

  The bit line BL is precharged by the P channel MOS transistor 156 for precharging. If the precharge P-channel MOS transistor 156 is used, it is not necessary to precharge the bit line BL which is not related to the data read, so that current consumption accompanying precharge can be reduced.

  Data read from a predetermined memory cell moves from the bit line BL (not shown) to the main data line MDL via the branch point br. When the MOS transistor 162 as the input control transistor is turned on at a predetermined timing, a high level or low level signal corresponding to the data is input to the gate of the MOS transistor 155. At this time, the MOS transistor 161 as the connection control transistor is turned off. As a result, the read data does not flow further downstream without going through the inverting sense circuit 100. When the enable signal SLE becomes high level, the MOS transistor 154 is turned on.

  When the voltage level input to the gate of the MOS transistor 155 is a low level, the MOS transistor 155 is turned off, and a high level is sensed by the latch circuit including the inverters 51 and 52. That is, when the data input to the gate of the MOS transistor 155 is data corresponding to the low level, it is inverted and latched as data corresponding to the high level by the latch circuit.

  On the other hand, when the voltage level input to the gate of the MOS transistor 155 is high, the MOS transistor 155 is turned on, and the low level is sensed by the latch circuit composed of the inverters 151 and 152. That is, when the data input to the gate of the MOS transistor 155 is data corresponding to the high level, it is inverted and latched as data corresponding to the low level by the latch circuit.

  When the enable signal SLE is at a high level, the MOS transistor 157 is turned on, and the inverted data latched by the latch circuit is output to the downstream main data line MDL. As described above, data is inverted in the inversion sense circuit 100. In the first embodiment described above, the read data flows out to the main data line MDL in an inverted state. However, in the fourth embodiment, the read data is temporarily inverted without being inverted. The data flowing out to the line MDL and read in the inversion sense circuit 100 is inverted and flows to the main latch 106.

  FIG. 17 is a diagram illustrating an example of the internal configuration of the elliptical area A in FIG. As shown in FIG. 17, in each inversion sense circuit 100, the read target NAND unit and the MOS transistor 161 that is the connection control transistor upstream of the read target NAND unit are turned off, and the connection control transistor downstream of the read target NAND unit. The MOS transistor 161 is turned on. As described above, regarding the upstream and downstream, the side from the arbitrary position of the main data line MDL toward the main latch 106 is downstream, and the side away from the main latch 106 at the arbitrary position of the main data line MDL is upstream. It is defined as

  By turning off the read target NAND unit and the MOS transistor 161 of the inversion sense circuit 100 upstream from the read target NAND unit, the excess main data line MDL upstream from the read target NAND unit is electrically disconnected. Thus, it is possible to reduce the influence of the wiring capacity upstream of the read target NAND unit. Also, by turning on the MOS transistor 161 of the inverting sense circuit 100 on the downstream side of the read target NAND unit, a data transfer path from the read target NAND unit to the main latch 106 is formed.

  Next, the charge / discharge current at the time of reading in the NAND flash memory according to the fourth embodiment of the present invention will be considered with reference to FIG.

  In the conventional NAND type memory, as shown in FIG. 18A, a bit line BL is extended from the main latch 6, and a NAND string is connected to the bit line BL. In the example of FIG. 18A, 2048 NAND strings are connected to one bit line BL.

  FIGS. 18B to 18D show examples in which the NAND flash memory according to the fourth embodiment of the present invention has the same configuration as that shown in FIG. In this configuration, the main data line MDL is extended from the main latch 106 as shown in FIG. As shown in FIG. 18C, a plurality of bit lines BL are branched from the main data line MDL. As shown in FIG. 18D, in this example, the inversion sense circuit 100 is provided on the main data line MDL for each unit shown in FIG. 18C, and constitutes a NAND unit. Various units can be used to configure the NAND unit by providing the inversion sense circuit 100 on the main data line MDL for every unit, but all of them are included in the present invention.

  In this example, the main data line MDL is divided into four areas, and eight bit lines BL are branched from the main data line MDL in each area. The eight bit lines BL are branched so as to be nested in the upward and downward directions, respectively. As shown in FIG. 18B, 64 NAND strings are connected to each bit line BL. By adopting such a configuration, (64 × 8 × 4 = 2048) is obtained, which is equivalent to the configuration shown in FIG.

  In such a configuration, as shown in FIG. 18B, one bit line BL has 64 strings. On the other hand, conventionally, as shown in FIG. 18A, one bit line BL has 2048 strings. Therefore, compared to the conventional configuration, the length of the lower bit line BL can be shortened to (64/2048 = 1/32), and the parasitic capacitance is similarly reduced.

  When data reading is selected in the farthest area, a 1/16 junction capacitance is added to the conventional wiring length compared to the conventional wiring length. When data reading is selected in the nearest area, a 1/64 junction capacitance is added to a conventional wiring length of 1/4.

  In the fourth embodiment of the present invention, the inversion sense circuit 100 is provided in the main data line MDL. The parasitic capacitance is compared before and after the inverting sense circuit 100.

When data reading is selected in the farthest area, the parasitic capacitance on the bit line BL side from the inverting sense circuit 100 is the sum of the parasitic capacitance of the bit line BL and the parasitic capacitance of the main data line MDL. That is, the relative parasitic capacitance on the bit line BL side from the inversion sense circuit 100 is the junction capacitance (32C / 32) of the bit line BL, the relative wiring capacitance (32C / 32) of the bit line BL, and the junction of the main data line MDL. This is the sum of the capacity (32C / 64) and the relative wiring capacity (32C / 4/4) of the main data line MDL. Since the main data line MDL can be arranged at a pitch of 1/4 of the conventional bit line BL, the wiring capacity is also equivalent to 1/4. Therefore, when data reading is selected in the farthest area, the relative parasitic capacitance on the bit line BL side from the inverting sense circuit 100 is
(32C / 32) + (32C / 32) + (32C / 64) + (32C / 16) = 4.5C
It becomes.

When data reading is selected in the farthest area, the parasitic capacitance on the main data line MDL side from the inverting sense circuit 100 is the junction capacitance (3 × (32C / 64)) of the main data line MDL and the main data line. This is the sum of the relative wiring capacity of MDL (3 × (32C / 4/4)). Therefore, when data reading is selected in the farthest area, the relative parasitic capacitance on the main data line MDL side from the inverting sense circuit 100 is
(3 × (32C / 64)) + (3 × (32C / 16)) = 7.5C
It becomes.

  When the data reading is selected in the nearest area, the relative parasitic capacitance on the bit line BL side from the inverting sense circuit 100 is the same as in the case where the data reading is selected in the farthest area. 5C. When data reading is selected in the nearest area, the relative parasitic capacitance on the main data line MDL side from the inverting sense circuit 100 is sufficiently larger than the parasitic capacitance on the bit line BL side from the inverting sense circuit 100. Small. From the above results, it can be considered that the ratio of the parasitic capacitance between the bit line BL and the main data line MDL in the NAND flash memory according to the fourth embodiment of the present invention is (1: 2) at most.

  As described above, in the fourth embodiment of the present invention, the bit line has a hierarchical structure, and the inverting sense circuit 100 prevents the current from flowing in the upper layer and the lower layer so that no current flows in the other layer. As a result, the parasitic capacitance of the bit line is reduced, the power consumption at the time of reading is reduced, and the parasitic capacitance charged / discharged in the case of data “1” and the parasitic capacitance charged / discharged in the case of data “0”. Flattened. Furthermore, since the inversion sense circuit 100 is provided in the main data line MDL before branching the plurality of bit lines BL from the main data line MDL, the number of inversion sense circuits 100 can be reduced. Further, in the fourth embodiment of the present invention, by turning off the MOS transistor 161 that is the connection control transistor of the inverting sense circuit 100 above the data reading target NAND unit, the extra main above the data reading target NAND unit is turned off. The data line MDL can be electrically disconnected to reduce the influence of the wiring capacitance above the data read target NAND unit.

  The present invention is not limited to the above-described embodiments, and various modifications and applications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1, 101: Memory cell array 2, 102: Command decoder 3, 103: X decoder and word line driver 4, 104: Y decoder 5, 105: Timing controller 6, 106: Main latch 7, 107: Output controller 10, 100: Inversion sense circuit BL: bit lines CN, CN ′: connection node MDL: main data line

Claims (13)

A bit line hierarchical structure consisting of an upper layer main data line and a lower layer bit line branched from the main data line;
A memory cell connected to the bit line;
And an inverting sense circuit for setting a current flow so that no current flows in one of the main data line and the bit line when the data stored in the memory cell is read. A non-volatile semiconductor memory device.   2. A re-inversion means for detecting whether or not a current has flowed through the main data line and outputting a result obtained by inverting the detection result as data stored in the memory cell is further provided. A nonvolatile semiconductor memory device according to claim 1. The inverting sense circuit is
A latch circuit for sensing data;
A latch control circuit for enabling the latch circuit;
A voltage level output circuit that outputs a signal corresponding to the voltage level of the bit line,
When enabled by the latch control circuit, the latch circuit inverts and senses a signal corresponding to the voltage level of the bit line output from the voltage level output circuit, and inverts and senses the signal The nonvolatile semiconductor memory device according to claim 1, wherein: is output to the main data line.   Further comprising re-inversion means for re-inverting the signal sensed by inversion outputted to the main data line and outputting the re-inverted signal as data stored in the memory cell. The nonvolatile semiconductor memory device according to claim 3.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the bit line is branched from the main data line through the inversion sense circuit.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the inversion sensing circuit further includes amplitude conversion means for changing the amplitude of the sensed data and outputting the changed data to the main data line.   The nonvolatile semiconductor memory device according to claim 6, wherein the amplitude conversion unit sets a drive voltage of the latch circuit according to an amplitude.   The non-volatile semiconductor memory device according to claim 6, wherein the amplitude conversion unit sets an output level of an output circuit that outputs the sensed data according to an amplitude.   4. The nonvolatile semiconductor memory device according to claim 3, further comprising means for precharging the bit line. The inversion sense circuit further includes connection control means for connecting / disconnecting the main data line between a branch point between the main data line and the bit line and the next branch point,
The voltage level output circuit outputs a signal corresponding to the voltage level of the bit line based on the voltage level of the bit line taken through the main data line,
4. The nonvolatile semiconductor memory device according to claim 3, wherein the latch circuit outputs a signal corresponding to the inverted and sensed voltage level to the main data line downstream of the connection control means. . When reading data from the memory cell to be read, the connection control means located upstream of the main data line from a branch point between the bit line connected to the memory cell to be read and the main data line; and The connection control means corresponding to the bit line connected to the memory cell to be read blocks the main data line,
11. The nonvolatile memory according to claim 10, wherein the connection control unit located downstream of the connection control unit corresponding to the bit line connected to the memory cell to be read connects the main data line. Semiconductor memory device. A nonvolatile semiconductor memory device in which a bit line structure has a hierarchical structure including a main data line in an upper layer and a bit line in a lower layer branched from the main data line, and a memory cell is connected to the bit line in the lower layer The data reading method of
A method of reading data from a nonvolatile semiconductor memory device, wherein at the time of data reading, a phase of a current flowing through the main data line and a phase of a current flowing through the bit line are paired.   13. The method of reading data from a nonvolatile semiconductor memory device according to claim 12, wherein the phase of the current flowing through the main data line is inverted and the phase of the current is output as read data.

Images