JP2012014400A - Semiconductor memory device and semiconductor memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device with a long product life.SOLUTION: A semiconductor memory device 2 comprises: a semiconductor memory part 30 which is classified into a first area with a high rewrite frequency, a second area with a low rewrite frequency, and a free block area; a memory controller 10 for performing control so as to copy data stored in the second block to the uppermost entry block of the free block area at a predetermined timing, and also freeing the block, where the data has been stored, from the second area and entering it in the lowermost block of the free block area.

Description

  The present invention relates to a semiconductor memory device having a semiconductor memory for storing data from a host device, and a semiconductor memory system including the host device and the semiconductor memory device.

  A nonvolatile semiconductor memory device having a NAND flash memory simplifies the structure by collectively erasing data stored in memory cells in units of a plurality of memory cells called blocks, and realizes low cost and large capacity is doing. Since a semiconductor memory device has no movable part and low power consumption, it is widely used as a storage device for a host device such as a mobile phone or a portable music player. However, it is known that the NAND flash memory has a limit on the number of times of writing / erasing.

  This limitation is due to the fact that in the erase process for the memory cell, a high voltage is applied to the gate relative to the substrate and electrons are injected into the floating gate. If the erasing process is performed many times, the oxide film around the floating gate may deteriorate and the data may be destroyed. In order to avoid the concentration of erasure processing on specific memory cells and prolong the product life, the memory cells with a large number of erasure processing times are replaced with the memory cells with a small number of times, and the deterioration progress of the memory cells is averaged. So-called wear leveling is carried out.

  Furthermore, the area (partition) for storing data with high rewrite frequency and the area (partition) for storing data with low rewrite frequency are made the same size and stored in two areas at a predetermined timing. There is known a semiconductor memory device that averages the wear leveling process of the entire semiconductor memory by exchanging the obtained data with each other.

  In a semiconductor memory device that performs wear leveling, it is difficult for a host device to specify a data storage position using a physical address indicating a physical position of each memory cell in the semiconductor memory. For this reason, the concept of logical space is constructed, and physical addresses are converted into logical addresses indicating positions in the logical space. In order to convert a logical address into a physical address, a logical address / physical address conversion table (hereinafter referred to as “logical / physical (L / P) conversion table”) is used.

JP 2008-225576 A

  An embodiment of the present invention aims to provide a semiconductor memory device having a long product life and a semiconductor memory system having a long product life.

  In order to achieve the above object, a semiconductor memory device according to one embodiment of the present invention includes a first area including a block that stores data in a logical address range with a high rewrite frequency, and a logical address range with a low rewrite frequency. A semiconductor memory unit classified into a second area composed of blocks for storing data and a free block area composed of storable blocks entered in the release order from the first or second area; When rewriting the data stored in the block of the area, the rewritten data is stored in the block of the highest entry in the free block area, and the block in which the data is stored is stored in the first area. From the free block area, and stored in the block of the second area at a predetermined timing. Data is copied to the block of the highest entry in the free block area, and the block in which the data is stored is released from the second area and controlled to enter the lowest block of the free block area. And a memory controller.

It is a block diagram of the semiconductor memory system of this Embodiment. It is explanatory drawing for demonstrating the structure of a semiconductor memory part. It is explanatory drawing for demonstrating the process of the semiconductor memory device of this Embodiment. 4 is a flowchart for explaining a processing flow of the semiconductor memory device of the present embodiment;

  A semiconductor memory device 2 and a semiconductor memory system (hereinafter also referred to as “memory system”) 1 according to an embodiment of the present invention will be described.

  As shown in FIG. 1, the semiconductor memory device 2 of the embodiment is housed in a memory card that is detachably connected to a host device 3 such as a personal computer or a digital camera, or in the host device 3. This is a so-called embedded type storage device that records start-up data and the like. Alternatively, the semiconductor memory device 2 and the host device 3 may constitute a memory system 1 such as an SSD (Solid State Disk) or an MP3 player that is a portable music player. The semiconductor memory device 2 includes a semiconductor memory unit (hereinafter also simply referred to as “memory unit”) 30 and a memory controller 10.

  The memory unit 30 is a NAND flash memory, and has a structure in which a large number of memory cells 31 as unit cells are connected by a bit line used for writing and a word line used for reading. The NAND type memory unit 30 shares a plurality of cells with a conductive wire necessary for driving the memory cell 31. Therefore, data writing / reading is performed in units of a plurality of bits called pages, and erasing is performed in batches in units of a plurality of pages called blocks, for example, in units of 64 pages.

  The memory controller 10 includes a ROM 19, a CPU 11 that is a control unit, a RAM 14, a host I / F (interface) 18, an encoding process of data to be stored, and a stored data connected via a bus 17. An error correcting code (ECC) unit 20 that performs decoding processing and a NAND I / F (interface) 21 are included. Note that the ECC unit 20 is not required when the host device 3 has the ECC function.

  The memory controller 10 uses the CPU 11 to perform data transmission / reception with the host device 3 via the host I / F 18 and data transmission / reception with the memory unit 30 via the NAND I / F 21. During the operation of the semiconductor memory device 2, the RAM 14 stores a logical address / physical address conversion table (hereinafter referred to as “logical / physical conversion table”) 16 as will be described later. It will be rewritten.

  Here, as shown in FIG. 2, the plurality of memory cells 31 constituting the semiconductor memory unit 30 are divided into a plurality of physical blocks which are erase units. On the other hand, the host device 3 connected to the semiconductor memory device 2 instructs transmission / reception of data by a logical address (LBA: Logical Block Address) indicating the position of each memory cell 31 in the logical space.

  In the following description, the logical space partition size is the same as the physical block size, and one logical block is associated with one logical space partition (hereinafter referred to as “logical block”). The conversion format. That is, the size of one logical block is the same as the size of one physical block, but a logical-physical conversion format in which a plurality of physical blocks are associated with one logical block may be used.

  The CPU 11 executes an operation of an address conversion unit (not shown) for converting a logical address and a physical address based on the logical / physical conversion table 16 by using firmware (FW). Control of the entire semiconductor memory device 2 in response to a command input from the host device 3, such as wear leveling processing, is also executed by the CPU 11 with FW. In addition, you may have a driver for exclusive use of each process, for example, a wear leveling process, or IC. The ROM 19 is a storage unit that stores a control program or the like for the semiconductor memory device 2, and information for the memory controller 10 to control the semiconductor memory device 2 in a part of the memory unit 30 or a nonvolatile storage unit (not shown). For example, the logical-physical conversion table 16 is stored.

  As shown in FIGS. 3A and 3B, the memory unit 30 includes a region A (41A1, 41A2) that is a first region and a region B (41B1, 41B2) that is a second region. ), A third area C (41C1, 41C2), and a free block area (42).

  For area A, area B, and area C, one or more blocks are allocated from the free block area (42). Note that the memory unit 30 may be managed by being divided into at least two areas. For example, the area C may not be set. The host device 3 or the memory controller 10 manages which logical address range corresponds to the area A, the area B, and the area C. No logical address is assigned to the free block area (42).

  Here, the free block area (42) includes a plurality of writable blocks, in other words, a plurality of storable blocks. Since the NAND type memory unit 30 cannot perform a so-called overwrite operation, it is necessary to perform a writing process after performing a block erasing process. Further, even if one page is rewritten, it is necessary to rewrite all the blocks composed of, for example, 64 pages. As will be described later, the semiconductor memory device 2 performs the wear leveling process by preparing a free block area (42).

  It should be noted that the block released from the area A, the area B, or the area C with the data update may be erased when it is registered in the free block area (42), or a new area A, area B Alternatively, the erasing process may be executed when it is assigned to the area C, or the erasing process may be executed at an arbitrary timing.

  The area A is composed of a single block or a plurality of blocks that store data in a logical address range that is frequently rewritten. The area B is composed of one or a plurality of blocks that store data in a logical address range with a low rewrite frequency. The free block area is composed of one or a plurality of storable blocks entered in the order of release from the area A or the area B. The area C includes a plurality of blocks that store data in a logical address range that does not require rewriting, and is not a target of rewriting processing with the free block area. The host device 3 or the memory controller 10 sets the logical address ranges of the area A, the area B, and the area C according to the usage.

  For example, the area A is a data area for storing a log or the like at the time of system operation of the host device 3, and its rewrite frequency is higher than that of the area B. The area B is a program area for storing firmware executed by the host device 3 and its rewrite frequency is lower than that of the area A. The area C is an area in which important information necessary for basic operation of the system such as startup data of the semiconductor memory device 2 or boot code of the host device 3 is stored.

  Then, as shown in FIG. 3A, when the memory controller 10 of the semiconductor memory device 2 rewrites (updates) the data stored in the block of the area A (41A1, 41A2), The data is copied to the block (42T) of the highest entry in the free block area, and the block in which the data is originally stored is released from the area A (41A1, 41A2), and is moved to the lowest position (42B) of the free block area. Control to enter.

  That is, the block (42T) of the highest entry in the free block area 42 of the logical-physical conversion table 16 is changed to the logical address of the area A, and the block of the area A where the data was originally stored is changed to the lowest block of the free block area. (42B). That is, releasing the block means invalidating the association with the logical address for this block and allocating it to the free block area 42.

  The released block is entered at the lowest position in the free block area 42 and is assigned to the write process in order from the highest block (42T) in the free block area 42, and therefore, cyclic allocation is performed for the block in which data update occurs. As a result, the same block is not continuously used for rewriting. In other words, the wear leveling process is automatically performed on the area A when rewriting.

  Further, as shown in FIG. 3B, the memory controller 10 transfers the data stored in the block of the area B (41B1, 41B2) to the block 42T of the highest entry in the free block area 42 at a predetermined timing. At the same time as copying, control is performed so that the block in the area B in which the data is stored is released from the area B and entered in the lowest 42B of the free block area 42.

  Since the block assigned to the area B holds data with a low rewrite frequency, when this embodiment is not applied, there are few opportunities to be assigned to the free block area 42 by the data update, and the rewrite is hardly performed. . Accordingly, the block is circulated only between the area A and the free block, and uniform wear leveling processing over the entire storage area cannot be performed. On the other hand, when this embodiment is applied, a more uniform wear leveling process is performed as the memory unit 30 by releasing a block at a predetermined timing from the area B (41B1, 41B2) including blocks with low rewrite frequency. I do.

  Note that the timing for performing the wear leveling process in the area B is preferably based on the number of times data is rewritten, a predetermined time interval, a predetermined number of activations, or the like stored in the memory unit 30. It is particularly preferable to follow the command instructions from

  Note that the wear leveling process for the area B (41B1 and 41B2) may rewrite all the data stored in the area at one time, but takes time. For this reason, it is preferable to rewrite a part of the data stored in the block of the region B in order at every predetermined timing. For example, every time there is a command instruction from the host device 3, by shifting the block to be rewritten in the area B, a part of the data can be rewritten in order.

  As for the area C, by performing the wear leveling process at a predetermined timing similarly to the area B, the memory unit 30 can perform a more uniform wear leveling process. However, the area C stores important information. Since data may be damaged in the data rewriting process, the area C is preferably excluded from the wear leveling process.

  Since the memory device 2 and the memory system 1 according to the present embodiment can perform more uniform wear leveling processing as the memory unit 30, the product life is long.

  Next, the processing flow of the memory device 2 and the memory system 1 according to the present embodiment will be described in detail with reference to the flowchart of FIG.

<Step S10> Logical-physical conversion table reading process For example, the memory device 2 is connected to the host device 3 to be supplied with power (S10: Yes) and is in an operating state. Then, the logical / physical conversion table 16 stored in the nonvolatile memory unit is transferred to the RAM 14. Then, the CPU 11 repeatedly performs data writing / reading processing based on the logical-physical conversion table 16 until an end instruction is given (S11: Yes). In the following, only the data writing process will be described.

<Step S11> First Wear Leveling Processing When data such as a system operation log is transmitted from the host device 3, an encoding process is performed by the ECC 20, and a region A (41A1) which is a first region of the memory unit 30 Etc.). At this time, in the case of rewriting processing of a part of the data of the already stored block, the rewritten data is stored in the block 42T of the highest entry in the free block area 42 under the control of the memory controller 10. At the same time, the block in which the data is stored is released from the first area and entered in the lowest block 42B of the free block area 42.

  In other words, the logical address of the area A is assigned to the block 42T of the highest entry in the free block area 42. The block in which the data is stored is erased and changed from the logical address in the area A to the lowest block 42B in the free block area 42 as a storable block. That is, in the area A, the wear leveling process is automatically performed in the normal rewriting process.

<Step S12>
Until the dedicated command (hereinafter referred to as “dedicated command”) for instructing the start of the wear leveling processing for the area B is issued from the host device 3 (No), the normal processing from step S10 is repeated.

  Here, the dedicated command is issued based on the number of times of rewriting data stored in the memory unit 30, a predetermined time interval, a predetermined number of activations, or the like. When based on the number of data rewrites, for example, the host device 3 issues a dedicated command every time N times (N is a natural number) write processing commands are issued. In the case of a time interval, a dedicated command is issued once a day, once a week, or once every two hours. As the number of activations, for example, the number of activations of the memory system 1 is counted, and a command is issued when the number of activations reaches a predetermined number.

  The semiconductor memory device 2 that has received the dedicated command may immediately start the wear leveling process in the region B, but start the wear leveling process at a so-called idling time when no other process is performed. Also good.

  In the semiconductor memory device 2 of the present embodiment, the host device 3 manages the number of times for determining the timing of issuing the dedicated command, but the semiconductor memory device 2 may also manage it. Further, in the semiconductor memory device 2, the timing for starting the wear leveling processing of the area B is determined based on the instruction of the dedicated command from the host device 3, but the semiconductor memory device is not the dedicated command from the host device 3, but the semiconductor memory device Based on the number of rewrites of data stored in the memory unit 30, a predetermined time interval, or a predetermined number of activations, the predetermined timing may be determined by itself and the wear leveling process of the region B may be performed.

  As described above, the predetermined timing for issuing the dedicated command is the number of times of rewriting the data stored in the memory unit 30, one of the predetermined time interval or the predetermined number of activations, or the connected host device 3. Based on the command instructions from. However, the host device 3 also issues a dedicated command based on the number of times of rewriting data stored in the memory unit 30, a predetermined time interval, or a predetermined number of activations.

<Step S13> Second Wear Leveling Processing When a dedicated command is issued from the host device 3 (S13: Yes), the wear leveling processing of the area B is performed under the control of the memory controller 10. That is, the data stored in one block of the area B is copied to the block 42T of the highest entry in the free block area 42, and the block of the area B in which the data is stored is released from the area B and free block Control is performed by the memory controller 10 so as to enter the lowest block 42B of the area 42.

<Step S14>
For example, a predetermined number of blocks in the area B are sequentially processed in step S13. When the process for the predetermined number of blocks is completed (Yes), the wear leveling process for the area B is once ended and the normal process from step S11 is performed.
It should be noted that the extent to which the wear leveling processing has been performed in the area B is stored in the CPU 11, and when the next command is input, the subsequent processing is performed.

  Here, the number of blocks to be subjected to wear leveling processing is appropriately determined by one command. Of course, you may process about all the blocks of the area | region B at once. Further, the control may be performed not based on the number of blocks processed by one command but by the processing time required for the wear leveling process.

<Step S15> Data Saving Process When the operation of the semiconductor memory device 2 is turned off (S10: No), the data saving process is performed before that. That is, the logical-physical conversion table 16 and the wear leveling processing information stored in the RAM 14 are stored in the nonvolatile memory unit.

  The semiconductor memory device 2 and the memory system 1 having the semiconductor memory device 2 that perform the above operation have a long product life in order to perform uniform wear leveling processing.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory system, 2 ... Semiconductor memory device, 3 ... Host device, 10 ... Memory controller, 11 ... CPU, 14 ... RAM, 16 ... Logical-physical conversion table, 17 ... Bus, 19 ... ROM, 20 ... ECC part, 30 ... Semiconductor memory unit, 31 ... Memory cell, 42 ... Free block area, 42B ... Lowermost block, 42T ... Uppermost block

Claims (5)

A first area composed of blocks storing data in a logical address range with a high rewrite frequency; a second area composed of blocks storing data in a logical address range with a low rewrite frequency; and the first or first A free block area consisting of storable blocks entered in order of release from the area of 2, and a semiconductor memory unit classified into:
When rewriting the data stored in the block of the first area, the rewritten data is stored in the block of the highest entry in the free block area, and the block in which the data is stored is stored in the first block. Release from the area of 1 and enter the lowest block of the free block area,
At a predetermined timing, the data stored in the block of the second area is copied to the block of the highest entry in the free block area, and the block storing the data is released from the second area. And a memory controller that controls to enter the lowest part of the free block area.   The predetermined timing is based on either the number of rewrites of data stored in the semiconductor memory unit, a predetermined time interval, or a predetermined number of activations, or a command instruction from a connected host device. The semiconductor memory device according to claim 1.   3. The semiconductor memory device according to claim 1, wherein a part of the data stored in the block of the second area is rewritten in order at every predetermined timing.   4. The semiconductor memory unit according to claim 1, wherein the semiconductor memory unit has a third area including a block for storing data in a logical address range that does not require rewriting of stored data. 5. The semiconductor memory device described in 1. A host device,
A semiconductor memory system comprising: the semiconductor memory device according to claim 1.

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