JP2012013664A - Pattern structure for interstage probe, interstage measurement method, and multi-chip module high-frequency circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern structure for an interstage probe, that can measure S parameters between stages of a module including multiple stages of transistors, an interstage measurement method, and a multi-chip module high-frequency circuit.SOLUTION: A pattern structure for an interstage probe comprises a dielectric substrate, a first signal transmission line disposed on a first surface of the dielectric substrate, a pair of first ground terminal electrodes disposed adjacent to the first signal transmission line on the first surface of the dielectric substrate, a first VIA hole disposed below the first ground terminal electrode, and a rear surface ground electrode disposed on a second surface opposite to the first surface of the dielectric substrate and connected to the first ground terminal electrode via the first VIA hole. The first signal transmission line can be connected to a signal terminal of a high-frequency probe, and the pair of first ground terminal electrodes can be connected to a pair of ground terminals of the high-frequency probe.

Description

  Embodiments described herein relate generally to an interstage probe pattern structure, an interstage measurement method, and a multichip module high-frequency circuit.

  In order to obtain a higher gain from one package, a plurality of stages of transistors are connected in series within the package. A monolithic microwave integrated circuit (MMIC) has been actively used as a technique for forming a plurality of transistors, a plurality of matching circuits, and a plurality of bias circuits on a single semiconductor substrate.

  In the MMIC, a semiconductor device, an input / output matching circuit, a capacitor, a power supply line, and the like are integrated on a semiconductor substrate (see, for example, Patent Documents 1 to 3).

JP 2000-49549 A JP 2002-110737 A JP 2003-110381 A

  In the case of a module composed of a plurality of stages of transistors, the S parameter can be measured only at the outermost contour, that is, the input side of the first stage transistor connected to the input terminal and the last stage connected to the output terminal. Only on the output side of the transistor. Design confirmation is performed only with the characteristics of the outermost contour. In addition, adjustment of the bias point and S parameter between the stages of a plurality of stages has to rely on trial and error.

  Further, when the microstrip line used for impedance matching is thicker than the high frequency probe pitch, it is difficult to measure the S parameter.

  Further, since the pattern for measuring the S parameter with the high frequency probe is a coplanar line, the impedance is lower than that of the microstrip line, resulting in impedance discontinuity.

  According to one aspect, the dielectric substrate, the first signal transmission line disposed on the first surface of the dielectric substrate, and disposed adjacent to the first signal transmission line on the first surface of the dielectric substrate. A pair of first ground terminal electrodes, a first VIA hole disposed below the first ground terminal electrode, and a second surface opposite to the first surface of the dielectric substrate. On the other hand, a pattern structure for an interstage probe is provided that includes a back ground electrode connected via a first VIA hole. The signal terminal of the high frequency probe can be connected to the first signal transmission line, and the pair of ground terminals of the high frequency probe can be connected to the pair of first ground terminal electrodes.

(A) The typical arrangement block diagram of the pattern structure for interstage probes which concerns on embodiment, (b) The typical cross-section figure along the III-III line of Fig.1 (a). The equivalent circuit schematic of the interstage probe applied to the pattern structure for interstage probes which concerns on embodiment. It is the structural example 1 of the pattern structure for interstage probes which concerns on embodiment, (a) Pattern structure figure at the time of interstage measurement, (b) Pattern structure figure at the time of multistage connection. It is the structural example 2 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: The pattern structure figure at the time of interstage measurement. It is the structural example 3 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: (a) Pattern structure figure, (b) Pattern structure figure at the time of interstage measurement, (c) Pattern structure figure at the time of multistage connection . It is the structural example 4 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: (a) Pattern structure figure, (b) Pattern structure figure at the time of interstage measurement, (c) Pattern structure figure at the time of multistage connection . It is the structural example 5 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: (a) Pattern structure figure at the time of interstage measurement, (b) Pattern structure figure at the time of multistage connection, (c) At the time of multistage connection Another pattern structure diagram. It is the structural example 6 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: (a) Pattern structure figure at the time of interstage measurement, (b) Pattern structure figure at the time of multistage connection, (c) At the time of multistage connection Another pattern structure diagram. It is the structural example 7 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: The pattern structure figure at the time of interstage measurement. It is the structural example 8 of the pattern structure for another interstage probe which concerns on embodiment, Comprising: The pattern structure figure at the time of interstage measurement. The typical plane pattern block diagram of the multichip module high frequency circuit which concerns on embodiment. (A) Corresponding to FIG. 11, three-stage discrete transistors FET1, FET2, and FET3 are connected in series to form a multistage amplifier circuit. (B) Equivalent of interstage probe pattern structure SP1 circuit diagram. (A) Corresponding to the interstage probe pattern structure of the configuration example 3 shown in FIGS. 5C and 6C, a circuit configuration example in which signal transmission lines are connected using bonding wires LD after interstage measurement. (B) Corresponding to the interstage probe pattern structure of Configuration Example 5 or Configuration Example 6 shown in FIG. 7 (a) and FIG. 7 (b), or FIG. 8 (a) and FIG. After measurement, the circuit configuration example in which the signal transmission lines are connected using the bonding wires LDM, (c) the interstage probe pattern of the configuration example 5 or the configuration example 6 shown in FIG. 7 (c) or FIG. 8 (c) The example of a circuit structure which connected between signal transmission lines using metal foil MF after measurement between steps corresponding to a structure. The typical plane pattern block diagram of the multichip module high frequency circuit which concerns on a comparative example. FIG. 15 is a schematic circuit configuration diagram corresponding to FIG. 14. FIG. 15 is a schematic sectional view taken along the line II-II in FIGS. 11 and 14. FIG. 15 is a schematic sectional view taken along line III-III in FIGS. 11 and 14. FIG. 19A is an enlarged schematic plan pattern configuration diagram of a discrete transistor FET3 portion applied to the multichip module high-frequency circuit according to the embodiment, and FIG. 18B is an enlarged view of a portion J in FIG. FIG. 19 is a structural example 1 of a discrete transistor, and is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. FIG. 19 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. FIG. 19 is a schematic cross-sectional structure diagram illustrating a third example of the discrete transistor and taken along line IV-IV in FIG. FIG. 19 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. FIG. 3 is a schematic bird's-eye view in the vicinity of a discrete transistor FET3 applied to the multichip module high-frequency circuit according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

(Pattern structure for interstage probes)
The pattern structure for interstage probes according to the embodiment is mainly applied to interstage measurement of a module constituted by a plurality of amplifiers in one package in a microwave high-frequency semiconductor device.

  A typical arrangement configuration of the interstage probe pattern structure and the tip portion of the high-frequency probe according to the embodiment is represented as shown in FIG. 1A, and is a schematic view taken along the line II in FIG. A typical cross-sectional structure is expressed as shown in FIG.

  As shown in FIG. 1A, the distal end portion of the high-frequency probe includes a signal terminal SP0 and a pair of ground terminals G0 and G0 arranged close to both sides of the signal terminal SP0. Here, the distances X1 and X2 between the signal terminal SP0 and the pair of ground terminals G0 and G0 are, for example, about 150 μm.

  As shown in FIGS. 1A and 1B, the interstage probe pattern structure according to the embodiment includes a dielectric substrate 14 and a signal transmission disposed on the first surface of the dielectric substrate 14. A line SL, a pair of ground terminal electrodes S0 and S0 disposed adjacent to the signal transmission line SL on the first surface of the dielectric substrate 14, and a VIA hole SC0 disposed below the ground terminal electrode S0; Formed on the inner wall of the VIA hole SC0, the base electrode 132 connected to the ground terminal electrode S0, the buried electrode 130 formed on the base electrode 132, and connected to the base electrode 132 and the buried electrode 130, the dielectric substrate 14 And a ground electrode 125 disposed on the back surface. Here, the ground electrode 125 may be disposed not only on the first dielectric substrate 14 but also on the back surfaces of the second dielectric substrate 18 and the semiconductor substrate 16 described later.

  A signal terminal SP0 of the high-frequency probe 40 can be connected to the signal transmission line SL, and a pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of ground terminal electrodes S0 and S0.

  The distance between the ground terminal electrode S0 and the signal transmission line SL is smaller than the distances X1 and X2 between the pair of ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  Using the high-frequency probe 40, the S parameter between the signal transmission line SL and the ground terminal electrode S0 can be measured.

  The ground terminal electrode S0 is connected to the ground electrode 125 (see FIG. 1B) via the VIA hole SC0 formed thereunder, and is at the ground potential. Here, the width X3 of the signal transmission line SL is, for example, about 100 μm. This is a value determined from the arrangement of the high-frequency probe 40 because measurement is difficult when the width of the signal transmission line SL used for matching is larger than the pitch of the high-frequency probe 40.

  In the inter-stage probe pattern structure according to the embodiment, when measuring inter-stage parameters of a plurality of stages of transistors, the signal terminal SP0 at the tip of the high-frequency probe 40 and the pair of ground terminals G0 and G0 are respectively inter-stage probes. It is in contact with the signal transmission line SL having the pattern structure for use and the pair of ground terminal electrodes S0 and S0.

  As shown in FIG. 2, an equivalent circuit of the high-frequency probe 40 applied to the inter-stage probe pattern structure according to the embodiment includes a capacitor C01 connected to the signal terminal SP0 at the tip of the high-frequency probe 40, and a capacitor C01. A diode D01 having an anode connected thereto, a diode D02 having a cathode connected thereto, a capacitor C02 connected between the cathode of the diode D01 and the anode of D02, and a tester 24 connected in parallel to the capacitor C02. A pair of ground terminals G0 and G0 are arranged adjacent to the signal terminal SP0. The pair of ground terminals G0 and G0 are connected to a ground potential common to the tester 24.

(Pattern configuration example for interstage probe)
The pattern structure for interstage probes according to the embodiment is a pattern that can be contacted by the high-frequency probe 40 during interstage measurement. The pattern structure for interstage probes according to the embodiment is finished in a product form and incorporated in a package at the time of multistage connection. In the product form incorporated in the package, the high frequency probe 40 is connected to a package terminal outside the package, and the high frequency circuit characteristics are measured.

  In the interstage probe pattern structure according to the embodiment, the characteristic impedance of the high-frequency probe 40 is 50Ω, so that the transmission line has a characteristic impedance close to 50Ω or a characteristic impedance of about 25Ω to 100Ω on the high-frequency circuit. It is preferable to place it at the upper point.

  In the interstage probe pattern structure according to the embodiment, since the shape of the high-frequency probe 40 is, for example, 150 μm pitch, the width of the interstage probe pattern to be contacted is preferably about 100 μm, for example.

  Further, in the interstage probe pattern structure according to the embodiment, by aligning the shape of the end face of the transmission line regardless of the width of the transmission line, without replacing the high-frequency probe 40 for each interstage probe pattern, The same high frequency probe 40 can be measured for the interstage probe pattern structures according to all the embodiments.

  In addition, since the inter-stage probe pattern structure according to the embodiment is measured by applying the high-frequency probe 40, a pair of ground terminal electrodes S0 and S0 are arranged on both sides of the signal transmission line SL adjacent to the signal transmission line SL. A coplanar structure having a pattern of S0 is provided.

  On the other hand, if the width of the microstrip line is narrow, impedance discontinuity occurs and the characteristics change, which is not preferable. Also, if there is a ground pattern on the side of the track, the impedance is reduced, which is not preferable.

  For example, when the signal transmission line (microstrip line) SL having a line width of 254 μm is formed on an alumina substrate having a thickness of the dielectric substrate 14 of about 254 μm, the characteristic impedance of the signal transmission line SL is 50Ω. On the other hand, the characteristic impedance of the coplanar structure having a pair of ground terminal electrodes S0 and S0 with a line width of 254 μm and a distance of 40 μm on an alumina substrate having a thickness of 254 μm on the dielectric substrate 14 is 39Ω.

  Therefore, in the multistage operation of the interstage probe pattern structure according to the embodiment, it is desirable to connect the signal transmission lines SL with bonding wires or capacitors and use them properly according to the situation.

-Configuration example 1-
FIG. 3A is a configuration example 1 of an interstage probe pattern structure according to an embodiment, and the pattern structure at the time of interstage measurement is represented as shown in FIG. It is expressed as shown in (b).

  As shown in FIG. 3A, the configuration example 1 of the interstage probe pattern structure according to the embodiment includes a dielectric substrate 14 and a first signal transmission disposed on the first surface of the dielectric substrate 14. The line SL1, the pair of first ground terminal electrodes S01 and S02 disposed adjacent to the first signal transmission line SL1 on the first surface of the dielectric substrate 14, and the lower portions of the first ground terminal electrodes S01 and S02 The first VIA holes SC01 and SC02 that are arranged and the second surface opposite to the first surface of the dielectric substrate 14 are arranged via the first VIA holes SC01 and SC02 with respect to the first ground terminal electrodes S01 and S02. On the back surface ground electrode 125 connected, the second signal transmission line SL2 disposed on the first surface of the dielectric substrate 14 so as to face the first signal transmission line SL1, and on the first surface of the dielectric substrate 14 Second signal transmission line A pair of second ground terminal electrodes S03 and S04 disposed adjacent to L2 and a lower portion of the second ground terminal electrodes S03 and S04, and the second ground terminal electrodes S03 and S04 are connected to the back surface ground electrode 125. Second VIA holes SC03 and SC04 are provided.

  Here, the distance ΔD between the first signal transmission line SL1 and the second signal transmission line SL2 may be about the thickness of the dielectric substrate 14, and is about 0.1 mm to 0.254 mm, for example.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the first signal transmission line SL1, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of first ground terminal electrodes S01 and S02. .

  Similarly, the signal terminal SP0 of the high frequency probe 40 can be connected to the second signal transmission line SL2, and the pair of ground terminals G0 and G0 of the high frequency probe 40 are connected to the pair of second ground terminal electrodes S03 and S04. Is possible.

  The distance between the first ground terminal electrodes S01 and S02 and the first signal transmission line SL1 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  The distance between the second ground terminal electrodes S03 and S04 and the second signal transmission line SL2 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  The S parameter between the first signal transmission line SL1 and the first ground terminal electrodes S01 and S02 can be measured using the high-frequency probe 40, and the arrangement of the high-frequency probe 40 can be changed to change the second signal transmission line SL2 And the S parameter between the second ground terminal electrodes S03 and S04 can be measured.

  Here, the width of the first end face transmission line SL1 and the second end face transmission line SL2 is, for example, 100 μm.

  In addition, the high-frequency probe 40 can be connected to and disconnected from the interstage probe pattern structure according to the embodiment.

  In the configuration example 1 of the interstage probe pattern structure according to the embodiment, the ground terminal electrodes S01, S02, S03, and S04 are formed in the VIA holes SC01 and SC02 penetrating the dielectric substrate 14, as in FIG. -It is connected to the ground electrode 125 via SC03 and SC04 and is at the ground potential.

  In the configuration example 1 of the interstage probe pattern structure according to the embodiment, during interstage measurement, the interstage probe signal terminal SP0 and the ground terminals G0 and GO are connected to the first signal transmission line SL1 and the ground terminal electrodes S01 and S02. Contact and measure the S parameter on the output side of the previous stage. Similarly, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the second signal transmission line SL2 and the ground terminal electrodes S03 and S04, and the S parameter on the input side of the next stage is measured.

  In the configuration example 1 of the inter-stage probe pattern structure according to the embodiment, the pattern structure at the time of multi-stage connection is arranged on the dielectric substrate 14 and separated from each other as shown in FIG. A capacitor C2 connected between the transmission line SL1 and the second signal transmission line SL2 is provided. Other configurations are the same as those in FIG.

-Interstage measurement method using configuration example 1-
The interstage measurement method using the configuration example 1 of the interstage probe pattern structure according to the embodiment includes the first signal transmission line SL1 disposed on the first surface of the dielectric substrate 14 and the dielectric substrate 14. Forming a pattern structure for an interstage probe having a pair of first ground terminal electrodes S01 and S02 disposed adjacent to the first signal transmission line SL1 on the first surface; and on the first signal transmission line SL1 The signal terminal SP0 of the high frequency probe 40 is connected, the pair of first ground terminal electrodes S01 and S02 are connected to the pair of ground terminals G0 and G0, and the first signal transmission line SL1 and the first ground terminal are connected. Measuring an S parameter between the electrodes S01 and S02.

-Configuration example 2-
It is the structural example 2 of the pattern structure for interstage probes which concerns on embodiment, Comprising: The pattern structure at the time of interstage measurement is represented as shown in FIG.

  As shown in FIG. 4, the configuration example 2 of the interstage probe pattern structure according to the embodiment is arranged on the end surface of the first signal transmission line SL1 facing the second signal transmission line SL2, and the first signal transmission line The first end face transmission line SM1 having a narrower width than SL1 and the second end face of the second signal transmission line SL2 facing the first signal transmission line SL1, and a second width having a narrower width than the second signal transmission line SL2. And an end face transmission line SM2. Further, the pair of first ground terminal electrodes S01 and S02 are disposed adjacent to the first end surface transmission line SM1, and the pair of second ground terminal electrodes S02 and S04 are disposed adjacent to the second end surface transmission line SM2. Is done.

  Here, the distance ΔD between the first end face transmission line SM1 and the second end face transmission line SM2 may be about the thickness of the dielectric substrate 14, and is about 0.1 mm to 0.254 mm, for example.

  The distance between the first ground terminal electrodes S01 and S02 and the first end face transmission line SM1 is smaller than the distance between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the first end face transmission line SM1, and the signal terminal SP0 of the high-frequency probe 40 can be connected to the second end face transmission line SM2.

  The distance between the second ground terminal electrodes S03 and S04 and the second end face transmission line SM2 is smaller than the distance between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  Further, the S parameter between the first end face transmission line SM1 and the first ground terminal electrodes S01 and S02 can be measured using the high-frequency probe 40.

  Further, the S parameter between the second end face transmission line SM2 and the second ground terminal electrodes S03 and S04 can be measured using the high-frequency probe 40.

  Here, the width of the first end face transmission line SM1 and the second end face transmission line SM2 is about 100 μm.

  The high frequency probe 40 can be connected and disconnected.

  In the configuration example 2 of the inter-stage probe pattern structure according to the embodiment, the inter-stage measurement pattern structure is arranged on the dielectric substrate 14 and spaced apart from each other as shown in FIG. SL2, the end face transmission line SM1 connected to the first signal transmission line SL1, the end face transmission line SM2 connected to the first signal transmission line SL1, and the dielectric board 14 spaced apart from each other on the dielectric substrate 14. 14 and the ground terminal electrodes S01 and S02 disposed adjacent to the end surface transmission line SM1, and the ground terminal electrodes S03 and S02 disposed on the dielectric substrate 14 and disposed adjacent to the end surface transmission line SM2. S04. The ground terminal electrodes S01, S02, S03, and S04 are connected to the ground electrode 125 via the VIA holes SC01, SC02, SC03, and SC04 penetrating the dielectric substrate 14 as in FIG. Has been made.

  In the configuration example 2 of the interstage probe pattern structure according to the embodiment, during the interstage measurement, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the end face transmission line SM1 and the ground terminal electrodes S01 and S02. Then, the S parameter on the output side of the previous stage is measured. Similarly, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the end face transmission line SM2 and the ground terminal electrodes S03 and S04, and the S parameter on the input side of the next stage is measured.

  In the configuration example 2 of the inter-stage probe pattern structure according to the embodiment, the pattern structure in the multi-stage connection is similar to FIG. 3B, in which a capacitor is connected between the end face transmission lines SM1 and SM2 that are separated from each other. Also good. Alternatively, the end face transmission lines SM1 and SM2 separated from each other may be connected using a bonding wire. Alternatively, the signal transmission lines SL1 and SL2 that are separated from each other may be connected using a bonding wire.

-Interstage measurement method using configuration example 2-
In the interstage measurement method using the configuration example 2 of the interstage probe pattern structure according to the embodiment, the step of forming the interstage probe pattern structure is further performed on the first surface of the dielectric substrate 14 by the first step. A second signal transmission line SL2 disposed to face the signal transmission line SL1, and a pair of second ground terminal electrodes S03 disposed on the first surface of the dielectric substrate 14 adjacent to the second signal transmission line SL2. A step of forming S04, the signal terminal SP0 of the high-frequency probe 40 is connected to the second signal transmission line SL2, and the pair of ground terminals G0 of the high-frequency probe are connected to the pair of second ground terminal electrodes S03 and S04. G0 is connected to measure the S parameter between the second signal transmission line SL2 and the second ground terminal electrodes S03 and S04.

  Moreover, you may have the step which connects between 1st signal transmission line SL1 and 2nd signal transmission line SL2 with a capacitor.

―Example 3―
FIG. 5B shows a configuration example 3 of the inter-stage probe pattern structure according to the embodiment. The pattern structure is represented as shown in FIG. 5A, and the inter-stage measurement pattern structure is shown in FIG. The pattern structure at the time of multistage connection is expressed as shown in FIG.

  In the configuration example 3 of the interstage probe pattern structure according to the embodiment, as shown in FIG. 5, the first end face transmission line SM1 is a first separated transmission line SD1 separated from the first signal transmission line SL1. The second end face transmission line SM2 is represented by a second separated transmission line SD2 separated from the second signal transmission line SL2.

  Here, the distance ΔD between the first separation transmission line SD1 and the second separation transmission line SD2 may be about the thickness of the dielectric substrate 14, and is about 0.1 mm to 0.254 mm, for example.

  The width of the first separated transmission line SD1 and the second separated transmission line SD2 is about 100 μm.

  The high frequency probe 40 can be connected and disconnected.

  In the configuration example 3 of the interstage probe pattern structure according to the embodiment, as shown in FIG. 5A, the pattern structure includes signal transmission lines SL1 and SL2 arranged on the dielectric substrate 14 and spaced apart from each other. The dielectric substrate 14 is separated from the first signal transmission line SL1 and is separated from the first signal transmission line SL1, and the separation transmission line SD2 is separated from the second signal transmission line SL2. Ground terminal electrodes S01 and S02 disposed on the top and adjacent to the separated transmission line SD1, and ground terminal electrodes S03 and S04 disposed on the dielectric substrate 14 and disposed adjacent to the separated transmission line SD2. With. The ground terminal electrodes S01, S02, S03, and S04 are connected to the ground electrode 125 via the VIA holes SC01, SC02, SC03, and SC04 penetrating the dielectric substrate 14 as in FIG. Has been made.

  In the configuration example 3 of the interstage probe pattern structure according to the embodiment, at the time of interstage measurement, as shown in FIG. 5B, the first signal transmission line SL1 and the separated transmission line SD1 are connected by the bonding wire LD1. The second signal transmission line SL2 and the separation transmission line SD2 are connected by a bonding wire LD2. Other configurations are the same as those in FIG.

  In the configuration example 3 of the interstage probe pattern structure according to the embodiment, during the interstage measurement, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separated transmission line SD1 and the ground terminal electrodes S01 and S02. Then, the S parameter on the output side of the previous stage is measured. Similarly, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separation transmission line SD2 and the ground terminal electrodes S03 and S04, and the S parameter on the input side of the next stage is measured.

  In the configuration example 3 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 5C, the pattern structure at the time of multi-stage connection is such that bonding wires LD3 are provided between the signal transmission lines SL1 and SL2 that are separated from each other. Connected. Alternatively, a capacitor may be connected between the separated transmission lines SD1 and SD2 separated from each other. Alternatively, as in FIG. 5B, the first signal transmission line SL1 and the separation transmission line SD1 are connected by the bonding wire LD1, and the second signal transmission line SL2 and the separation transmission line SD2 are connected by the bonding wire LD2. Further, the separated transmission line SD1 and the separated transmission line SD2 that are separated from each other may be connected using a capacitor or a bonding wire.

-Interstage measurement method using configuration example 3-
In the interstage measurement method using the interstage probe pattern structure configuration example 3 according to the embodiment, the step of forming the interstage probe pattern structure further includes a first signal facing the second signal transmission line SL2. The first separated transmission line SD1 disposed on the end face of the transmission line SL1, having a narrower width than the first signal transmission line SL1, and separated from the first signal transmission line SL1, and the first signal transmission line SL1 A step of forming a second separated transmission line SD2 disposed on an end face of the second signal transmission line SL2 facing the second signal transmission line SL2 and having a narrower width than the second signal transmission line SL2 and separated from the second signal transmission line SL2; Connecting the first separation transmission line SD1 and the first signal transmission line SL1 with the first bonding wire LD1, and between the second separation transmission line SD2 and the second signal transmission line SL2. The step of connecting with the second bonding wire LD2, the signal terminal SP0 of the high-frequency probe 40 is connected to the first separation transmission line SD1, and the pair of ground terminals G0 of the high-frequency probe 40 are connected to the pair of first ground terminal electrodes S01 and S02. Connecting G0 and measuring the S parameter between the first separated transmission line SD1 and the first ground terminal electrodes S01 and S02; connecting the signal terminal SP0 of the high-frequency probe 40 to the second separated transmission line SD2; A pair of ground terminals G0 and G0 of the high-frequency probe 40 are connected to the pair of second ground terminal electrodes S03 and S04, and the S parameter between the second separated transmission line SD2 and the second ground terminal electrodes S03 and S04 is measured. Steps.

  Moreover, you may have the step which connects between 1st isolation | separation transmission line SD1 and 2nd isolation | separation transmission line SD2 with a capacitor.

  Further, a step of connecting the first signal transmission line SL1 and the second signal transmission line SL2 with the third bonding wire LD3 may be performed.

—Example 4—
FIG. 6A is a configuration example 4 of the inter-probe pattern structure according to the embodiment, and the pattern structure is represented as shown in FIG. 6A. The inter-stage measurement pattern structure is shown in FIG. The pattern structure at the time of multistage connection is expressed as shown in FIG.

  In configuration example 4 of another inter-stage probe pattern structure according to the embodiment, one of the pair of first ground terminal electrodes and one of the pair of second ground terminal electrodes are ground terminals formed in a common pattern. The electrode S05 is provided, and the other of the pair of first ground terminal electrodes and the other of the pair of second ground terminal electrodes include a ground terminal electrode S06 formed in a common pattern.

  Here, the distance ΔD between the first separation transmission line SD1 and the second separation transmission line SD2 may be about the thickness of the dielectric substrate 14 as in the configuration example 3, for example, 0.1 mm to It is about 0.254 mm.

  In the configuration example 4 of the interstage probe pattern structure according to the embodiment, the ground terminal electrodes S01 and S02 are formed by the common ground terminal electrode S05, and the ground terminal electrodes S03 and S04 are formed by the common ground terminal electrode S06. is doing. The ground terminal electrodes S05 and S06 are connected to the ground electrode 125 through the VIA holes SC01, SC03, SC02, and SC04 penetrating the dielectric substrate 14, and are at the ground potential. Other configurations are the same as those in Structural Example 3.

  Since the interstage measurement method using the configuration example 4 is the same as the interstage measurement method using the configuration example 3, description thereof is omitted.

-Example 5-
FIG. 7A shows a configuration example 5 of another inter-stage probe pattern structure according to the embodiment, and the pattern structure at the time of inter-stage measurement is represented as shown in FIG. It is expressed as shown in FIG. 7B, and another pattern structure at the time of multistage connection is expressed as shown in FIG. 7C.

  As shown in FIG. 7A, the configuration example 5 of another interstage probe pattern structure according to the embodiment includes a dielectric substrate 14 and a first surface disposed on the first surface of the dielectric substrate 14. The signal transmission line SL1, a pair of first ground terminal electrodes S01 and S02 disposed adjacent to the side surface of the first signal transmission line SL1 on the first surface of the dielectric substrate 14, and the first ground terminal electrodes S01 and S01 The first VIA holes SC01 and SC02 arranged at the lower part of S02 and the second surface opposite to the first surface of the dielectric substrate 14, and the first VIA holes SC01 and SC01 are arranged with respect to the first ground terminal electrodes S01 and S02. A back-surface ground electrode 125 connected via SC02 and a first signal transmission line SL1 are disposed on a side surface between the pair of first ground terminal electrodes S01 and S02 and separated from the first signal transmission line SL1. 1 separate transmission And a road SD1.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the first separated transmission line SD1, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of first ground terminal electrodes S01 and S02. .

  Further, the second signal transmission line SL2 disposed on the first surface of the dielectric substrate 14 so as to face the first signal transmission line SL1, and the second signal transmission line SL2 disposed on the first surface of the dielectric substrate 14. A pair of second ground terminal electrodes S03 and S04 disposed adjacent to the side surfaces of the first and second ground terminal electrodes S03 and S04, and the second ground terminal electrodes S03 and S04 are connected to the back surface ground electrode 125. The second VIA holes SC03 and SC04 and the second signal transmission line SL2 are arranged between the pair of second ground terminal electrodes S03 and S04 on the side surface of the second signal transmission line SL2 and separated from the second signal transmission line SL2. SD1.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the second separated transmission line SD2, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of second ground terminal electrodes S03 and S04. .

  Here, the distance ΔM between the first signal transmission line SL1 and the second signal transmission line SL2 is, for example, about 0.1 mm to 0.254 mm. The dimension of ΔM is such that the first signal transmission line SL1 and the second signal transmission line SL2 are separated by a distance similar to the thickness of the dielectric substrate 14 in order to separate the first signal transmission line SL1 and the second signal transmission line SL2 in terms of propagation of the microwave signal. It is desirable to do.

  The distance between the first ground terminal electrodes S01 and S02 and the first separation transmission line SD1 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  The distance between the second ground terminal electrodes S03 and S04 and the second separated transmission line SD2 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  In the configuration example 5 of the interstage probe pattern structure according to the embodiment, during interstage measurement, as shown in FIG. 7A, the bonding wire LD1 is connected between the first signal transmission line SL1 and the first separated transmission line SD1. The second signal transmission line SL2 and the second separation transmission line SD2 are connected by a bonding wire LD2.

  In the configuration example 5 of the interstage probe pattern structure according to the embodiment, during interstage measurement, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separated transmission line SD1 and the ground terminal electrodes S01 and S02. Then, the S parameter on the output side of the previous stage is measured. Similarly, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separation transmission line SD2 and the ground terminal electrodes S03 and S04, and the S parameter on the input side of the next stage is measured.

  In the configuration example 5 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 7B, the pattern structure at the time of the multi-stage connection is such that bonding wires LDM are provided between the signal transmission lines SL1 and SL2 that are separated from each other. Connected. Alternatively, a capacitor may be connected between the separated transmission lines SD1 and SD2 separated from each other.

  In the configuration example 5 of the interstage probe pattern structure according to the embodiment, the distance ΔM between the first signal transmission line SL1 and the second signal transmission line SL2 is compared with the pattern structure of the configuration example 3 shown in FIG. , Can be set small. For this reason, the length of the bonding wire LDM can be set shorter than the length of the bonding wire LD3. As a result, since the inductance of the bonding wire LDM between the first signal transmission line SL1 and the second signal transmission line SL2 is reduced, reflection loss and radiation loss can be reduced.

  In the configuration example 5 of the inter-stage probe pattern structure according to the embodiment, the pattern structure at the time of multi-stage connection is a metal foil between the signal transmission lines SL1 and SL2, which are separated from each other, as shown in FIG. You may connect using MF. Here, the material of the metal foil is not limited. For example, the metal foil may be welded and formed by thermocompression bonding. Alternatively, a copper foil may be formed by soldering. The width ΔMF of the metal foil MF is preferably equal to the width ΔS of the first signal transmission line SL1 and the second signal transmission line SL2. By making the width ΔMF of the metal foil MF equal to the width ΔS of the first signal transmission line SL1 and the second signal transmission line SL2, it is possible to reduce reflection loss and radiation loss while maintaining pattern continuity. Because.

  Since the interstage measurement method using the configuration example 5 is the same as the interstage measurement method using the configuration example 3, description thereof is omitted.

—Example 6—
FIG. 8A shows a configuration example 6 of another inter-stage probe pattern structure according to the embodiment. The pattern structure at the time of inter-stage measurement is represented as shown in FIG. It is represented as shown in FIG. 8B, and another pattern structure at the time of multistage connection is represented as shown in FIG.

  Configuration example 6 of another interstage probe pattern structure according to the embodiment faces the side surface of the first signal transmission line SL1 on the first surface of the dielectric substrate 14, as shown in FIG. 8A. A pair of third ground terminal electrodes S05 and S06 and a third separated transmission line SD3 disposed adjacent to the side surface, and a side surface opposite to the side surface of the second signal transmission line SL2 on the first surface of the dielectric substrate 14 A pair of fourth ground terminal electrodes S07 and S08 and a fourth separated transmission line SD4 that are disposed adjacent to each other, a third ground terminal electrode S05 and S06, and a fourth ground terminal electrode S07 and S08 that are disposed below the fourth ground terminal electrode S07 and S08, respectively. 3 VIA holes SC05 and SC06 and fourth VIA holes SC07 and SC08.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the third separated transmission line SD3, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of third ground terminal electrodes S05 and S06. .

  Similarly, the signal terminal SP0 of the high-frequency probe 40 can be connected to the fourth separated transmission line SD4, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of fourth ground terminal electrodes S07 and S08. Is possible.

  Here, the distance ΔM between the first signal transmission line SL1 and the second signal transmission line SL2 is, for example, about 0.1 mm to 0.254 mm, similarly to the configuration example 5. The dimension of ΔM is such that the first signal transmission line SL1 and the second signal transmission line SL2 are separated by a distance similar to the thickness of the dielectric substrate 14 in order to separate the first signal transmission line SL1 and the second signal transmission line SL2 in terms of propagation of the microwave signal. It is desirable to do.

  The distance between the third ground terminal electrodes S05 and S06 and the third separated transmission line SD3 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  Further, the distance between the fourth ground terminal electrodes S07 and S08 and the fourth separation transmission line SD4 is smaller than the distances X1 and X2 between the ground terminals G0 and G0 of the high-frequency probe 40 and the signal terminal SP0.

  In the configuration example 6 of the interstage probe pattern structure according to the embodiment, during interstage measurement, as shown in FIG. 8A, a bonding wire LD1 is connected between the first signal transmission line SL1 and the first separation transmission line SD1. The second signal transmission line SL2 and the second separation transmission line SD2 are connected by a bonding wire LD2. Alternatively, here, the first signal transmission line SL1 and the third separation transmission line SD3 may be connected by the bonding wire LD1, and the second signal transmission line SL2 and the fourth separation transmission line SD4 may be connected by the bonding wire LD2. good.

  That is, in the configuration example 6, during the interstage measurement, the pattern of the first ground terminal electrodes S01 and S02 and the first separated transmission line SD1 and the third ground terminal electrodes S05 and S06 are adapted to the arrangement of the high-frequency probe 40. One of the patterns of the third separated transmission line SD3 can be selected.

  Similarly, in the configuration example 6, the pattern of the second ground terminal electrodes S03 and S04 and the second separated transmission line SD2 and the fourth ground terminal electrodes S07 and S08 are adapted to the arrangement of the high-frequency probe 40 during the interstage measurement. Any one of the patterns of the fourth separation transmission line SD4 can be selected.

  As described above, the configuration example 6 has an advantage that the interstage measurement can be easily performed by appropriately selecting the pattern in conformity with the arrangement of the high-frequency probe 40 during the interstage measurement.

  In configuration example 6 of the interstage probe pattern structure according to the embodiment, during interstage measurement, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separated transmission line SD1 and the ground terminal electrodes S01 and S02. Then, the S parameter on the output side of the previous stage is measured. Alternatively, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separation transmission line SD3 and the ground terminal electrodes S05 and S06, and the S parameter on the output side of the previous stage is measured.

  Similarly, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separation transmission line SD2 and the ground terminal electrodes S03 and S04, and the S parameter on the input side of the next stage is measured. Alternatively, the signal terminal SP0 and the ground terminals G0 and G0 of the interstage probe are brought into contact with the separated transmission line SD4 and the ground terminal electrodes S07 and S08, and the S parameter on the input side of the next stage is measured.

  In the configuration example 6 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 8B, the pattern structure at the time of the multi-stage connection is such that bonding wires LDM are provided between the signal transmission lines SL1 and SL2 that are separated from each other. Connected. Alternatively, a capacitor may be connected between the separated transmission lines SD1 and SD2 separated from each other.

  In the configuration example 6 of the interstage probe pattern structure according to the embodiment, as in the configuration example 5, the distance ΔM between the first signal transmission line SL1 and the second signal transmission line SL2 is set as shown in FIG. 3 can be set smaller than the pattern structure 3. For this reason, the length of the bonding wire LDM can be set shorter than the length of the bonding wire LD3. As a result, since the inductance of the bonding wire LDM between the first signal transmission line SL1 and the second signal transmission line SL2 is reduced, reflection loss and radiation loss can be reduced.

  In the configuration example 6 of the inter-stage probe pattern structure according to the embodiment, the pattern structure at the time of multi-stage connection is a metal foil between the signal transmission lines SL1 and SL2 that are separated from each other as shown in FIG. You may connect using MF. Here, the material of the metal foil is not limited. For example, the metal foil may be welded and formed by thermocompression bonding. Alternatively, a copper foil may be formed by soldering. The width ΔMF of the metal foil MF is preferably equal to the width ΔS of the first signal transmission line SL1 and the second signal transmission line SL2. By making the width ΔMF of the metal foil MF equal to the width ΔS of the first signal transmission line SL1 and the second signal transmission line SL2, it is possible to reduce reflection loss and radiation loss while maintaining pattern continuity. Because.

  Since the interstage measurement method using the configuration example 6 is the same as the interstage measurement method using the configuration example 3, the description thereof is omitted.

-Example 7-
FIG. 9 shows a configuration example 7 of another interstage probe pattern structure according to the embodiment, and the pattern structure at the time of interstage measurement is represented as shown in FIG. In FIG. 9, the dielectric substrate 14 is arranged in the same manner as in FIG. 7, but the illustration of the dielectric substrate 14 is omitted.

  In the configuration example 7 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 9, the first separation transmission line SD1 is disposed adjacent to the end of the first signal transmission line SL1, The two separated transmission lines SD2 are disposed adjacent to the end of the second signal transmission line SL2. Other configurations are the same as the configuration example 5 shown in FIG.

  In the configuration example 7 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 9, the first separation transmission line SD1 is disposed adjacent to the end of the first signal transmission line SL1, and the second By disposing the separation transmission line SD2 adjacent to the end portion of the second signal transmission line SL2, the end region of the first signal transmission line SL1 and the end region of the second signal transmission line SL2 are effectively used. Can do. In addition, the length of the bonding wire LD1 between the ends of the first separated transmission line SD1 and the first signal transmission line SL1 and the length of the bonding wire LD2 between the second separated transmission line SD2 and the end of the second signal transmission line SL2 are shortened. In addition, since the inductance of the bonding wire is reduced, reflection loss and radiation loss can be reduced during inter-step measurement.

  The interstage measurement method using the configuration example 7 is the same as the interstage measurement method using the configuration example 5 and the configuration example 6, and thus the description thereof is omitted.

—Example 8—
SC01 / SC02 / SC03, the pattern structure during inter-step measurement is expressed as shown in FIG. In FIG. 10, the dielectric substrate 14 is arranged in the same manner as in FIG. 7, but the illustration of the dielectric substrate 14 is omitted.

  In the configuration example 8 of another inter-stage probe pattern structure according to the embodiment, as shown in FIG. 10, the dielectric substrate 14 and the first surface of the dielectric substrate 14 are arranged to face each other. The first signal transmission line SL1 and the second signal transmission line SL2 and the first signal transmission line SL1 and the second signal transmission line SL2 are continuously arranged on the first surface of the dielectric substrate 14 adjacent to the side surfaces of the first signal transmission line SL1 and the second signal transmission line SL2. The first and second pairs of first ground terminal electrodes S01, S02, S03, first VIA holes SC01, SC02, SC03 disposed below the first ground terminal electrodes S01, S02, S03, and the dielectric substrate 14 The back surface ground electrode 1 is disposed on the second surface opposite to the first surface and connected to the first ground terminal electrodes S01, S02, S03 via the first VIA holes SC01, SC02, SC03. 5, a first separated transmission line SD1 disposed between the first pair of first ground terminal electrodes SC01 and SC02 on the side surface of the first signal transmission line SL1, and separated from the first signal transmission line SL1, and a second A side surface of the signal transmission line SL2 includes a second separated transmission line SD2 disposed between the second pair of first ground terminal electrodes S02 and S03 and separated from the second signal transmission line SL2.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the first separated transmission line SD1, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the first pair of first ground terminal electrodes S01 and S02. The signal terminal SP0 of the high-frequency probe 40 can be connected to the second separated transmission line SD2, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 are connected to the second pair of first ground terminal electrodes S02 and S03. Can be connected.

  Further, as shown in FIG. 10, the first signal transmission line SL1 in which the first and second pairs of first ground terminal electrodes S01, S02, and S03 are arranged on the first surface of the dielectric substrate 14 and the first signal transmission line SL1. The first and second pairs of second ground terminal electrodes S04, S05, and S06 that are continuously disposed adjacent to the side surface that faces the side surface of the two-signal transmission line SL2, and the second ground terminal electrodes S04, S05, and The second VIA holes SC01, SC02, SC03 arranged at the lower part of S06 and the second surface opposite to the first surface of the dielectric substrate 14 are arranged to be second to the second ground terminal electrodes S04, S05, S06. The back ground electrode 125 connected through the 2VIA holes SC01, SC02, and SC03 and the first signal transmission line SL1 are disposed between the first pair of second ground terminal electrodes S04 and S05 on the side surface of the first signal transmission line SL1. The third separated transmission line SD3 separated from the transmission line SL1 and the second signal transmission line SL2 are disposed between the second pair of second ground terminal electrodes S05 and S06 and separated from the second signal transmission line SL2. The fourth separated transmission line SD4 may be provided.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the third separated transmission line SD3, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the first pair of second ground terminal electrodes S04 and S05. The signal terminal SP0 of the high-frequency probe 40 can be connected to the fourth separated transmission line SD4, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 are connected to the second pair of second ground terminal electrodes S05 and S06. Can be connected.

  As shown in FIG. 10, the first separation transmission line SD1 is disposed adjacent to the end of the first signal transmission line SL1, and the second separation transmission line SD2 is the end of the second signal transmission line SL2. It may be arranged adjacent to.

  In the configuration example 8 of the interstage probe pattern structure according to the embodiment, as shown in FIG. 10, the pattern occupation of the first ground terminal electrodes S01, S02, and S03 and the second ground terminal electrodes S04, S05, and S06 is occupied. The area can be saved, and it is possible to cope with a finer inter-probe pattern structure.

  In the configuration example 8 of the inter-stage probe pattern structure according to the embodiment, as shown in FIG. 10, the first separation transmission line SD1 is disposed adjacent to the end of the first signal transmission line SL1, and the second By disposing the separation transmission line SD2 adjacent to the end portion of the second signal transmission line SL2, the end region of the first signal transmission line SL1 and the end region of the second signal transmission line SL2 are effectively used. Can do. In addition, the length of the bonding wire LD1 between the ends of the first separated transmission line SD1 and the first signal transmission line SL1 and the length of the bonding wire LD2 between the second separated transmission line SD2 and the end of the second signal transmission line SL2 are shortened. In addition, since the inductance of the bonding wire is reduced, reflection loss and radiation loss can be reduced during inter-step measurement.

  The interstage measurement method using the configuration example 8 is the same as the interstage measurement method using the configuration example 5 and the configuration example 6, and thus the description thereof is omitted.

(Multichip module high frequency circuit)
A typical plane pattern configuration example of the multichip module high-frequency circuit according to the embodiment is expressed as shown in FIG. Corresponding to FIG. 11, a schematic circuit configuration example in which a multi-stage amplifier circuit is configured by connecting three stages of discrete transistors FET1, FET2, and FET3 in series is expressed as shown in FIG.

As shown in FIG. 11, the multichip module high-frequency circuit 30 according to the embodiment includes a semiconductor substrate 16 on which a plurality of discrete transistors FET1, FET2, and FET3 are formed, and a first dielectric substrate 14 on which capacitors C1 to C4 are formed. ₁ , 14 ₂ , 14 ₃ , 14 ₄ , second dielectric substrates 18 ₁ , 18 ₂ forming a matching circuit, and interstage probe pattern structures SP 1, SP 2. The plurality of discrete transistors FET1, FET2, and FET3 may be connected in series, for example.

Similarly to the configuration example 1 in FIG. 3, the inter-stage probe pattern structures SP1 and SP2 include the first signal transmission line SL1 disposed on the first surface of the first dielectric substrate 14 ₂ and 14 ₃ , and the first signal transmission line SL1. A pair of first ground terminal electrodes S01 and S02 disposed adjacent to the first signal transmission line SL1 on the first surface of the dielectric substrates 14 ₂ and 14 ₃ , and below the first ground terminal electrodes S01 and S02 The first VIA holes SC01 and SC02 are disposed on the second surfaces opposite to the first surfaces of the first dielectric substrates 14 ₂ and 14 ₃ , and the first VIA holes are disposed on the first ground terminal electrodes S01 and S02. The back surface ground electrode 125 connected through SC01 and SC02, and the second signal transmission line disposed on the first surface of the first dielectric substrate 14 ₂ and 14 _{3 so} as to face the first signal transmission line SL1 and SL2, the first dielectric substrate 14 ₂ - 1 ₃ a pair of second ground terminal electrodes S03 · S04 disposed adjacent to the first surface to a second signal transmission line SL2, and is disposed under the second ground terminal electrodes S03 · S04, the second ground terminal Second VIA holes SC03 and SC04 connecting the electrodes S03 and S04 to the back ground electrode 125 are provided.

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the first signal transmission line SL1, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of first ground terminal electrodes S01 and S02. .

  The signal terminal SP0 of the high-frequency probe 40 can be connected to the second signal transmission line SL2, and the pair of ground terminals G0 and G0 of the high-frequency probe 40 can be connected to the pair of second ground terminal electrodes S03 and S04. .

  The plurality of discrete transistors FET1, FET2, and FET3 are formed on the same semiconductor substrate 16.

  Alternatively, the plurality of discrete transistors FET1, FET2, and FET3 may be formed on a plurality of separate semiconductor substrates, respectively.

The semiconductor substrate 16, the first dielectric substrate 14 ₁ , 14 ₂ , 14 ₃ , 14 ₄ , and the second dielectric substrate 18 ₁ , 18 ₂ are all connected to the common ground electrode 125 on the back surface. Good (see FIG. 23).

  Similarly to the configuration example 2 in FIG. 4, the inter-stage probe pattern structures SP1 and SP2 are arranged on the end face of the first signal transmission line SL1 facing the second signal transmission line SL2, and the first signal transmission line SL1. A first end face transmission line SM1 having a narrower width and a second end face having a width narrower than that of the second signal transmission line SL2 disposed on the end face of the second signal transmission line SL2 facing the first signal transmission line SL1. And a pair of first ground terminal electrodes S01 and S02 are disposed adjacent to the first end face transmission line SM1, and a pair of second ground terminal electrodes S03 and S04 is a second end face transmission. You may arrange | position adjacent to track | line SM2.

  In the inter-probe pattern structures SP1 and SP2, as shown in the configuration example 3 of FIG. 5, the first end face transmission line SM1 is composed of a first separated transmission line SD1 separated from the first signal transmission line SL1. In addition, the second end surface transmission line SM2 may be configured by a first separated transmission line SD2 separated from the first signal transmission line SL2.

  Further, as shown in the configuration example 4 in FIG. 6, the interstage probe pattern structures SP1 and SP2 include one of the pair of first ground terminal electrodes S01 and S02 and one of the pair of second ground terminal electrodes S03 and S04. Is formed by a ground terminal electrode S05 having a common pattern, and the other of the pair of first ground terminal electrodes S01 and S02 and the other of the pair of second ground terminal electrodes S03 and S04 is formed by a ground terminal electrode S06 having a common pattern. May be.

  In the embodiment shown in FIG. 11, since the plurality of discrete transistors FET1, FET2, and FET3 are integrated on the same semiconductor substrate 16, they are compared with the case where they are formed on separate semiconductor substrates. , Collection accuracy has been improved.

The semiconductor substrate 16, the first dielectric substrate 14 ₁ , 14 ₂ , 14 ₃ , 14 ₄ and the second dielectric substrate 18 ₁ , 18 ₂ are arranged on one package substrate 10 surrounded by the frame member 12. And contained in one package.

  The semiconductor substrate 16 on which the discrete transistors FET1, FET2, and FET3 are mounted may be directly mounted on the surface of the package substrate 10.

  The semiconductor substrate 16 includes discrete transistors FET1, FET2, and FET3, gate terminals G1, G2, and G3 of the discrete transistors FET1, FET2, and FET3, source terminal electrodes S1, S2, and S3, and drain terminal electrodes D1, D2, and Only D3 may be included as a circuit element.

  The discrete transistors FET1, FET2, and FET3 used in the multichip module high-frequency circuit 30 according to the embodiment include, for example, a field effect transistor (FET) and a high electron mobility transistor (HEMT). ) Etc. can be applied.

  As shown in FIG. 11, a capacitor C1 is connected to the input terminal Pi, and a capacitor C4 is connected to the output terminal Po.

The gate input terminal g1, which is connected via a capacitor C1 to an input terminal Pi, by the gate bias voltage V _GG, the gate voltage Vgg1 is supplied.

  The gate input terminal g1 is connected to the gate terminal electrode G1 of the discrete transistor FET1 via the input transmission line λg1.

  The drain terminal electrode D1 of the discrete transistor FET1 is connected to the drain output terminal d1 via the output transmission line λd1.

A drain voltage Vdd1 is supplied to the drain output terminal d1 by the drain bias voltage V _DD .

  A capacitor C2 is connected to the drain output terminal d1.

The drain output terminal d1 gate input terminal g2 connected via the capacitor C2, the by the gate bias voltage V _GG, the gate voltage Vgg2 is supplied.

The gate input terminal g2 is connected to the gate terminal electrode G2 of the discrete transistor FET2 via the input transmission line λg2. Here, the input transmission line λg2, because they are disposed on the first dielectric substrate 14 _4, compared to the case which is arranged in a separate dielectric substrate, has improved current accuracy.

The drain terminal electrode D2 of the discrete transistor FET2 is connected to the drain output terminal d2 via the output transmission line λd2. Here, since the output transmission line λd2 is disposed on the first dielectric substrate 14 ₃ , the collection accuracy is improved as compared with the case where the output transmission line λd2 is disposed on a separate dielectric substrate.

A drain voltage Vdd2 is supplied to the drain output terminal d2 by the drain bias voltage V _DD .

  A capacitor C3 is connected to the drain output terminal d2.

The gate input terminal g3 to the drain output terminal d2 is connected via the capacitor C3, the gate bias voltage V _GG, the gate voltage Vgg3 is supplied.

  The gate input terminal g3 is connected to the gate terminal electrode G3 of the discrete transistor FET3 via the input transmission line λg3.

  The drain terminal electrode D3 of the discrete transistor FET3 is connected to the drain output terminal d3 via the output transmission line λd3.

A drain voltage Vdd3 is supplied to the drain output terminal d3 by the drain bias voltage V _DD .

  A capacitor C4 is connected to the drain output terminal d3, and the capacitor C4 is connected to the output terminal Po.

  Here, among the plurality of discrete transistors FET1, FET2, and FET3, the gate width of the discrete transistor FET2 used in the preceding stage is narrower than the gate width of the discrete transistor FET3 used in the final stage, thereby forming a cascade connection. A multistage amplifier may be configured.

  Further, among the plurality of discrete transistors FET1, FET2, and FET3, the gate width of the discrete transistor FET1 used in the first stage is narrower than the gate width of the discrete transistor FET2 used in the second stage. You may comprise the multistage amplifier by connection.

  As shown in FIG. 12A, the schematic circuit configuration of the multistage amplifier circuit corresponding to FIG. 11 is configured by cascade connecting three stages of discrete transistors FET1, FET2, and FET3 in series. . As shown in FIG. 12A, capacitors C2 and C3 are connected between the signal transmission lines of the interstage probe pattern structures SP1 and SP2 after the interstage measurement. In FIG. 12A, S0 represents four ground terminal electrodes as a representative. An equivalent circuit of the inter-stage probe pattern structure SP1 is represented, for example, as shown in FIG. The inter-stage probe pattern structure SP2 is similarly expressed except that it is connected by the capacitor C3.

  FIG. 13A shows an example of a circuit configuration in which signal transmission lines are connected using bonding wires LD after interstage measurement in such an interstage probe pattern structure. The circuit configuration of FIG. 13A corresponds to the interstage probe pattern structure of Configuration Example 3 shown in FIGS. 5C and 6C.

  FIG. 13B shows a circuit configuration example in which signal transmission lines are connected using bonding wires LDM after inter-stage measurement in such an inter-stage probe pattern structure. The circuit configuration of FIG. 13B is the inter-stage probe pattern structure of Configuration Example 5 or Configuration Example 6 shown in FIG. 7A and FIG. 7B, or FIG. 8A and FIG. 8B. It corresponds to.

  FIG. 13C shows an example of a circuit configuration in which signal transmission lines are connected using a metal foil MF after interstage measurement in such an interstage probe pattern structure. FIG. 13C corresponds to the interstage probe pattern structure of Configuration Example 5 or Configuration Example 6 shown in FIG. 7C or FIG.

(Comparative example)
A schematic planar pattern configuration of a multi-chip module high-frequency circuit according to a comparative example of the embodiment is expressed as shown in FIG. 14, and corresponding to FIG. 14, three stages of discrete transistors FET1 to FET3 are connected in series. A schematic circuit configuration of the multistage amplifier circuit is expressed as shown in FIG.

  In the comparative example shown in FIGS. 14 and 15, the interstage probe pattern structures SP1 and SP2 are not provided, and therefore interstage measurement cannot be performed. The S parameter measurement terminals are only the gate input terminal g1 of the discrete transistor FET1 and the drain output terminal d3 of the discrete transistor FET3.

As shown in FIG. 16, a schematic cross-sectional structure taken along line II-II in FIG. 11 and FIG. 14 is arranged on the package substrate 10, the insulating layer 20 disposed on the package substrate 10, and the insulating layer 20. Input terminal electrode 22 ₁ , first dielectric substrates 14 ₁ and 14 ₂ disposed on package substrate 10, and semiconductor substrate 16 disposed on package substrate 10.

Capacitors C1 and C2 are disposed on the first dielectric substrate 14 ₁ and 14 ₂ , respectively, and a discrete transistor FET 1 is disposed on the semiconductor substrate 16.

The first dielectric substrate 14 ₁ can be applied as a capacitor formation substrate by adjusting the thickness of the first dielectric substrate 14 ₁ . This is because the capacitor value can be changed by changing the thickness of the first dielectric substrate 14 ₁ . Similarly, it is also possible to change the capacitor value by changing the first dielectric substrate 14 ₁ of the dielectric constant.

A schematic cross-sectional structure taken along the line III-III in FIGS. 11 and 14 includes a package substrate 10, an insulating layer 20 disposed on the package substrate 10, and an insulating layer 20 as shown in FIG. 17. Output terminal electrode 22 ₂ , first dielectric substrates 14 ₃ and 14 ₄ disposed on package substrate 10, semiconductor substrate 16 disposed on package substrate 10, and first dielectric substrate disposed on package substrate 10. Two dielectric substrates 18 ₁ and 18 ₂ are provided.

The first dielectric substrate 14 _3, 14 ₄ are disposed a capacitor C3, C4, respectively, to the semiconductor substrate 16 _0, it is arranged discrete transistors FET 3.

An input matching circuit and an output matching circuit are disposed on the second dielectric substrates 18 ₁ and 18 ₂ , respectively.

As shown in FIG. 17, the thicknesses of the first dielectric substrates 14 ₃ and 14 ₄ and the second dielectric substrates 18 ₁ and 18 ₂ can be appropriately changed. It is also possible to adjust the capacitor value by changing the dielectric constant and adjust the characteristic impedance of the arranged transmission line. Similarly, the capacitor area and the arranged stub length can be greatly shortened.

  In the schematic planar pattern configuration of the high-frequency circuit 30 having the multichip module structure according to the embodiment, the signal propagation directions of the plurality of discrete transistors FET1, FET2, and FET3 are alternately arranged at each stage. Also good. That is, as shown in FIG. 11, the signal propagation direction from the gate terminal electrode G1 to the drain terminal electrode D1 of the discrete transistor FET1 and the signal propagation direction from the gate terminal electrode G2 to the drain terminal electrode D2 of the discrete transistor FET2 are reversed. The signal propagation direction from the gate terminal electrode G2 to the drain terminal electrode D2 of the discrete transistor FET2 and the signal propagation direction from the gate terminal electrode G3 to the drain terminal electrode D3 of the discrete transistor FET3 are opposite to each other.

(Element structure)
In the multichip module high-frequency circuit according to the embodiment, an enlarged schematic planar pattern configuration of the applied discrete transistor FET3 portion is expressed as shown in FIG. 18A, and the J portion in FIG. An enlarged view of is shown as shown in FIG. Moreover, it is the structural examples 1-4 of the discrete transistor applied to the multichip module high frequency circuit which concerns on embodiment, Comprising: Typical cross-sectional structural examples 1-4 along the IV-IV line of FIG. These are expressed as shown in FIGS. The cross-sectional structures of the discrete transistors FET1 and FET2 are configured in the same manner as the discrete transistor FET3. In addition, in the high-frequency circuit having the multichip module structure according to the embodiment, a schematic bird's-eye view structure of the applied discrete transistor FET3 portion is expressed as shown in FIG.

  In the multichip module high-frequency circuit according to the embodiment, the discrete transistor FET3 is disposed on the semi-insulating substrate 110 and the first surface of the semi-insulating substrate 110 as shown in FIGS. A gate finger electrode 124 having a finger, a source finger electrode 120 and a drain finger electrode 122 are disposed on the first surface of the semi-insulating substrate 110, and each of the gate finger electrode 124, the source finger electrode 120 and the drain finger electrode 122 includes a plurality of fingers. A plurality of gate terminal electrodes G3, a plurality of source terminal electrodes S3 and a plurality of drain terminal electrodes D3 formed by bundling fingers, a VIA hole SC3 disposed below the source terminal electrode S3, and a semi-insulating substrate 110 Opposite the first surface It is arranged in two surfaces, and a back surface ground electrode 125 which is connected through a VIA hole SC3 to the source terminal electrodes S3 (see FIG. 23).

  As shown in FIGS. 11 and 23, the bonding wire 54 is connected to the gate terminal electrode G, the bonding wire 56 is connected to the drain terminal electrode D, and the VIA hole SC is formed below the source terminal electrode S. The source terminal electrode S is connected to the ground electrode 125 through an electrode layer (not shown) formed on the inner wall of the VIA hole SC. Here, the structure in which the back surface ground electrode 125 is formed on the source terminal electrode S via the VIA hole SC, as shown in FIG. 1B, the structure on the ground terminal electrode SC0 via the VIA hole SC0. This is similar to the structure in which the back ground electrode 125 is formed.

  The semi-insulating substrate is a GaAs substrate, SiC substrate, GaN substrate, substrate having a GaN epitaxial layer formed on the SiC substrate, substrate having a heterojunction epitaxial layer made of GaN / AlGaN formed on the SiC substrate, sapphire substrate, or diamond One of the substrates.

―Structure Example 1―
As a schematic cross-sectional structure taken along line IV-IV in FIG. 18B, the discrete transistor structure example 1 is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode 120, a gate finger electrode 124, and a drain finger electrode 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In Structural Example 1 shown in FIG. 19, a high electron mobility transistor (HEMT) is shown.

-Structural example 2-
As a schematic cross-sectional structure taken along line IV-IV in FIG. 18B, the discrete transistor structure example 2 is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, source region 126 and drain region 128 disposed on nitride-based compound semiconductor layer 112, source finger electrode 120 disposed on source region 126, and nitride-based compound semiconductor layer 112 A gate finger electrode 124 disposed above and a drain finger electrode 122 disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode 124. In Structural Example 2 shown in FIG. 20, a metal-semiconductor field effect transistor (MESFET) is shown.

―Structure Example 3―
As a schematic cross-sectional structure taken along line IV-IV in FIG. 18B, the discrete transistor structure example 3 is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode 120 and a drain finger electrode 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0 1 ≦ x ≦ 1) 118, and a gate finger electrode 124 disposed in the recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 3 shown in FIG. 21, HEMT is shown.

-Structural example 4-
As a schematic cross-sectional structure taken along line IV-IV in FIG. 18B, the discrete transistor structure example 4 is disposed on the semi-insulating substrate 110 and the semi-insulating substrate 110 as shown in FIG. Nitride-based compound semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride-based compound semiconductor layer 112, and aluminum gallium nitride layer A source finger electrode 120 and a drain finger electrode 122 disposed on (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0 1 ≦ x ≦ 1) 118 and a gate finger electrode 124 disposed in a two-stage recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 4 illustrated in FIG. 22, the HEMT is illustrated.

  Further, in Structural Example 4 described above, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116. In Structural Example 4 described above, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. Alternatively, a predetermined ion can be ion-implanted by an ion implantation technique. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  The ground electrode 125 includes a barrier metal layer and a ground metal layer disposed on the barrier metal layer, but is not shown in FIG. The barrier metal layer is made of, for example, a Ti layer or a Ti / Pt layer, and the ground metal layer is made of, for example, an Au layer.

  Therefore, the ground electrode 125 may have any one of an Au layer, a Ti / Au layer, a Ti / W / Au layer, and a Ti / Pt / Au layer. The thickness of the ground electrode 125 is, for example, about 5 μm to 30 μm.

  In the discrete transistor FET applied to the multichip module high-frequency circuit according to the embodiment, the pattern length in the longitudinal direction of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 is microwave / millimeter wave / submillimeter. As the wave and operating frequency increase, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  In the multichip module high-frequency circuit according to the embodiment, an interstage probe pattern structure is interwoven between the stages of the plurality of transistors as a circuit pattern for measuring the S parameter between the stages of the plurality of transistors. Thus, it is possible to measure the S parameter between stages, and it is possible to perform design confirmation, bias point, impedance matching, and S parameter adjustment between stages of a plurality of transistors.

  In the interstage probe pattern structure according to the embodiment, by narrowing down the end face of the microstrip line, even when the microstrip line used for impedance matching is thicker than the tip pitch of the high-frequency probe 40, S-parameters can be measured, and S-parameters between stages can be measured using high-frequency probes with the same pitch even for circuit configurations having different line widths.

  In the interstage probe pattern structure according to the embodiment, the impedance is discontinuous by separating the microstrip line and the pattern for measuring the S parameter by the high-frequency probe and wire-connecting only at the time of measurement. Can be eliminated.

  In the interstage probe pattern structure according to the embodiment, the microstrip line is separated from the pattern for measuring the S parameter by the high frequency probe, and wire connection is performed only at the time of measurement, so that a plurality of transistor stages are provided. S-parameters in between can be measured.

  In the inter-stage probe pattern structure according to the embodiment, during multi-stage operation, the impedance discontinuity can be avoided by skip-connecting the inter-stage probe pattern with a bonding wire having a loop. .

[Other embodiments]
Although embodiments of the present invention and some modifications have been described, these are presented as examples and are not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  The discrete transistors applied to the high-frequency circuit having the multichip module structure according to the embodiment are not limited to FETs and HEMTs, but also LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) and heterojunction bipolar transistors (HBTs). : Amplifying elements such as Hetero-junction Bipolar Transistor), MEMS (Micro Electro Mechanical Systems) elements, and the like are also applicable.

  Further, the number of cascade connection stages of discrete transistors applied to the multichip module high-frequency circuit according to the embodiment is not limited to three, and may be four or more.

10 ... package substrate 12 ... frame member 16 ... semiconductor substrate 14, 14 _1, 14 _2, 14 _3, 14 _4, 14 ₅ ... first dielectric substrate 18 _1, 18 ₂ ... second dielectric substrate 20: insulating Layer 22 ₁ ... Input terminal electrode 22 ₂ ... Output terminal electrode 30 ... Multi-chip module high-frequency circuit 40 ... Interstage probe 110 ... Semi-insulating substrate 112 ... Nitride-based compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
DESCRIPTION OF SYMBOLS 120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 125 ... Ground electrode 126 ... Source region 128 ... Drain region 130 ... Embedded electrode 132 ... Base electrode Pi ... Input terminal Po ... Output terminal FET1, FET2, FET3 ... Discrete Transistors C1, C2, C3, C4 ... Capacitors λg1, λg2, λg3 ... Input transmission lines λd1, λd2, λd3 ... Output transmission lines Vgg1, Vgg2, Vgg3 ... Gate voltages Vdd1, Vdd2, Vdd3 ... Drain voltages V _GG ... Gate bias voltage V _DD ... drain bias voltage G, G1, G2, G3 ... gate terminal electrodes S, S1, S2, S3 ... source terminal electrodes D, D1 to D3 ... drain terminal electrodes S0, S01, S02, S03, S04, S05, S06 ... Ground terminal electrode SL, L1, SL2 ... Signal transmission lines LD1, LD2, LD3, LDM ... Bonding wires SC, SC0, SC3 ... VIA holes SP0 ... Signal terminals G0 ... Ground terminals SP1, SP2 ... Interstage probe pattern structures SM1, SM2 ... End face transmission lines SD1, SD2 ... separated transmission lines ΔD, ΔM ... distance MF ... metal foil ΔS ... width of signal transmission line ΔMF ... width of metal foil

Claims (30)

A dielectric substrate;
A first signal transmission line disposed on a first surface of the dielectric substrate;
A pair of first ground terminal electrodes disposed adjacent to the first signal transmission line on the first surface of the dielectric substrate;
A first VIA hole disposed under the first ground terminal electrode;
A back surface ground electrode disposed on a second surface opposite to the first surface of the dielectric substrate and connected to the first ground terminal electrode via the first VIA hole, and the first signal transmission A pattern structure for interstage probes, wherein a signal terminal of a high-frequency probe can be connected to the line, and a pair of ground terminals of the high-frequency probe can be connected to the pair of first ground terminal electrodes. A second signal transmission line disposed on the first surface of the dielectric substrate so as to face the first signal transmission line;
A pair of second ground terminal electrodes disposed adjacent to the second signal transmission line on the first surface of the dielectric substrate;
A second VIA hole disposed under the second ground terminal electrode and connecting the second ground terminal electrode to the back ground electrode; and a signal terminal of a high-frequency probe can be connected to the second signal transmission line. 2. The interstage probe pattern structure according to claim 1, wherein a pair of ground terminals of the high-frequency probe can be connected to the pair of second ground terminal electrodes. A first end face transmission line disposed on an end face of the first signal transmission line facing the second signal transmission line and having a width narrower than the first signal transmission line;
A second end surface transmission line disposed on an end surface of the second signal transmission line facing the first signal transmission line and having a width narrower than that of the second signal transmission line, and the pair of first grounds The terminal electrode is disposed adjacent to the first end surface transmission line, and the pair of second ground terminal electrodes are disposed adjacent to the second end surface transmission line. The pattern structure for interstage probes as described in 1. The first end transmission line is formed of a first separated transmission line separated from the first signal transmission line, and the second end transmission line is separated from the second signal transmission line. The interstage probe pattern structure according to claim 3, wherein the interstage probe pattern structure is formed by:   5. The interstage probe pattern structure according to claim 3, wherein the first end face transmission line and the second end face transmission line have a width of 100 μm.   The interstage probe pattern structure according to any one of claims 1 to 5, wherein the high-frequency probe is connectable and separable.   One of the pair of first ground terminal electrodes and one of the pair of second ground terminal electrodes are formed in a common pattern, and the other of the pair of first ground terminal electrodes and the pair of second ground terminal electrodes. The pattern structure for interstage probes according to any one of claims 2 to 6, wherein the other is formed in a common pattern. A dielectric substrate;
A first signal transmission line disposed on a first surface of the dielectric substrate;
A pair of first ground terminal electrodes disposed adjacent to a side surface of the first signal transmission line on the first surface of the dielectric substrate;
A first VIA hole disposed under the first ground terminal electrode;
A back surface ground electrode disposed on a second surface opposite to the first surface of the dielectric substrate and connected to the first ground terminal electrode via the first VIA hole;
A first separation transmission line disposed on a side surface of the first signal transmission line between the pair of first ground terminal electrodes and separated from the first signal transmission line; A pattern structure for an interstage probe, wherein a signal terminal of a high-frequency probe can be connected, and a pair of ground terminals of the high-frequency probe can be connected to the pair of first ground terminal electrodes. A second signal transmission line disposed on the first surface of the dielectric substrate so as to face the first signal transmission line;
A pair of second ground terminal electrodes disposed adjacent to a side surface of the second signal transmission line on the first surface of the dielectric substrate;
A second VIA hole disposed under the second ground terminal electrode and connecting the second ground terminal electrode to the back surface ground electrode;
A second separated transmission line disposed between the pair of second ground terminal electrodes and separated from the second signal transmission line on a side surface of the second signal transmission line; 9. The interstage probe according to claim 8, wherein a signal terminal of the high-frequency probe can be connected, and a pair of ground terminals of the high-frequency probe can be connected to the pair of second ground terminal electrodes. Pattern structure.   9. The interstage probe pattern structure according to claim 8, wherein the first separation transmission line is disposed adjacent to an end of the first signal transmission line.   The first separation transmission line is disposed adjacent to an end portion of the first signal transmission line, and the second separation transmission line is disposed adjacent to an end portion of the second signal transmission line. The pattern structure for interstage probes according to claim 9. A pair of third ground terminal electrodes disposed on a first surface of the dielectric substrate adjacent to a side surface of the first signal transmission line on which the pair of first ground terminal electrodes are disposed; ,
A third separated transmission line disposed on the side of the first signal transmission line between the pair of first ground terminal electrodes and separated from the first signal transmission line;
A pair of fourth ground terminal electrodes disposed adjacent to a side surface of the dielectric substrate opposite to a side surface of the second signal transmission line on which the pair of second ground terminal electrodes are disposed; ,
A side surface of the second signal transmission line includes a fourth separation transmission line disposed between the pair of second ground terminal electrodes and separated from the second signal transmission line, and the third separation transmission line includes A signal terminal of a high frequency probe can be connected, a pair of ground terminals of the high frequency probe can be connected to the pair of third ground terminal electrodes, and a signal terminal of the high frequency probe can be connected to the fourth separated transmission line. The interstage probe pattern structure according to claim 9, wherein the pair of fourth ground terminal electrodes are connectable to a pair of ground terminals of the high-frequency probe. A dielectric substrate;
A first signal transmission line and a second signal transmission line disposed opposite to each other on the first surface of the dielectric substrate;
A first pair of first ground terminal electrodes and a second pair of first ground terminal electrodes, which are continuously disposed adjacent to side surfaces of the first signal transmission line and the second signal transmission line on the first surface of the dielectric substrate;
A first VIA hole disposed under the first ground terminal electrode;
A back surface ground electrode disposed on a second surface opposite to the first surface of the dielectric substrate and connected to the first ground terminal electrode via the first VIA hole;
A first separated transmission line disposed on a side surface of the first signal transmission line between the first pair of first ground terminal electrodes and separated from the first signal transmission line;
A second separation transmission line disposed on a side surface of the second signal transmission line between the second pair of first ground terminal electrodes and separated from the second signal transmission line; A signal terminal of the high-frequency probe can be connected to the first ground terminal electrode of the first pair, and a pair of ground terminals of the high-frequency probe can be connected to the first pair of first ground terminal electrodes,
A signal terminal of a high-frequency probe can be connected to the second separated transmission line, and a pair of ground terminals of the high-frequency probe can be connected to the second pair of first ground terminal electrodes. Pattern structure for interstage probes. Adjacent to the first signal transmission line on which the first and second pairs of first ground terminal electrodes are disposed on the first surface of the dielectric substrate and opposite to the side surfaces of the first signal transmission line and the second signal transmission line A first pair and a second pair of second ground terminal electrodes arranged in succession,
A second VIA hole disposed under the second ground terminal electrode;
A back surface ground electrode disposed on a second surface opposite to the first surface of the dielectric substrate and connected to the second ground terminal electrode via the second VIA hole;
A third separated transmission line disposed on a side surface of the first signal transmission line between the first pair of second ground terminal electrodes and separated from the first signal transmission line;
A side surface of the second signal transmission line, the fourth separation transmission line disposed between the second pair of second ground terminal electrodes and separated from the second signal transmission line; A signal terminal of a high-frequency probe can be connected to the first pair of second ground terminal electrodes, and a pair of ground terminals of the high-frequency probe can be connected to the first pair of second ground terminal electrodes.
A signal terminal of a high-frequency probe can be connected to the fourth separation transmission line, and a pair of ground terminals of the high-frequency probe can be connected to the second pair of second ground terminal electrodes. The pattern structure for interstage probes according to claim 13.   The first separation transmission line is disposed adjacent to an end portion of the first signal transmission line, and the second separation transmission line is disposed adjacent to an end portion of the second signal transmission line. The pattern structure for interstage probes according to claim 13 or 14. A first signal transmission line disposed on a first surface of the dielectric substrate; and a pair of first ground terminal electrodes disposed adjacent to the first signal transmission line on the first surface of the dielectric substrate; Forming a pattern structure for an interstage probe having:
A signal terminal of a high frequency probe is connected to the first signal transmission line, a pair of ground terminals of the high frequency probe is connected to the pair of first ground terminal electrodes, and the first signal transmission line and the first ground are connected. A step of measuring an S parameter between terminal electrodes. The step of forming the interstage probe pattern structure further includes a second signal transmission line disposed on the first surface of the dielectric substrate so as to face the first signal transmission line, and the dielectric substrate. Forming a pair of second ground terminal electrodes disposed adjacent to the second signal transmission line on the first surface;
A signal terminal of a high frequency probe is connected to the second signal transmission line, a pair of ground terminals of the high frequency probe is connected to the pair of second ground terminal electrodes, and the second signal transmission line and the second ground are connected. The interstage measurement method according to claim 16, further comprising a step of measuring an S parameter between the terminal electrodes.   The interstage measurement method according to claim 17, further comprising a step of connecting a capacitor between the first signal transmission line and the second signal transmission line. The step of forming the inter-stage probe pattern structure further includes a first width that is disposed on an end surface of the first signal transmission line facing the second signal transmission line and has a narrower width than the first signal transmission line. Forming an end face transmission line and a second end face transmission line disposed on an end face of the second signal transmission line facing the first signal transmission line and having a narrower width than the second signal transmission line;
A signal terminal of a high-frequency probe is connected to the first end face transmission line, a pair of ground terminals of the high-frequency probe is connected to the pair of first ground terminal electrodes, and the first end face transmission line and the first Measuring the S parameter between the ground terminal electrodes;
A signal terminal of a high frequency probe is connected to the second end face transmission line, a pair of ground terminals of the high frequency probe is connected to the pair of second ground terminal electrodes, and the second end face transmission line and the second end terminal are connected. The interstage measurement method according to claim 16, further comprising: measuring an S parameter between the ground terminal electrodes.   The interstage measurement method according to claim 19, further comprising a step of connecting a capacitor between the first end face transmission line and the second end face transmission line. The step of forming the interstage probe pattern structure is further disposed on an end face of the first signal transmission line facing the second signal transmission line, and has a narrower width than the first signal transmission line, And a first separated transmission line separated from the first signal transmission line, and an end face of the second signal transmission line facing the first signal transmission line, and having a narrower width than the second signal transmission line. And forming a second separated transmission line separated from the second signal transmission line;
Connecting the first separated transmission line and the first signal transmission line with a first bonding wire;
Connecting the second separated transmission line and the second signal transmission line with a second bonding wire;
A signal terminal of a high frequency probe is connected to the first separated transmission line, a pair of ground terminals of the high frequency probe is connected to the pair of first ground terminal electrodes, and the first separated transmission line and the first ground are connected. Measuring the S parameter between the terminal electrodes;
A signal terminal of a high-frequency probe is connected to the second separated transmission line, a pair of ground terminals of the high-frequency probe is connected to the pair of second ground terminal electrodes, and the second separated transmission line and the second ground are connected. The interstage measurement method according to claim 16, further comprising: measuring an S parameter between the terminal electrodes.   The interstage measurement method according to claim 21, further comprising a step of connecting a capacitor between the first separated transmission line and the second separated transmission line.   The interstage measurement method according to claim 21, further comprising a step of connecting the first signal transmission line and the second signal transmission line with a third bonding wire. A semiconductor substrate forming a plurality of discrete transistors;
A first dielectric substrate forming a capacitor;
A second dielectric substrate forming a matching circuit;
A first signal transmission line disposed on a first surface of the first dielectric substrate; and a pair of first signals disposed on the first surface of the first dielectric substrate adjacent to the first signal transmission line. A first ground terminal electrode; a first VIA hole disposed under the first ground terminal electrode; and a second surface opposite to the first surface of the first dielectric substrate, the first ground terminal electrode A back surface ground electrode connected via the first VIA hole, and a signal terminal of a high-frequency probe can be connected to the first signal transmission line, and the pair of first ground terminal electrodes A multichip module high-frequency circuit comprising: a pattern structure for interstage probes to which a pair of ground terminals of the high-frequency probe can be connected. The interstage probe pattern structure is:
A second signal transmission line disposed on the first surface of the first dielectric substrate so as to face the first signal transmission line;
A pair of second ground terminal electrodes disposed adjacent to the second signal transmission line on the first surface of the first dielectric substrate;
A second VIA hole disposed under the second ground terminal electrode and connecting the second ground terminal electrode to the back ground electrode; and a signal terminal of a high-frequency probe can be connected to the second signal transmission line. 25. The multichip module high-frequency circuit according to claim 24, wherein the pair of second ground terminal electrodes can be connected to a pair of ground terminals of the high-frequency probe. The interstage probe pattern structure is:
A first end face transmission line disposed on an end face of the first signal transmission line facing the second signal transmission line and having a width narrower than the first signal transmission line;
A second end surface transmission line disposed on an end surface of the second signal transmission line facing the first signal transmission line and having a width narrower than that of the second signal transmission line, and the pair of first grounds 26. The terminal electrode is disposed adjacent to the first end face transmission line, and the pair of second ground terminal electrodes are disposed adjacent to the second end face transmission line. A multichip module high-frequency circuit as described in 1.   The first end face transmission line is a first separated transmission line separated from the first signal transmission line, and the second end face transmission line is a second separated transmission line separated from the second signal transmission line. 27. The multichip module high frequency circuit according to claim 26, wherein the multichip module high frequency circuit is provided.   One of the pair of first ground terminal electrodes and one of the pair of second ground terminal electrodes are formed in a common pattern, and the other of the pair of first ground terminal electrodes and the pair of second ground terminal electrodes. 28. The multi-chip module high-frequency circuit according to claim 25, wherein the other is formed in a common pattern. The plurality of discrete transistors are:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
25. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. 28. The multichip module high frequency circuit according to any one of 28.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or 30. The multichip module high-frequency circuit according to claim 29, wherein the multi-chip module high-frequency circuit is any one of diamond substrates.