JP2012003527A - Data transfer management device, data transfer management method and data transfer management program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the appropriate buffer amount of a DMA buffer.SOLUTION: A channel related information acquisition part 21 acquires the stream transfer rate and CPU processing time of the stream data of a DMA object device and a processing time necessary for completing reading from a DMA buffer as transfer time variation factors, and a determination logic execution part 23 determines the presence/absence of the buffer shortage of the DMA buffer from the transfer time variation factors and management object elements set for every DMA channel, and a buffer increase/decrease determination part 24 controls the increase/decrease of the buffer amount of the DMA buffer in accordance with the presence/absence of the buffer shortage of the DMA buffer. When it is not possible to increase the buffer amount of the DMA buffer although the buffer shortage of the DMA buffer is present, the use of a DMA channel whose priority is low is restricted based on the priority of the DMA channel.

Description

  The present invention relates to a data transfer management device, a data transfer management method, and a data transfer management program.

  For example, a video capture card is mounted on a personal computer and a broadcast program is recorded on a hard disk drive. At this time, the stream data of the video continuously output from the video capture card is DMA-transferred to a DMA (Direct Memory Access) buffer, transferred from the DMA buffer to the hard disk drive, and stored.

  A DMA control device is mounted on the motherboard of the personal computer, and this DMA control device controls the DMA transfer of the stream data to the DMA buffer. The stream data transferred to the DMA buffer is transferred to and stored in the hard disk drive under the control of a CPU (Central Processing Unit). The amount of data (stream bit rate) during DMA transfer is variable, and a plurality of DMA channels exist as communication paths for transferring data from the video capture card to the DMA buffer. Here, if the buffer amount of the DMA buffer that receives the DMA-transferred stream data is insufficient, a failure such as data loss occurs.

  The DMA buffer that receives the DMA transfer data uses a part of the main memory of the system. For this reason, if a sufficient amount of DMA buffer is secured to reduce the possibility of dropping the DMA transfer data, there is a possibility that the memory of the system will be insufficient. In this case, it is necessary to adjust the buffer amount.

  On the other hand, a method for efficiently allocating a predetermined amount of buffer to a data stream is known. According to this method, the buffer is refreshed at the timing when the queue to which the predetermined maximum number of buffers are allocated uses up the buffer storage or at the timing of a regular refresh event. Then, the free buffer is again assigned to the queue of the data stream with high priority.

JP 2000-307609 A

  As described above, the DMA buffer secures a buffer amount with a fixed value for each individual system. However, due to an increase in the number of DMA channels, complexity of the system, changes in usage, etc. There is a problem that it is difficult to secure the buffer amount.

  The present invention has been made in view of these points, and an object thereof is to control a DMA buffer to an optimum buffer amount.

  According to an aspect of the present invention, a channel-related information acquisition unit that acquires a transfer-time variation factor that fluctuates during DMA transfer, and a DMA buffer shortage based on the transfer-time variation factor that is acquired by the channel-related information acquisition unit A data transfer comprising: a determination logic execution unit for determining whether or not there is a buffer; and a buffer increase / decrease determination unit for determining whether the buffer amount of the DMA buffer is increased or decreased depending on whether or not the buffer is insufficient A management device is provided.

  According to the disclosed data transfer management device, data transfer management method, and data transfer management program, there is an advantage that the optimum buffer amount of the DMA buffer can be dynamically controlled.

It is a figure which shows an example of the system provided with the data transfer management apparatus which concerns on embodiment of this invention. It is a functional block diagram which shows the function of a data transfer control apparatus. It is a figure which shows the example of the registration data in a data registration part, Comprising: (A) shows an example of management data, (B) has shown an example of channel data. It is a figure which shows the sequence of the initialization process to a data transfer management apparatus. It is a figure which shows the processing sequence of the start and stop of DMA control which a data transfer management apparatus implements. It is a figure which shows the processing sequence of the read request | requirement of a DMA buffer to a data transfer management apparatus, and a change factor notification at the time of transfer. It is a flowchart which shows the judgment logic in a data transfer management apparatus, and the flow of a subsequent process. It is a figure which shows an example of the hardware of the computer used for embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an example of a system provided with a data transfer management device according to an embodiment of the present invention.

  This system includes a CPU 11, a DMA buffer 12, a DMA target device 13, and a hard disk drive (HDD) 14, and each is connected to a bus 15. A part of the main memory 16 is allocated to the DMA buffer 12. A DMA controller 17 that controls data transfer from the DMA target device 13 to the DMA buffer 12 is connected to the bus 15. A data transfer management device 18 is connected to the DMA control device 17.

  In the above system, the DMA control device 17 and the data transfer management device 18 are incorporated in the system in the form of a device driver, for example. The DMA target device 13 may be, for example, a PCI-Express device that is a serial transfer interface device that outputs broadcast stream data.

  2 is a functional block diagram showing functions of the data transfer control device, FIG. 3 is a diagram showing an example of registration data in the data registration unit, (A) shows an example of management data, and (B) shows channel data. An example is shown.

  The data transfer management device 18 includes an initial setting processing unit 20 and a channel related information acquisition unit 21 connected to a DMA control device 17 that controls DMA transfer of stream data, and these are connected to a data registration unit 22. Yes. The data registration unit 22 is connected to a determination logic execution unit 23, a buffer increase / decrease determination unit 24, and a channel priority determination unit 25. The determination logic execution unit 23 is connected to the buffer increase / decrease determination unit 24. The buffer increase / decrease determination unit 24 and the channel priority determination unit 25 are connected to the DMA control device 17.

  The initial setting processing unit 20 performs initial setting processing when the DMA control device 17 is activated, and registers the data in the data registration unit 22. The channel related information acquisition unit 21 acquires DMA channel related information related to DMA transfer and registers it in the data registration unit 22.

  As shown in FIG. 3, in the data registration unit 22, management data is set as a system setting at the time of initial setting processing, and channel data of each DMA channel is set. In the management data, a buffer maximum value that can be used in all DMA channels and the number of channels of the DMA channel are set as system values. The channel data includes the minimum number of buffer planes, priority, first management target element, second management target element, first transfer variation factor, second transfer variation factor, third transfer variation factor, and buffer shortage. Decision logic is registered for each channel. A DMA buffer size of one side is set as the first management target element, and a DMA buffer threshold is set as the second management target element. The variation factor at the time of transfer is a variation factor that occurs at the time of DMA transfer, and the set number is determined according to the transfer path of the stream data. When the stream data of the DMA target device 13 is stored in the hard disk drive 14, three transfer time variation factors are set. That is, here, the first transfer time variation factor is set for registration of the hard disk storage time, the second transfer time variation factor is set for the stream transfer rate registration, and the third transfer time for the CPU processing time registration. A variable factor is set.

  The determination logic execution unit 23 determines whether or not the DMA buffer 12 has a buffer shortage using the buffer shortage determination logic based on the DMA channel related information acquired by the channel related information acquisition unit 21. The buffer increase / decrease determination unit 24 determines increase / decrease of the buffer amount of the DMA buffer 12 based on the determination result of the determination logic execution unit 23. When the buffer increase / decrease determining unit 24 determines that the buffer amount of the DMA buffer 12 cannot be increased, the channel priority determining unit 25 determines the DMA controller 17 based on the priority of the DMA channel registered in the channel data. Controls DMA channel usage restrictions.

FIG. 4 is a diagram showing a sequence of initial setting processing to the data transfer management device.
When the DMA control device 17 is activated, it performs initial setting control processing for the data transfer management device 18. In the data transfer management device 18, first, the initial setting processing unit 20 receives the maximum values of all the usable DMA buffers 12 and the number of DMA channels as management data, and registers them in the data registration unit 22 (T1).

  Next, the initial setting processing unit 20 receives the management target element of the first channel from the DMA control device 17 and registers it in the data registration unit 22 (T2, T3). Here, the DMA buffer size of one surface is registered as the first management target element of the first channel, and the DMA buffer threshold is registered as the second management target element.

  Further, the initial setting processing unit 20 receives the item of the variation factor at the time of transfer of the first channel from the DMA controller 17 and registers it in the data registration unit 22 (T4, T5, T6). Here, the hard disk storage time is registered as the first transfer variation factor of the first channel, the stream transfer rate is registered as the second transfer variation factor, and the CPU processing time is registered as the third transfer variation factor.

  Next, the initial setting processing unit 20 registers in the data registration unit 22 a determination logic for determining whether or not the buffer of the first channel is insufficient for the registered first to third transfer variation factors ( T7). Since this determination logic can be registered by an expression including the number of transfer variation factors corresponding to the system performing the DMA transfer, the application environment is flexible and has high expandability.

Thereafter, the same initial setting process as that for the first channel is performed for the second and subsequent channels.
Here, a specific example of the determination logic for determining whether or not the buffer is insufficient will be described.

[Example of judgment formula 1]
When the stream data output from the DMA target device 13 is stored in the hard disk drive 14, the HDD storage time is used as a variation factor during the first transfer. The stream transfer rate is used as the second transfer variation factor. CPU processing time is used as a variation factor during the third transfer. In such a case, the determination logic registered in the channel data is the following determination logical expression.
(Variation factor at the time of first transfer + Variation factor at the time of third transfer) × Variation factor at the time of second transfer> First element to be managed × Second element to be managed × 1000 (msec) (1)
[Example of decision formula 2]
Further, when the stream data output from the DMA target device 13 is viewed in real time, the hard disk drive 14 is not used. In such a case, since the hard disk processing time is not necessary, the CPU processing time is used as the first transfer variation factor, the stream transfer rate is used as the second transfer variation factor, and the registered determination logical formula is as follows: It becomes like the formula.
First transfer variation factor × second transfer variation factor> first management target element × second management target element × 1000 (msec) (2)
[Example of decision formula 3]
When the stream data output from the DMA target device 13 is distributed to another network device or the like, the network distribution time is used as a variation factor at the time of transfer. In this case, the CPU processing time is used as the first transfer variation factor, the network processing time is used as the second transfer variation factor, and the stream transfer rate is used as the third transfer variation factor. A decision logic is registered.
(Variation factor at the time of first transfer + Variation factor at the time of second transfer) × Variation factor at the time of third transfer> First management target element × Second management target element × 1000 (msec) (3)
FIG. 5 is a diagram showing a processing sequence for starting and stopping DMA control performed by the data transfer management device.

  When starting the DMA control, the DMA control device 17 that has completed the initial setting process makes a DMA start request and a DMA buffer read request for the first channel to the data transfer management device 18 (T11). The data transfer management device 18 that has received the DMA start request starts the DMA transfer request to the DMA target device 13 when the read request is the first time (T12). Thereafter, the data transfer management device 18 repeatedly executes the DMA data transfer asynchronously with the read request from the DMA control device 17, and transfers the stream data output from the DMA target device 13 to the DMA buffer 12 as needed. store. That is, the data transfer management device 18 makes a DMA transfer request to the DMA target device 13 (T13), and receives a DMA transfer completion notification from the DMA target device 13 (T14). At this time, the stream data is transferred to and stored in the DMA buffer 12 (T15). This DMA data transfer is repeatedly performed, and stream data is sequentially stored in each surface of the DMA buffer 12. The stream data stored in the DMA buffer 12 is read in response to the previous DMA buffer read request (T11), and when the read is completed (T16), the DMA buffer 12 is made empty and the subsequent DMA data transfer is performed. Reuse. The subsequent DMA start request, DMA buffer read request (T17) and read completion (T18) of the first channel are also repeatedly executed.

When stopping the DMA control, the DMA control device 17 makes a DMA stop request to the data transfer management device 18 (T19).
FIG. 6 is a diagram showing a processing sequence of a DMA buffer read request to the data transfer management device and a transfer time variation factor notification.

  The DMA controller 17 that has executed the DMA start request collects the CPU processing time, the hard disk storage time, and the stream transfer rate, which are the fluctuation factors during the first to third transfers. Here, the CPU processing time and hard disk storage time are calculated based on the time stamp of the event requested by the DMA controller 17. The stream transfer rate is collected when the DMA control device 17 inquires the DMA target device 13.

  CPU processing time collects the time from the first DMA read request (T21) to the execution of the next DMA read request (T26), excluding the hard disk storage time. That is, the DMA controller 17 holds the time stamp A at the time of the DMA read request (T21) of the first channel to the data transfer management device 18 (S1). Next, after receiving a read response from the data transfer management device 18 (T22), the DMA control device 17 holds the time stamp B when a storage start request is issued to the hard disk drive 14 (T23) (S2). ) Holds the time stamp C at the time of storage end notification from the hard disk drive 14 (T24) (S3). Thereafter, the DMA control device 17 inquires of the DMA target device 13 about the stream transfer rate (T25), and acquires the stream transfer rate of the stream data.

When the next DMA read request for the first channel is made to the data transfer management device 18 (T26), the DMA control device 17 holds the time stamp D (S4). Therefore, the CPU processing time excluding the hard disk storage time is calculated by the following equation.
DA- (CB) (4)
The hard disk storage time is the difference between the time stamp B when the DMA controller 17 makes a storage start request to the hard disk drive 14 and the time stamp C when the storage end notification is received from the hard disk drive 14. Therefore, the hard disk storage time is calculated by the following equation.
CB (5)
The hard disk storage time, the stream transfer rate, and the CPU processing time are changed when the DMA controller 17 requests the data transfer management device 18 for the next DMA read (T26), and the data transfer management device 18 causes the first to third transfer fluctuation factors. As notified. These first to third transfer time variation factors are collected in the same way and notified to the data transfer management device 18 at the second and subsequent read requests.

  In the data transfer management device 18, the channel related information acquisition unit 21 determines the hard disk storage time, the stream transfer rate, and the CPU processing time as the first transfer factor, the second transfer factor, and the second transfer factor of the channel data of the data registration unit 22. 3 Stored in the item of variable factors during transfer. The data transfer management device 18 which has received the first to third transfer variation factors executes the determination logic according to the formula of the buffer shortage determination logic registered in the channel data (S5).

FIG. 7 is a flowchart showing the decision logic and the subsequent processing flow in the data transfer management device.
In the data transfer management device 18, first, the determination logic execution unit 23 reads the first and second management target elements, the first to third transfer variation factors, and the buffer shortage determination logic from the channel data of the data registration unit 22, Decision logic is executed (S11). Here, the above-described equation (1) of the determination logic is used.

Next, it is determined whether the DMA buffer 12 is insufficient as a result of the execution of the determination logic (S12).
Here, it is assumed that the channel data registered in the data registration unit 22 is as follows, for example.
First management target element (one side DMA buffer size) = 64K
Second management target element (DMA buffer threshold) = 80%
First transfer variation factor (HDD storage time) = 10 msec
Second transfer variation factor (stream transfer rate) = 20 Mbps (= 2560 KBytes)
Fluctuation factor during the third transfer (CPU processing time) = 15 msec
In this case, the determination logic execution unit 23 executes the DMA buffer shortage determination logic using the above determination logical expression (1). The left side of the decision formula (1) is
Left side formula = (10 + 15) × 2560 = 64000 (6)
And the right side of the decision formula (1) is
Right side expression = 64 × 80 × 1000 = 51200 (7)
It becomes. Accordingly, in the determination logical expression (1), “left side expression> right side expression” is true, and the DMA buffer shortage determination logic is established.

  When the DMA buffer shortage determination logic is established, it is determined that the buffer amount of the DMA buffer 12 is insufficient in determining whether the DMA buffer 12 is insufficient, and an attempt is made to increase one side of the DMA buffer 12. That is, the buffer increase / decrease determination unit 24 determines whether or not the DMA buffer 12 is within the buffer size that can be used in all channels when the DMA buffer 12 is further increased (S13). This is determined by comparing the maximum value of the DMA buffer 12 of management data registered in the data registration unit 22 with the buffer size of the DMA buffer 12 used in the currently used DMA channel.

  If it is determined that the buffer size does not reach the buffer size that can be used in all channels even if the DMA buffer 12 is increased by one, the DMA buffer 12 is increased by one (S14). However, if it is determined that the buffer size that can be used for all channels is reached by increasing the number of DMA buffers 12, the use of the DMA channel is restricted based on the priority of the DMA channel (S15). That is, the channel priority determination unit 25 controls the DMA controller 17 to stop the low priority channel and not accept a new request from the priority registered in the data registration unit 22. To implement.

  In step S12 for determining whether or not the DMA buffer 12 is insufficient, if it is determined that the DMA buffer 12 is insufficient, it is determined whether or not there is an increased DMA buffer 12 (S16). The process is terminated as it is.

  When the DMA buffer 12 has been increased by one plane in the buffer shortage determination logic at the time of the previous read request, the buffer increase / decrease determination unit 24 determines whether the DMA buffer 12 does not become below the minimum plane of the channel when the DMA buffer 12 is decreased by one plane. Judgment is made (S17). If the number of DMA buffers 12 is reduced by one, this process is terminated as long as it is below the minimum surface of the channel. If the DMA buffer 12 is not reduced below the minimum channel surface even if the DMA buffer 12 is reduced, the DMA buffer 12 is reduced (S18), and the process is terminated.

  As described above, the data transfer management device 18 determines whether the buffer is insufficient for each DMA read request, and dynamically controls the increase and decrease of the buffer surface. As a result, the buffer amount of the DMA buffer 12 can be ensured appropriately, and the possibility of dropping DMA transfer data is reduced.

  The data transfer management device 18 manages the maximum values of all the usable DMA buffers 12, the number of DMA channels, and the priority for each channel. For this reason, in addition to buffer increase / decrease processing, a low priority channel is regulated according to the usage rate of the usable DMA buffer 12, and control that does not accept a start request can be performed.

FIG. 8 is a diagram showing an example of computer hardware used in the embodiment of the present invention.
The computer 30 is entirely controlled by a CPU 31 corresponding to the CPU 11 of FIG. A random access memory (RAM) 32 and a plurality of peripheral devices are connected to the CPU 31 via a bus 38. The RAM 32 corresponds to the main memory 16 in FIG.

  The RAM 32 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 31. The RAM 32 stores various data necessary for processing by the CPU 31.

  Peripheral devices connected to the bus 38 include a hard disk drive 33, a graphic processing device 34, an input interface 35, an optical drive device 36, and a communication interface 37 corresponding to the hard disk drive 14 of FIG.

  The hard disk drive 33 magnetically writes and reads data to and from the built-in disk. The hard disk drive 33 is used as a secondary storage device of the computer 30. The hard disk drive 33 stores an OS program, an application program, a program having a processing function of the DMA control device 17 in FIG. 1, a data transfer management program having a processing function of the data transfer management device 18, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 39 is connected to the graphic processing device 34. The graphic processing device 34 displays an image on the screen of the monitor 39 in accordance with a command from the CPU 31. Examples of the monitor 39 include a liquid crystal display device.

  A keyboard 40 and a mouse 41 are connected to the input interface 35. The input interface 35 transmits signals sent from the keyboard 40 and mouse 41 to the CPU 31. The mouse 41 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 36 reads data recorded on the optical disk 42 using laser light or the like. The optical disk 42 is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 42 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 37 is connected to the network 43. The communication interface 37 transmits and receives data to and from other computers or communication devices via the network 43.

The processing functions of the present embodiment can be realized by the hardware as described above.
The processing contents of the functions that the DMA control device 17 and the data transfer management device 18 should have can be described in a program recorded on a computer-readable recording medium. By executing this program on a computer, the above processing can be realized on the computer. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk 42, and a semiconductor memory. When distributing to the market, store the program on a portable recording medium for distribution, or store it in a storage device of a computer connected via a network and transfer it to another computer via the network You can also. When executed by a computer, the program is stored in a hard disk device or the like in the computer, loaded into the main memory, and executed.

11 CPU
12 DMA buffer 13 DMA target device 14 Hard disk drive 15 Bus 16 Main memory 17 DMA controller 18 Data transfer management device 20 Initial setting processing unit 21 Channel related information acquisition unit 22 Data registration unit 23 Judgment logic execution unit 24 Buffer increase / decrease determination unit 25 Channel priority determination unit 30 computer 31 CPU
32 RAM
33 Hard Disk Drive 34 Graphic Processing Device 35 Input Interface 36 Optical Drive Device 37 Communication Interface 38 Bus 39 Monitor 40 Keyboard 41 Mouse 42 Optical Disc 43 Network

Claims (4)

A channel-related information acquisition unit for acquiring a transfer-time fluctuation factor that fluctuates during DMA transfer;
A determination logic execution unit that determines whether there is a buffer shortage in the DMA buffer based on the transfer-time variation factor acquired by the channel-related information acquisition unit;
A buffer increase / decrease determination unit that determines an increase or decrease in the buffer amount of the DMA buffer according to the presence or absence of the buffer shortage;
A data transfer management device characterized by comprising: A channel priority determination unit that restricts the use of the DMA channel based on the priority of the DMA channel when the buffer increase / decrease determination unit determines that the buffer amount of the DMA buffer cannot be increased;
The data transfer management device according to claim 1, further comprising: Acquire the fluctuation factor at the time of transfer that fluctuates during DMA transfer,
Determining whether or not the DMA buffer is deficient based on the transfer-time variation factor;
Increase or decrease the buffer amount of the DMA buffer according to the presence or absence of the buffer shortage,
And a data transfer management method. On the computer,
Acquires the fluctuation factor at the time of transfer, which is the fluctuation factor at the time of DMA transfer,
Determining whether or not the DMA buffer is deficient based on the transfer-time variation factor;
Increase or decrease the buffer amount of the DMA buffer according to the presence or absence of the buffer shortage,
A data transfer management program for executing a process.

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