JP2012003471A - Scan chain formation method, program and design support device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan chain formation method for suppressing the increase of delay elements and the increase of test costs while solving a timing error.SOLUTION: A scan chain is formed so that wiring length between the scan terminals of each of a plurality of scans FF can be made the shortest. Afterwards, a coordinate set X3 in which any timing error is not generated with an object scan FF in which a timing error is generated among the plurality of scans FF as a center is calculated, and one scan FF is selected so that the order of connection of the scan chain before reorder processing can be held as much as possible from among the scans FF arranged in the coordinate set X3 (steps S17 to S19, and S23). Then, the order of connection is changed so that the selected scan FF can be connected to the object scan FF (step S20).

Description

  The present invention relates to a scan chain forming method, a program, and a design support apparatus.

  Conventionally, a scan test method is known as one of LSI design for testability (DFT) (see, for example, Patent Document 1). In this scan test method, a path (scan chain) for controlling and observing a flip-flop (FF) in a logic circuit from outside is formed. That is, the FFs in the logic circuit are replaced with scan FFs, and a plurality of scan FFs are connected in series during an operation test to form a scan chain. By inputting a test signal from the input terminal of the scan chain and sequentially shifting this value, a predetermined input value is set in the combinational circuit to be tested. Next, the output value of the combinational circuit obtained by the set input value is shifted again by the scan chain and output from the output terminal. Then, by verifying this output value, it is possible to verify whether or not the combinational circuit to be tested is operating normally. In this way, it is possible to easily identify a defective portion of an integrated circuit composed of complicated circuits.

JP 2006-258694 A

  By the way, the conventional scan chain is formed by determining the connection order based on the arrangement information of the scan FFs so that the wiring length between the scan terminals of each scan FF is the shortest. However, in this case, the signal propagation time between the scan FFs is too short and a hold error may occur. Such a hold error can be improved by inserting a delay element between the scan terminals to delay the signal propagation and secure a hold time. However, with this method, the number of delay elements increases as the number of hold errors increases, causing problems such as circuit complexity and increased power consumption.

  In addition, if the wiring length between the scan terminals of each scan FF exceeds a certain distance, the signal propagation between the scan FFs takes a long time, so the hold error does not occur. However, if the signal propagation time between the scan FFs becomes too long, a setup error occurs. Such a setup error can be improved by lowering the frequency of the clock signal input to each scan FF. However, this method has a problem that the test time is increased and the test cost is increased.

  According to one aspect of the present invention, a calculation step of calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits, and the first step One data holding circuit is arranged so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest among the data holding circuits arranged in the range. A selection step of selecting, and a reordering step of changing a connection order so as to connect the selected data holding circuit and the first data holding circuit.

  According to one aspect of the present invention, it is possible to suppress an increase in delay elements and an increase in test cost while eliminating timing errors.

The schematic block diagram of a design support apparatus. (A), (b) The circuit diagram which shows the scan chain before and behind a reorder process. 6 is a flowchart for explaining scan chain reorder processing; 6 is a flowchart for explaining scan chain reorder processing; 6 is a flowchart for explaining scan chain reorder processing; (A), (b) Explanatory drawing for demonstrating the reorder process of a 1st application example. (A), (b) Explanatory drawing for demonstrating the reorder process of a 1st application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 2nd application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 2nd application example. Explanatory drawing for demonstrating the reorder process of a 2nd application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 3rd application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 3rd application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 3rd application example. (A), (b) Explanatory drawing for demonstrating the reorder process of the 3rd application example.

Hereinafter, an embodiment will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a layout design apparatus according to the present embodiment.
As shown in FIG. 1, the design support apparatus 10 is, for example, a general design support apparatus (CAD: Computer Aided Design). The design support apparatus 10 includes a central processing unit (CPU) 11, a memory 12, a storage device 13, a display device 14, an input device 15, and a drive device 16. These devices 11, 13, 14, 15 and 16 and the memory 12 are connected to each other via a bus 17.

  The CPU 11 executes a program using the memory 12 and realizes processing necessary for forming a scan chain (scan chain reorder processing and the like). The memory 12 stores programs and data necessary for providing a scan chain forming function. The memory 12 usually includes a cache memory, a system memory, a display memory, and the like.

  The display device 14 is used for displaying a layout display, a parameter input screen, and the like. As the display device 14, for example, a CRT, LCD, PDP or the like (not shown) is used. The input device 15 is used to input a request or instruction from a user and parameters. As the input device 15, for example, a keyboard and a mouse device are used.

  The storage device 13 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, and the like. The storage device 13 stores a program for forming a scan chain (hereinafter referred to as a program) and various data files (hereinafter referred to as files). In response to an instruction from the input device 15, the CPU 11 appropriately transfers data stored in a program or various files to the memory 12 and executes it sequentially. The storage device 13 is also used as a database.

  A program executed by the CPU 11 is provided on the storage medium 18. The drive device 16 drives the storage medium 18 and accesses the stored contents. The CPU 11 reads the program from the storage medium 18 via the drive device 16 and installs it in the storage device 13.

  As the storage medium 18, any computer-readable storage medium such as a memory card, a flexible disk, an optical disk (for example, CD-ROM, DVD-ROM, etc.), a magneto-optical disk (for example, MO, MD, etc.) may be used. it can. The above-mentioned program can be stored in the storage medium 18 and loaded into the memory 12 for use as necessary.

  The storage medium 18 includes a medium and a disk device that record a program uploaded or downloaded via a communication medium. Furthermore, not only a storage medium that records a program that can be directly executed by a computer, but also a storage medium that records a program that can be executed once installed on another storage medium (such as a hard disk), or is encrypted. In addition, a storage medium on which a compressed program is recorded is also included.

FIG. 2 is a block diagram illustrating an example of a scan chain.
On the scan chain shown in FIG. 2A, scan flip-flops (scan FFs) 1a to 1f are included. Each of the scan FFs 1a to 1f includes a scan-in terminal SI and a scan-out terminal SO (also collectively referred to as “scan terminals”). In the operation test, each scan FF 1a to 1f has a scan-out terminal SO of each scan FF connected to a scan-in terminal SI of the next-stage scan FF through a scan wiring, and a number of scan FFs connected in series. Yes. Specifically, in the scan chain shown in FIG. 2A, a large number of scan FFs 1a to 1f are serially arranged in the order of scan FFs 1a → 1b → 1c → 1d → 1e → 1f from the input terminal Ti to the output terminal To. It is connected. At the time of the operation test, each of the scan FFs 1a to 1f latches the data input to the scan-in terminal SI based on the clock signal input to the clock terminal (not shown) and outputs the data from the scan-out terminal SO. Therefore, it operates as a shift register.

  During normal operation, the connection between the scan-in terminal SI and the scan-out terminal SO is cut off by the switching function provided in each of the scan FFs 1a to 1f, and each of the scan FFs 1a to 1f is connected to another logic circuit.

  Here, FIG. 2B shows a scan chain reorder process (link order change process) in order to eliminate a hold error occurring between the scan FFs 1c and 1d in the scan chain shown in FIG. It shows the scan chain after it has been performed. That is, in the scan chain after the reorder processing, the connection order shown in FIG. 2A is changed so that the scan FFs 1a → 1c → 1b → 1d → 1e → 1f from the input terminal Ti to the output terminal To. To eliminate the hold error.

Next, an outline of a method for forming a scan chain while eliminating such hold errors and setup errors will be described with reference to FIG.
First, the CPU 11 executes logic circuit arrangement and wiring, and forms a scan chain based on the arrangement information of the scan FFs in the logic circuit so that the wiring length between the scan terminals of the scan FFs 1a to 1f is the shortest. (Step S1). Note that the scan chain shown in FIG. 2A is the scan chain formed in step S1.

  Subsequently, the CPU 11 executes timing analysis processing (for example, Static timing analysis: STA) on the scan chain formed in Step S1 (Step S2). If a timing error (hold error or setup error) occurs in the scan chain in this timing analysis process (YES in step S3), the CPU 11 executes a scan chain reorder process (step S4).

  Next, the CPU 11 executes the timing analysis process again on the scan chain after the reorder process (step S5). If a timing error occurs in the scan chain in this timing analysis process (YES in step S6), the CPU 11 determines whether or not the reorder process has been executed a predetermined number of times set in advance (step S7). . At this time, if the number of reorder processes has not reached the predetermined number (NO in step S7), the processes in steps S4 to S6 are repeatedly executed. On the other hand, when the number of reorder processes reaches a predetermined number (YES in step S7), the scan chain layout process is terminated.

  If no timing error has occurred in the scan chain in the timing analysis process (NO in steps S3 and S6), it is determined that the hold timing and the setup timing have converged to normal timing, and the scan chain layout process is terminated. To do.

  Next, a specific process of the scan chain reorder process in step S4 will be described with reference to FIGS. First, the first application example shown in FIGS. 6 and 7 (application example in which the scan chain shown in FIG. 2A is changed to the scan chain shown in FIG. 2B) will be described.

  First, the CPU 11 assigns numbers in order (ascending order) from the input side to the output side for each scan FF on the scan chain before the reorder process (step S11: number assignment step). Specifically, in the scan chain before the reorder process shown in FIG. 6A, each of the scan FFs 1a to 1f scans from the input terminal Ti toward the output terminal To, as in FIG. 2A. They are connected in the order of FF1a → 1b → 1c → 1d → 1e → 1f. Therefore, in this case, the scan FFs 1a, 1b, 1c, 1d, 1e, and 1f are assigned numbers “1”, “2”, “3”, “4”, “5”, and “6”, respectively. (See the numbers in each scan FF in FIG. 6A). The initial number information given to the scan chain before the reorder process is stored in the storage device 13.

  Next, the CPU 11 selects any one scan FF among the scan FFs in which the timing error has occurred in the timing analysis process as a target scan FF (first data holding circuit) to be reordered (first data holding circuit). Step S12). In this example, the CPU 11 determines whether or not a timing error has occurred from the output-side scan FF, and first selects the scan FF in which the timing error has occurred. Specifically, the CPU 11 determines whether or not a timing error has occurred in the order of scan FFs 1f → 1e → 1d → 1c → 1b → 1a. In this case, since a timing error (hold error) has occurred between the scan FFs 1c and 1d (see the broken line arrow in FIG. 6A), the scan FF 1d is selected as the target scan FF.

Subsequently, the CPU 11 calculates a minimum propagation delay time Dmin in which no hold error occurs with the target scan FF 1d as a base point (reference) (step S13). Here, the minimum propagation delay time Dmin is set such that the hold time of the scan FF is Th and the clock skew is Cs.
Dmin = Th + Cs
Can be calculated. That is, a hold error occurs when the total value of the signal delay Din inside the scan FF and the wiring delay Dline between the scan FFs is smaller than the minimum propagation delay time Dmin (= Th + Cs). Next, the CPU 11 converts the calculated minimum propagation delay time Dmin into a distance between scan FFs (specifically, a distance between scan terminals of the scan FFs) (step S14). A hold error does not occur when the scan FF and the target scan FF 1d, which are arranged at coordinates farther than the converted distance between the scan FFs, are connected by the scan wiring. That is, in these steps S13 and S14, it is possible to obtain a set of coordinates X1 (first set of coordinates) where the target scan FF1d is the base point (center) and no hold error occurs.

Next, the CPU 11 calculates a maximum propagation delay time Dmax in which no setup error occurs with the target scan FF 1d as a base point (reference) (step S14). Here, the maximum propagation delay time Dmax is T, where the clock period is T and the setup time of the scan FF is Ts.
Dmax = T−Ts + Cs
Can be calculated. That is, a setup error occurs when the total value of the signal delay Din inside the scan FF and the wiring delay Dline between the scan FFs is larger than the maximum propagation delay time Dmax. Subsequently, the CPU 11 converts the calculated maximum propagation delay time Dmax into a distance between the scan FFs (specifically, a distance between the scan terminals of the scan FFs). A setup error does not occur when the scan FF and the target scan FF 1d arranged at coordinates closer than the converted distance between the scan FFs are connected by the scan wiring. That is, in these steps S15 and S16, it is possible to obtain a set of coordinates X2 (second set of coordinates) in which the setup error does not occur with the target scan FF1d as the base point (center). As a result, a coordinate set X3 included in both the coordinate set X1 where no hold error occurs and the coordinate set X2 where no setup error occurs, that is, a set of coordinates where no timing error occurs centered on the target scan FF1d. X3 can be obtained. When the wiring angle of the scan wiring is an arbitrary angle as in this example, the coordinate set X3 is circular as shown in FIG. When the wiring angle of the scan wiring is only a right angle as in the second application example, the coordinate set X3 has a diamond shape as shown in FIG. The scan FF arranged in the coordinate set X3 is a scan FF selection candidate in which no timing error occurs when the scan wiring is connected to the target scan FF 1d. The distance between scan FFs and the base point are considered from the scan FF scan terminals and the scan FF arrangement coordinates. The numerical values of parameters (clock skew Cs and the like) necessary for calculating the minimum propagation delay time Dmin and the maximum propagation delay time Dmax vary depending on the technology used in the design, the layout, and the like.

  Next, in step S <b> 17 of FIG. 5, the CPU 11 determines whether there is a scan FF that is a selection candidate for the connection destination of the target scan FF 1 d. Specifically, in this example, since it is determined in step S12 whether or not a timing error has occurred from the output-side scan FF, selection candidates are selected from the scan-side FFs 1a to 1c that are more input than the scan FF 1d. It is determined whether or not there is a scan FF. Here, as shown in FIG. 6A, since the scan FF 1b is arranged in the coordinate set X3 (first range), it is determined that there is a scan FF as a selection candidate (YES in step S17). ). Subsequently, in this example, since the reorder process by applying the coordinate set X3 is executed from the output side (YES in step S18), the process proceeds to step S19. In this step S19, the CPU 11 selects the selection candidate scan FF (here, the scan FF 1b) with the largest number from the target scan FF 1d toward the input side among the scan FFs of selection candidates (selection step). Here, the selection candidate scan FF having the closest number from the target scan FF 1d toward the input side is selected by executing the reorder process in a state where the connection order of the scan chains formed in step S1 is maintained as much as possible. It is to do.

  Next, the CPU 11 changes the connection order of the scan FFs so as to connect the target scan FF 1d and the selection candidate scan FF 1b selected in step S19, that is, executes reorder processing of the target scan FF 1d (step S20: re-order). Order process). That is, as illustrated in FIG. 6B, the CPU 11 changes the connection destination of the scan-in terminal of the scan FF 1d from the scan FF 1c to the scan-out terminal of the scan FF 1b. As a result, the connection order is determined from the output side in the order of scan FFs 1f → 1e → 1d → 1b. Further, the CPU 11 changes the connection order of the scan FFs 1a to 1c so as to maintain the connection order of the scan chains formed in step S1 as much as possible in accordance with the change of the connection order (change process). That is, the CPU 11 sets the connection order of the scan FFs 1a, 1b, and 1c so that the initial numbers of the scan FFs 1a and 1c whose connection order is undetermined are in ascending order from the input side, that is, the scan FFs 1a → 1c → 1b. Change to In FIG. 6B, the wiring whose connection has been changed in accordance with the reorder process as described above, that is, the reorder candidate wiring is indicated by a broken line arrow.

  Next, the CPU 11 determines whether or not the reorder process has been executed by applying the coordinate set X3 to all the scan FFs (here, the scan FFs 1a to 1d) whose connection order has been changed (step S21). Here, since the coordinate set X3 is not yet applied to the scan FFs 1a to 1c (NO in step S21), the process returns to step S11, and the coordinate set X3 is applied to the scan FFs 1a to 1c. That is, it is confirmed that no timing error occurs for all the scan FFs 1a to 1c (reorder candidate wirings) whose connection order has been changed in step S20.

  Specifically, in step S11, the CPU 11 assigns numbers in order from the input terminal Ti side to the output terminal To side for each scan FF of the scan chain after the connection order is changed. Here, as shown in FIG. 7A, the scan FFs 1a, 1c, 1b, 1d, 1e, and 1f are respectively “1”, “2”, “3”, “4”, “5”, “6”. The number is given. The numbers in parentheses shown in the scan FF in the drawings after FIG. 7 are initial numbers given to the scan chain formed in step S1.

  Next, the CPU 11 selects the scan FF 1b on the most output side as the target scan FF 1b among the scan FFs 1a to 1c whose connection order has been changed (step S12). Thereafter, the CPU 11 calculates a coordinate set X3 around the scan FF 1b where no timing error occurs (steps S13 to S16: calculation step). Of the scan FFs arranged in the coordinate set X3, the scan FFs 1a and 1c on the input side of the target scan FF 1b are selection candidates (YES in step S17). The CPU 11 selects the scan FF 1c having the highest number among the selection candidate scan FFs 1a and 1c as a connection destination scan FF (step S19). As described above, since the scan FF 1c that is the connection destination of the reorder candidate wiring of the target scan FF 1b is selected as the connection scan FF, it can be determined that no timing error occurs in the scan FFs 1b and 1c. . Then, as shown in FIG. 7A, the CPU 11 determines the connection destination of the scan-in terminal of the target scan FF 1b as the scan-out terminal of the scan FF 1c (step S20).

  Similarly, the coordinate set X3 is also applied to the scan FF 1c (steps S11 to S20), and as shown in FIG. 7B, the connection destination of the scan-in terminal of the target scan FF 1c is connected to the scan-out terminal of the scan FF 1a. To confirm.

  As described above, when the application of the coordinate set X3 is completed for all the scan FFs whose connection order has been changed (YES in step S21), the CPU 11 sets the coordinate set X3 for all the scan FFs in which the timing error has occurred. It is determined whether or not the application has been completed (step S22). Here, since the application of the coordinate set X3 has been completed for all the scan FFs 1c and 1d in which the timing error has occurred (YES in step S22), the scan chain reordering process is terminated.

  By such reorder processing, the connection order (scan FF1a → 1b → 1c → 1d → 1e → 1f) before the reorder process shown in FIG. 6A is changed to the connection order (scan FF1a shown in FIG. 7B). → 1c → 1b → 1d → 1e → 1f). At this time, in the scan FFs 1a, 1b, 1c, and 1d in which the connection order is changed, the connection destination is fixed by applying the coordinate set X3 in which the timing error (hold error and setup error) does not occur. It has been resolved. Therefore, a scan chain in which the hold error and the setup error are eliminated is formed by this reorder process. In other words, the hold error and the setup error can be eliminated only by changing the connection order between the scan FFs without inserting a delay element between the scan FFs.

  When a timing error occurs in the timing analysis process for the scan chain after the reorder process, the same reorder process as described above is repeatedly executed until the number of reorder processes reaches a predetermined number.

  Next, the scan chain reordering process in the second application example will be described with reference to FIGS. FIG. 8A shows the scan chain before reorder processing formed in step S1 of FIG. In this scan chain, the scan FFs 2a to 2g are connected in the order of scan FFs 2a → 2b → 2c → 2d → 2e → 2f → 2g from the input terminal Ti to the output terminal To, and between the scan FFs 2b and 2c. A hold error has occurred.

  First, as shown in FIG. 8A, the CPU 11 adds “1”, “2”, “3”, “4”, “5” to the scan FFs 2a, 2b, 2c, 2d, 2e, 2f, and 2g, respectively. , “6” and “7” are assigned initial numbers (step S11). The initial number information given to the scan chain before the reorder process is stored in the storage device 13.

  Next, the CPU 11 selects any one scan FF among the scan FFs in which the timing error has occurred as a target scan FF (step S12). In this example, the CPU 11 determines whether or not a timing error has occurred from the scan FF on the input side, and first selects a scan FF in which a timing error has occurred. Specifically, the CPU 11 determines whether or not a timing error has occurred in the order of scan FFs 2a → 2b → 2c → 2d → 2e → 2f → 2g. In this case, since a hold error has occurred between the scan FFs 2b and 2c (see the broken line arrow), the scan FF 2b is selected as the target scan FF.

  Subsequently, by calculating a coordinate set X1 that does not cause a hold error and a coordinate set X2 that does not cause a setup error centered on the target scan FF2b, a coordinate set X3 that does not cause a timing error is calculated (steps S13 to S16). ).

  Next, the CPU 11 determines whether or not there is a scan FF that is a candidate for selection of the connection destination of the target scan FF 2b (step S17). Specifically, in this example, since it is determined whether or not a timing error has occurred from the input-side scan FF in step S12, selection candidates are selected from the scan-side FFs 2c to 2g that are more output than the scan FF 2b. It is determined whether or not a scan FF exists. Here, as shown in FIG. 8A, since the scan FF 2f is arranged in the coordinate set X3, it is determined that there is a scan FF as a selection candidate (YES in step S17). Subsequently, in this example, since the reorder process by applying the coordinate set X3 is executed from the input side (NO in step S18), the CPU 11 moves from the target scan FF 2b to the output side among the selection candidate scan FFs. The selection candidate scan FF having the smallest number (here, scan FF 2f) is selected (step S23). Here, the selection candidate scan FF having the closest number from the target scan FF 2b toward the output side is selected by executing the reorder process while maintaining the connection order of the scan chains formed in step S1 as much as possible. It is to do.

  Next, the CPU 11 changes the connection order of the scan FFs so as to connect the target scan FF 2b and the selection candidate scan FF 2f selected in step S19 (step S20). That is, as illustrated in FIG. 8B, the CPU 11 changes the connection destination of the scan-out terminal of the scan FF 2b from the scan FF 2c to the scan-in terminal of the scan FF 2f. Along with this change, the connection order of the scan FFs 2c to 2g is such that the initial numbers of the scan FFs 2c to 2e and 2g whose connection order is undetermined are in ascending order from the input side, that is, the scans 2f → 2c → 2d → 2e. → Changed to 2g (refer to broken line arrow for changed part). In addition, it can be said that the change of the connection order at this time is executed so that the scan wiring (scan path) in which the occurrence of the timing error is not detected in the timing analysis process is corrected as much as possible.

  Next, the CPU 11 confirms that no timing error occurs between the scan FFs 2f and 2c by applying the coordinate set X3 to the scan FF 2f whose connection order has been changed. Specifically, for the scan FFs 2a, 2b, 2f, 2c, 2d, 2e, and 2g on the scan chain shown in FIG. 8B, “1”, “2”, “3”, “4”, Numbers “5”, “6”, and “7” are assigned (see FIG. 9A). Subsequently, a coordinate set X3 centering on the scan FF 2f is calculated, and it is confirmed whether or not the scan FF 2c, which is a connection destination of the scan FF 2f, is arranged in the coordinate set X3 (steps S12 to S17). However, here, since the scan FF 2c is not arranged in the coordinate set X3, it is determined that a hold error occurs between the scan FFs 2f and 2c. Therefore, the CPU 11 selects the selection candidate scan FF2e arranged in the coordinate set X3 as the scan FF that is the connection destination of the target scan FF2f.

  Subsequently, as illustrated in FIG. 9A, the CPU 11 changes the connection destination of the scan-out terminal of the scan FF 2f from the scan FF 2c to the scan-in terminal of the scan FF 2e. Along with this change, the connection order of the scan FFs 2c to 2e, 2g is such that the initial numbers of the scan FFs 2c, 2d, 2g whose connection order is undetermined are in ascending order from the input side, that is, the scan FFs 2e → 2c → 2d. → Changed to 2g (refer to broken line arrow for changed part).

  Next, the CPU 11 confirms that a timing error does not occur between the scan FFs 2e and 2c by applying the coordinate set X3 to the scan FF 2e whose connection order has been changed (steps S11 to S19). Here, as shown in FIG. 9B, since the scan FF 2c is included in the coordinate set X3 centered on the scan FF 2e, the CPU 11 connects the scan-out terminal of the scan FF 2e to the scan-in of the scan FF 2c. The terminal is determined (step S20). Similarly, the CPU 11 applies the coordinate set X3 to the scan FF 2d and determines the connection destination of the scan-out terminal of the scan FF 2d as the scan-in terminal of the scan FF 2g as shown in FIG. 10 (steps S11 to S20). ). Note that the connection order between the scan FFs 2c and 2d has not been changed from before the reorder process, and a timing error has not occurred before the reorder process. Therefore, the coordinate set X3 is not applied to the scan FF 2c.

  As a result of the above processing, the application of the coordinate set X3 is completed for all the scan FFs whose connection order has been changed and all the scan FFs in which the timing error has occurred (YES in steps S21 and S22). End the reorder process.

  By such reorder processing, the connecting order of the scan FFs 2a → 2b → 2c → 2d → 2e → 2f → 2g (see FIG. 8A) is changed to the scan FFs 2a → 2b → 2f → 2e → 2c → 2d → 2g ( (See FIG. 10). Thereby, a scan chain in which the hold error and the setup error are eliminated is formed.

  Finally, the scan chain reordering process in the third application example will be described with reference to FIGS. FIG. 11A shows the scan chain before reorder processing formed in step S1 of FIG. In this scan chain, the scan FFs 3a to 3h are connected in the order of the scan FFs 3a → 3b → 3c → 3d → 3e → 3f → 3g → 3h from the input terminal Ti to the output terminal To. Further, in this scan chain, a hold error has occurred between the scan FFs 3c and 3d and between the scan FFs 3f and 3g (see broken line arrows).

  First, as shown in FIG. 11A, the CPU 11 adds “1”, “2”, “3”, “4”, “4” to the scan FFs 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, respectively. Initial numbers “5”, “6”, “7”, and “8” are assigned (step S11). The initial number information given to the scan chain before the reorder process is stored in the storage device 13.

  Next, as in the first application example, the CPU 11 executes reorder processing by applying the coordinate set X3 from the output-side scan FF. Specifically, the CPU 11 determines whether or not a timing error has occurred in the order of scan FFs 3h → 3g → 3f → 3e → 3d → 3c → 3b → 3a. In this case, since a hold error has occurred between the scan FFs 3f and 3g (see the broken line arrow), the CPU 11 selects the scan FF 3g as the target scan FF (step S12).

  Subsequently, by calculating a coordinate set X1 that does not cause a hold error and a coordinate set X2 that does not cause a setup error centered on the target scan FF 3g, a coordinate set X3 that does not cause a timing error is calculated (steps S13 to S16). ).

  Next, as shown in FIG. 11A, since the scan FFs 3d and 3e on the input side with respect to the target scan FF 3g are arranged in the coordinate set X3, it is determined that there is a selection candidate scan FF (in step S17). YES) Subsequently, since the application of the coordinate set X3 is executed from the output side in this example (YES in step S18), the largest number of the selection candidate scan FF3d (number: 4) and scan FF3e (number: 5) is selected. A selection candidate scan FF3e is selected (step S23).

  Next, as illustrated in FIG. 11B, the CPU 11 changes the connection destination of the scan-in terminal of the target scan FF 3 g from the scan FF 3 f to the scan-out terminal of the scan 3 e. Along with this change, the connection order of the scan FFs 3d to 3g is set so that the initial numbers of the scan FFs 3d and 3f whose connection order is undefined are in ascending order from the input side, that is, the scan FFs 3d → 3f → 3e → 3g. (See the dashed arrow).

  Next, the CPU 11 confirms that a timing error does not occur between the scan FFs 3e and 3f by applying the coordinate set X3 to the scan FF 3e whose connection order has been changed (steps S11 to S19). Here, as shown in FIG. 12A, since the scan FF 3f is included in the coordinate set X3 centered on the scan FF 3e, the connection destination of the scan-in terminal of the scan FF 3e is determined as the scan-out terminal of the scan FF 3f. (Step S20). Similarly, the coordinate set X3 is applied to the scan FF 3f, and as shown in FIG. 12B, the connection destination of the scan-in terminal of the scan FF 3f is determined as the scan-out terminal of the scan FF 3d (step S11). ~ S20).

  By such processing, application of the coordinate set X3 is completed for all the scan FFs 3e and 3f whose connection order has been changed (YES in step S21). However, as described above, in the scan chain of this example, a timing error also occurs between the scan FFs 3c and 3d (NO in step S22). Therefore, the CPU 11 returns to step S11 and returns to the scan FFs 3c and 3d. Execute order processing.

  First, as shown in FIG. 13A, the CPU 11 adds “1”, “2”, “3”, “4”, “4” to the scan FFs 3a, 3b, 3c, 3d, 3f, 3e, 3g, and 3h, respectively. Numbers “5”, “6”, “7”, and “8” are assigned (step S11).

  Next, since a timing error has occurred between the scan FFs 3c and 3d (see the broken line arrow), the output-side scan FF 3d is selected as the target scan FF (step S12). Subsequently, the CPU 11 calculates a coordinate set X3 centered on the target scan FF 3d (steps S13 to S16).

  Next, the CPU 11 determines whether or not there is a scan FF that is a candidate for selection of the connection destination of the target scan FF 3d (step S17). At this time, since there is no scan FF arranged in the coordinate set X3 among the scan FFs 3a to 3c on the input side from the scan FF 3d, it is determined that there is no scan FF as a selection candidate (in step S17). NO). Then, in step S24 shown in FIG. 5, the CPU 11 connects the scan FF (here, the scan FF 3b) closest to the boundary of the coordinate set X1 among the scan FFs 3a to 3c on the input side from the scan FF 3d. Select FF. More specifically, the CPU 11 selects the scan FF that is closest to the boundary line of the coordinate set X1 and has not been connected to the scan wiring among the scan FFs 3a to 3c on the input side from the scan FF 3d. When the coordinate set X3 is applied from the input-side scan FF as in the second application example, the output-side scan FF is closest to the boundary line of the coordinate set X1 than the target scan FF, and A scan FF in which scan wire reconnection is not performed is selected.

  Subsequently, as illustrated in FIG. 13B, the CPU 11 changes the connection destination of the scan-in terminal of the target scan FF 3d from the scan FF 3c to the scan-out terminal of the scan FF 3b (step S20). Along with this change, the connection order of the scan FFs 3a to 3d is such that the initial numbers of the scan FFs 3a and 3c whose connection order is undefined are in ascending order from the input side, that is, the scan FFs 3a → 3c → 3b → 3d. (See the dashed arrow).

  Next, the CPU 11 confirms that a timing error does not occur between the scan FFs 3b and 3c by applying the coordinate set X3 to the scan FF 3b whose connection order has been changed (steps S11 to S19). Here, as shown in FIG. 14A, since the scan FF 3c is included in the coordinate set X3 centered on the target scan FF 3b, the connection destination of the scan-in terminal of the scan FF 3b becomes the scan-out terminal of the scan FF 3c. Confirmed (step S20). Similarly, the coordinate set X3 is applied to the scan FF 3c, and as shown in FIG. 14B, the connection destination of the scan-in terminal of the scan FF 3c is determined as the scan-out terminal of the scan FF 3a (step S11). ~ S20).

  As a result of the above processing, the application of the coordinate set X3 is completed for all the scan FFs whose connection order has been changed and all the scan FFs in which the timing error has occurred (YES in steps S21 and S22). End the order process.

  By such reorder processing, the connecting order of the scan FFs 3a → 3b → 3c → 3d → 3e → 3f → 3g → 3h (see FIG. 11A) is changed to the scan FFs 3a → 3c → 3b → 3d → 3f → 3e → The connection order is changed from 3g to 3h (see FIG. 14B). When a timing error occurs in the timing analysis process (step S5 in FIG. 3) for the scan chain after the reorder process (for example, when a timing error occurs between the scan FFs 3b and 3d), the number of reorder processes The reorder process similar to that described above is repeatedly executed until the number reaches a predetermined number. When a margin is set when calculating the minimum propagation delay time Dmin, a timing error occurs in the timing analysis process even if the scan FF 3b is not arranged in the coordinate set X3 centered on the scan FF 3d. Sometimes not.

According to this embodiment described above, the following effects can be obtained.
(1) From the scan FFs arranged in the coordinate set X3 where the timing error does not occur, centering on the target scan FF in which the timing error has occurred, the connecting order of the scan chains before the reorder processing is maintained as much as possible. One scan FF is selected. Then, the connection order is changed so that the selected scan FF and the target scan FF are connected. Thereby, since the scan FF and the target scan FF arranged at a position where the timing error does not occur are connected, the timing error in the target scan FF can be eliminated. In other words, it is possible to eliminate the hold error or reduce the error value only by changing the connection order between the scan FFs without inserting a delay element between the scan FFs. At this time, the scan FFs arranged at positions where not only the hold error but also the setup error does not occur are selected as the connection destinations. Therefore, the setup error can be solved only by changing the connection order between the scan FFs. For this reason, it is not necessary to lower the frequency of the clock signal input to each scan FF, and the increase in test time and test cost can be suppressed.

  (2) Further, the connection destinations of the target scan FFs are selected so that the connection order of the scan chains before the reorder process formed so that the wiring length between the scan terminals of each scan FF is the shortest is maintained as much as possible. I did it. As a result, when the connection order changing process proceeds, the scan FF arranged at a position away from the target scan FF (specifically, a position away from the coordinate set X2 centered on the target scan FF). However, it is possible to avoid the situation where it does not remain as a tip. Therefore, it is possible to suitably suppress the occurrence of a setup error in the scan chain after the reorder process.

  (3) In the first and third application examples, the reorder process is executed by applying the coordinate set X3 from the scan FF on the output side. As a result, a hold error can be sent to the scan FF on the input side. For this reason, the hold error can be eliminated by adjusting the timing of the test signal input from the input terminal Ti.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
-Step S7 in the above embodiment may be omitted. In this case, for example, the reorder process (step S4) may be executed only once.

  -Step S24 in the above embodiment may be omitted. In this case, for example, when there is no scan FF as a selection candidate in step S17, the subsequent processing may be executed without changing the connection order.

In step S11 of the above embodiment, numbers may be assigned to the scan FFs on the scan chain in descending order from the input side to the output side.
In the above embodiment, a margin may be set when calculating the minimum propagation delay time Dmin and the maximum propagation delay time Dmax.

  In the above embodiment, the minimum propagation delay time Dmin and the maximum propagation delay time Dmax are not converted into the distance between the scan FFs, and these delay times Dmin and Dmax can be used as they are for searching the selection candidate scan FF. Good. That is, a first range in which no timing error occurs centering on the target scan FF may be calculated from the minimum propagation delay time Dmin and the maximum propagation delay time Dmax.

  In the above embodiment, when a timing error remains in the timing analysis process after executing the scan chain reorder process, a delay element is inserted between the scan FFs in which the timing error has occurred. Also good. Thereby, it is possible to eliminate the hold error while reducing the number of delay elements to be inserted in order to eliminate the hold error.

In the above embodiment, the present invention can be applied to the case where a scan chain is formed by a data holding circuit other than a flip-flop.
The following notes are disclosed regarding the above embodiments.

(Appendix 1)
A scan chain forming method executed by a central processing unit of a design support device,
A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
A scan chain forming method comprising:

(Appendix 2)
Before the calculating step, including a numbering step of sequentially assigning numbers to the plurality of data holding circuits on the scan chain from the input side toward the output side,
The calculating step includes a step of selecting the first data holding circuit from an output side data holding circuit among the plurality of data holding circuits,
In the selection step, among the data holding circuits arranged in the first range, the number closest to the number of the first data holding circuit on the input side than the first data holding circuit. The scan chain forming method according to appendix 1, wherein a given data holding circuit is selected.

(Appendix 3)
Before the calculating step, including a numbering step of sequentially assigning numbers to the plurality of data holding circuits on the scan chain from the input side toward the output side,
The calculating step includes a step of selecting the first data holding circuit from an input side data holding circuit among the plurality of data holding circuits,
In the selection step, among the data holding circuits arranged in the first range, the number closest to the number of the first data holding circuit on the output side than the first data holding circuit. The scan chain forming method according to appendix 1, wherein a given data holding circuit is selected.

(Appendix 4)
The calculation step includes
Calculating a first set of coordinates centering on the first data holding circuit and causing no hold error;
The scan chain according to any one of appendices 1 to 3, further comprising: calculating a second set of coordinates centering on the first data holding circuit and causing no setup error. Forming method.

(Appendix 5)
The selection step includes
In the case where there is no data holding circuit as a selection candidate within the first range,
When selecting the first data holding circuit from the data holding circuit on the output side, select the data holding circuit closest to the boundary of the set of the first coordinates on the input side than the first data holding circuit Or
When selecting the first data holding circuit from the data holding circuit on the input side, select the data holding circuit closest to the boundary of the set of the first coordinates on the output side than the first data holding circuit The scan chain forming method according to appendix 4, wherein:

(Appendix 6)
Calculating the first set of coordinates comprises:
Calculating a minimum propagation delay time in which the hold error does not occur with the first data holding circuit as a base point;
Converting the minimum propagation delay time into a distance between scan terminals of the data holding circuit,
The step of calculating the second set of coordinates includes:
Calculating a maximum propagation delay time in which the setup error does not occur with the first data holding circuit as a base point;
The scan chain forming method according to claim 4, further comprising a step of converting the maximum propagation delay time into a distance between scan terminals of the data holding circuit.

(Appendix 7)
The reordering process includes:
The connection order of the data holding circuits in which the connection order is undetermined by the connection between the data holding circuit selected in the selection step and the first data holding circuit, and the wiring length between the scan terminals of each data holding circuit is 7. The scan chain forming method according to any one of appendices 1 to 6, further including a changing step of changing the connection order of the scan chains formed to be the shortest so as to keep as much as possible.

(Appendix 8)
For the data holding circuit whose connection order has been changed in the changing step, the step of confirming that the timing error does not occur using the first range as the data holding circuit as the first data holding circuit. The scan chain forming method according to appendix 7, wherein the scan chain is formed.

(Appendix 9)
A program executed by the design support device,
A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
The program characterized by including.

(Appendix 10)
A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
A design support apparatus characterized by executing

DESCRIPTION OF SYMBOLS 10 Design support apparatus 11 Central processing unit 1a-1f, 2a-2g, 3a-3h Scan flip-flop (data holding circuit)
SI Scan-in terminal (Scan terminal)
SO scan-out terminal (scan terminal)

Claims (7)

A scan chain forming method executed by a central processing unit of a design support device,
A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
A scan chain forming method comprising: Before the calculating step, including a numbering step of sequentially assigning numbers to the plurality of data holding circuits on the scan chain from the input side toward the output side,
The calculating step includes a step of selecting the first data holding circuit from an output side data holding circuit among the plurality of data holding circuits,
In the selection step, among the data holding circuits arranged in the first range, the number closest to the number of the first data holding circuit on the input side than the first data holding circuit. 2. The scan chain forming method according to claim 1, wherein a given data holding circuit is selected. Before the calculating step, including a numbering step of sequentially assigning numbers to the plurality of data holding circuits on the scan chain from the input side toward the output side,
The calculating step includes a step of selecting the first data holding circuit from an input side data holding circuit among the plurality of data holding circuits,
In the selection step, among the data holding circuits arranged in the first range, the number closest to the number of the first data holding circuit on the output side than the first data holding circuit. 2. The scan chain forming method according to claim 1, wherein a given data holding circuit is selected. The calculation step includes
Calculating a first set of coordinates centering on the first data holding circuit and causing no hold error;
The method according to claim 1, further comprising: calculating a second set of coordinates centering on the first data holding circuit and causing no setup error. Chain formation method. The selection step includes
In the case where there is no data holding circuit as a selection candidate within the first range,
When selecting the first data holding circuit from the data holding circuit on the output side, select the data holding circuit closest to the boundary of the set of the first coordinates on the input side than the first data holding circuit Or
When selecting the first data holding circuit from the data holding circuit on the input side, select the data holding circuit closest to the boundary of the set of the first coordinates on the output side than the first data holding circuit The scan chain forming method according to claim 4, wherein: A program executed by the design support device,
A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
The program characterized by including. A calculating step for calculating a first range in which a timing error does not occur with reference to a first data holding circuit in which a timing error has occurred among a plurality of data holding circuits;
One of the data holding circuits arranged in the first range is held so as to hold the connecting order of the scan chains formed so that the wiring length between the scan terminals of each data holding circuit is the shortest. A selection step of selecting a data holding circuit;
A reordering step for changing a connection order so as to connect the selected data holding circuit and the first data holding circuit;
A design support apparatus characterized by executing

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