JP2011258992A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor with little deterioration which is caused by aging and repeated polarization and inversion, or a dielectric capacitor with high dielectric constant, thereby providing a semiconductor device having a highly reliable wiring without increase in specific resistance.SOLUTION: The semiconductor device includes an electrode formed on the surface of a semiconductor substrate. The electrode is consisted of a conductor layer having orientation. In addition to the electrode, the semiconductor device includes a barrier layer consisted of a fine crystal or an amorphous represented by the expression M1M2, where M1 is an element selected from Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V and Cr, and M2 is an element selected from Ta, Ti, Zr, Hf, W, Y, Mo and Nb.

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a step of forming a dielectric film on an electrode made of a material that is easily oxidized by a high temperature step. Further, the present invention relates to a dielectric capacitor, and particularly relates to improvement of its ferroelectricity.

  Ferroelectric memory (FERAM) has excellent features such as non-volatility, constant power operation, high-speed writing, and high rewrite resistance, and is a device that has attracted attention in recent years.

For example, as shown in FIG. 17, a ferroelectric capacitor used in this ferroelectric memory has a tungsten plug 3 formed on a silicon oxide layer 2 formed on a silicon substrate 1, and a lower electrode 5 made of platinum. , A ferroelectric layer 6 made of a PZT (PbZr _X Ti _1-X O ₃ ) film and an upper electrode 7 made of platinum are laminated.

  Here, the reason why platinum is used as the lower electrode 5 is as follows. The ferroelectric film 6 must be formed on the alignment film. This is because if formed on an amorphous film, the ferroelectricity is impaired due to poor orientation. On the other hand, the lower electrode 5 must be formed in a state insulated from the silicon substrate 1. For this reason, the silicon oxide layer 2 is formed on the silicon substrate 1. This silicon oxide layer 2 is amorphous. In general, a film formed on an amorphous film becomes a non-oriented film, but platinum has a property of forming an oriented film even if formed on an amorphous film. For this reason, platinum is often used as the lower electrode.

  However, the conventional ferroelectric capacitor as described above has the following problems.

  Since platinum easily permeates oxygen, there is a problem that the ferroelectricity decreases due to the escape of oxygen in the ferroelectric (PZT), aging, and repeated polarization inversion. That is, as shown in FIG. 18, oxygen in the ferroelectric film 6 may escape from between the platinum columnar crystals constituting the lower electrode 5.

In addition, such a problem occurs not only in a ferroelectric memory but also in a capacitor using a dielectric having a high dielectric constant.
Furthermore, tantalum silicon nitride (TaSiN) has been proposed as a wiring barrier layer. However, when oxidized, nitrogen is generated, and an oxide film is also formed in such wiring by a subsequent heat treatment. There was a problem that the performance decreased.

The present invention solves the above-mentioned problems, prevents oxidation of the underlying material, and is a ferroelectric capacitor or a dielectric having a high dielectric constant that is less deteriorated not only during manufacture but also due to repeated aging and polarization reversal. An object is to provide a capacitor.
It is another object of the present invention to provide a semiconductor device having a highly reliable wiring without an increase in specific resistance.

  In the present invention, a “capacitor” refers to a structure in which electrodes are provided on both sides of an insulator, and includes a structure having this structure regardless of whether or not it is used for charge accumulation.

The first of the present invention includes an electrode formed on the surface of the semiconductor substrate,
The electrode is composed of a conductor layer having orientation,
In addition to the electrodes,
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu,
Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
It is characterized by including the barrier layer which consists of an amorphous or microcrystal represented by these.

  In the above semiconductor device, the composition ratio of the barrier layer is determined so that the grain boundary becomes indefinite so as to prevent diffusion or spike of oxygen.

  In the semiconductor device, the surface of the semiconductor substrate is any one of a tungsten plug, a copper plug, and a polysilicon plug formed on the semiconductor substrate.

  In the semiconductor device, the surface of the semiconductor substrate is made of a material that can be oxidized at a crystallization temperature of a dielectric layer formed in an upper layer.

  In the semiconductor device, the conductive layer having the orientation is made of any one of platinum, an iridium layer, an iridium layer, or an alloy of platinum and iridium, and further includes titanium, tungsten, cobalt, molybdenum, copper, and the like. It contains at least one of silicide, alloy, or polysilicon.

  In the semiconductor device, a dielectric layer is further formed on the electrode surface.

  In the semiconductor device, the dielectric layer is PZT.

In the semiconductor device, a lower electrode formed on a surface of a semiconductor substrate, a dielectric layer formed on the lower electrode and made of a ferroelectric or a dielectric having a high dielectric constant, and formed on the dielectric layer. An upper electrode, and the lower electrode is composed of a conductive layer having orientation,
In addition to the lower electrode,
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
And a dielectric capacitor including a barrier layer made of amorphous or microcrystalline.

In the semiconductor device, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1).

  In the semiconductor device, the barrier layer includes a grading layer whose composition ratio changes.

In the semiconductor device, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1) formed on a tungsten plug, and the electrode is an Ir layer.

In the semiconductor device, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1) formed on a tungsten plug, and the electrode is a platinum layer.

The present invention also includes a lower electrode formed on the surface of a semiconductor substrate, a dielectric layer formed on the lower electrode and made of a ferroelectric or a dielectric having a high dielectric constant, and formed on the dielectric layer. And an upper electrode
The following formula M1 _x M2 _1-x (0 <x <1) between the dielectric layer and the upper electrode
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
And a dielectric capacitor including a barrier layer made of amorphous or microcrystalline.

In the semiconductor device, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1).

In the above semiconductor device, the barrier layer includes a trace amount of a constituent element of the base material.
For example, the barrier property is further improved by containing a small amount of silicon, tungsten, or copper.

The present invention includes a step of forming an electrode on the surface of a semiconductor substrate and a step of forming a dielectric film on the upper layer, and the step of forming the electrode comprises the steps of:
Forming an electrode composed of a conductive layer having orientation;
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
And a step of forming a barrier layer made of amorphous or microcrystal represented by

  In the method for manufacturing a semiconductor device, the composition ratio of the barrier layer is determined so that the grain boundary is indefinite so as to prevent diffusion or spike of oxygen, and the dielectric layer forming step includes: It is a step of forming a film at a temperature lower than the crystallization temperature of the layer.

  In the semiconductor device manufacturing method, the electrode is formed on a tungsten plug, a copper plug, or a polysilicon plug formed on a surface of a semiconductor substrate.

  In the semiconductor device manufacturing method, at least a surface layer of the electrode is formed on a material that oxidizes at a crystallization temperature of the dielectric layer.

The present invention includes an electrode formed on the surface of a semiconductor substrate, and the electrode is composed of a conductive layer having orientation, and in addition to the electrode,
A first group of Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr;
It includes a barrier layer made of amorphous or microcrystal containing at least one element selected from the second group consisting of Ta, Ti, Zr, Hf, W, Y, Mo and Nb.

  In the semiconductor device, the barrier layer is IrTaPt.

  When a ternary or quaternary or higher compound is used, the barrier effect is very good, the lattice constants can be easily aligned, and an electrode having good interface characteristics can be formed.

The present invention is effective not only in the case of a dielectric capacitor but also in the case where a heating step in an oxidizing atmosphere is involved after the formation of the wiring layer.
In addition, as a barrier layer (M1 _x M2 _1-x : (0 <x <1)) used in the present invention, Au _0.4 Fe _0.6 , Au _0.35 Ti _0.65 , Au _0.35 Zr _0.65 , Co _0.40 Hf _0.60 , Co _0.5 Mo _0.5 , Co _0.5 Ta _0.5 ,... CoTi, CoW, CoY, CoZr, CrTi, CuHf, CuTa, CuZr, FeMo, FeTi, FeW, FeY, FeZr, HfNi, HfV, IrNb, IrTa, MoNi, MoRe, MoRu, MoZr NbNi, NbPd, NbRh, NiTa, NiTi, NiW, NiY, NiZr, OsTa, OsW, PdTi, PtW, PtZr, ReTa, ReW, RhZr, RuW, RuZr, VZr, WZr, and the like are applicable.

  In addition to the above binary compounds, a first group consisting of Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr, Ta, Ti, Zr, A barrier layer made of amorphous or microcrystal containing at least one element each selected from the second group consisting of Hf, W, Y, Mo, Nb, for example, a ternary compound such as IrTiPt or a compound made of four or more elements Etc. are also applicable.

  Note that this composition ratio can be changed as appropriate, and by changing the composition ratio continuously, it is possible to improve the lattice matching with the underlying and upper layer films, but the composition ratio is continuously changed. By doing so, it is possible to obtain a material functionally close to the target value while improving lattice matching.

  Note that even a slight change in the composition ratio can cause a significant change in the crystallization temperature. In other words, it is possible to improve the lattice matching and obtain a highly reliable crystal thin film while obtaining necessary characteristics.

  Here, the microcrystal means a crystal grain size of around 10 nm or smaller and a grain boundary that does not penetrate the entire film thickness.

As described above, according to the present invention, the following formulas M1 _x M2 _1-x (0 <x <1) are used as electrodes.
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
It is made to include the barrier layer which consists of an amorphous or microcrystal represented by these. Since this amorphous or microcrystalline barrier layer has no clear grain boundary, it has a large barrier effect and prevents interdiffusion of oxygen and spikes, and this barrier layer is formed at the deposition temperature of the dielectric layer. Amorphous or microcrystalline state can be maintained without crystallization. Therefore, the escape of oxygen from the dielectric layer can be prevented, and the secular change of dielectric characteristics can be suppressed. In addition, the dielectric thin film formed on these amorphous or microcrystalline films has good orientation and can provide a highly reliable dielectric structure.

1 is a diagram showing a structure of a ferroelectric capacitor according to a first embodiment of the present invention. FIG. 3 is a diagram showing a manufacturing process of the ferroelectric capacitor according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram of the ferroelectric capacitor according to the first embodiment of the present invention. It is a SEM photograph which shows the composition ratio and film-forming condition of Ta in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio and film-forming condition of IrTa in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio and film-forming condition of IrTa in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio and film-forming condition of IrTa in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio and film-forming condition of IrTa in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio and film-forming condition of IrTa in the 2nd Embodiment of this invention. It is a SEM photograph which shows the composition ratio of Ir and the film-forming condition in the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device by the 3rd Embodiment of this invention. It is a figure which shows the relationship between the annealing temperature of the semiconductor device, and its sheet resistance. It is a figure which shows the structure of the semiconductor device by the 4th Embodiment of this invention. It is a figure which shows the structure of the ferroelectric memory by the 5th Embodiment of this invention. It is a figure which shows the result of having measured the hysteresis characteristic of the ferroelectric memory by the 5th Embodiment of this invention. It is a figure which shows the relationship between a composition and peak value of IrTa. It is a figure which shows the ferroelectric memory of a prior art example. It is explanatory drawing of the same ferroelectric memory.

FIG. 1 shows a structure of a ferroelectric capacitor as a first embodiment of the present invention.
As shown in FIG. 1, the ferroelectric capacitor according to the first embodiment of the present invention includes a lower electrode 5 made of an Ir layer having a thickness of 100 nm formed on a tungsten plug 3 of a conventional ferroelectric capacitor, The lower electrode 5 further includes a barrier layer 4 made of Ir _0.4 Ta _0.6 having a thickness of 100 nm on the tungsten plug 3 side. The barrier layer 4 is made of a ferroelectric layer 6 made of PZT having a thickness of 210 nm.

  That is, in the present invention, as shown in FIG. 2A, after forming a silicon oxide layer 2 on a silicon substrate 1 on which a desired element region is formed, a contact hole is formed.

Then, after forming a Ti layer and a TiN layer (not shown), as shown in FIG. 2B, tungsten is buried in this contact hole by a CVD method using WF ₆ to form a tungsten plug 3.

Then, as shown in FIG. 2 (c), to form the barrier layer 4 made of Ir _0.4 Ta _0.6 with a thickness of 100nm by sputtering

  Thereafter, as shown in FIG. 2D, a lower electrode 5 made of an Ir layer having a thickness of 100 nm is formed by sputtering.

  Then, after patterning the barrier layer and the lower electrode 5, a PZT thin film is formed on the upper layer by a sol-gel method as shown in FIG. 2 (e). Then, the ferroelectric layer 6 is formed through a crystallization annealing process at 625 ° C. for 1 minute by the RTA method.

  Finally, the upper electrode 7 is formed to complete the ferroelectric memory.

  According to such a configuration, a stable and highly reliable ferroelectric memory is completed without increasing the sheet resistance of the lower electrode.

  Oxidation of W and IrTa after annealing and film peeling do not occur, and it is possible to maintain a highly reliable film quality and obtain a highly reliable ferroelectric memory.

In the ferroelectric memory formed in this way, as shown in FIG. 3, since the barrier layer 4 is composed of an amorphous Ir _0.4 Ta _0.6 layer, oxygen in the ferroelectric layer 6 is the barrier layer. Transmission is blocked.

  Accordingly, it is possible to form a ferroelectric memory having a long life and high reliability with no leakage current.

The sheet resistance of the laminate of the amorphous Ir _0.4 Ta _0.6 layer having a thickness of 100 nm and the Ir layer having a thickness of 100 nm is 1 × 10 ⁻¹ Ω, and there is no problem as an electrode material.

Since Ir is a columnar crystal, the ferroelectric film 6 formed in the upper layer has extremely good orientation. Slightly permeates oxygen in the ferroelectric film 6, but the permeated oxygen is deposited around the columnar crystal as IrO ₂ and the barrier property is enhanced. On the other hand, since the amorphous Ir _0.4 Ta _0.6 layer has a higher barrier property, oxygen in the ferroelectric film is present on the substrate side due to the presence of these two layers (Ir layer 5 and amorphous Ir _0.4 Ta _0.6 layer 4). Does not penetrate.
Thereby, the ferroelectricity of the ferroelectric film 6 is greatly improved.

In the above embodiment, the amorphous Ir _0.4 Ta _0.6 layer 4 is formed only on the lower electrode 5, but the oxygen in the ferroelectric film can be obtained by interposing the amorphous Ir _0.4 Ta _0.6 layer also on the upper electrode 7. Can be reliably prevented. However, a certain degree of effect can be obtained with only one of them. Furthermore, an IrTaPt layer obtained by adding Pt to an IrTa layer is also effective.

  The ferroelectric capacitor as described above can be used as a nonvolatile memory by connecting one of the source and drain of a transistor and an upper electrode or a lower electrode, for example. Further, it goes without saying that the present invention can also be applied to an FET structure nonvolatile memory using a gate electrode sandwiched between ferroelectric electrodes.

Next, a second embodiment of the present invention will be described in which the composition of this Ir _x Ta _1-x is changed as a barrier layer. Other structures are the same as those in the first embodiment.

An Ir _x Ta _1-x layer was formed on the silicon substrate by a reactive sputtering method while changing the Ir composition ratio x. The film forming conditions were as shown in the table below.

  The crystallinity and film quality of the film obtained as a result are shown in the following table.

Furthermore, SEM photographs at this time are shown in FIGS. Here, FIGS. 4 to 9 show that Ta, Ir _x Ta _1-x (X = _0.2 , _0.4 , 0, 5, 0.6, _0.8 ,: Ir _0.2 Ta _0.8 , Ir _0.4) through a silicon film on the silicon oxide film surface. (Ta _0.6 , Ir _0.5 Ta _0.5 , Ir _0.6 Ta _0.4 , Ir _0.8 Ta _0.2 ) are formed. FIG. 10 shows iridium formed on the surface of the silicon oxide film. In the figure, silicide appears to be white at the interface.

From the XRD and SEM results, it was found that when the iridium content was 20-50%, an amorphous state was obtained. Further, when the iridium content is 60-80%, the microcrystalline state is taken.
According to the SEM results, it was found that when the iridium content was 40%, the best amorphous state was obtained without crystal grains.
Regarding the barrier property, the amorphous state is better. This is because the permeation (diffusion) of oxygen mainly passes through the crystal grain boundaries, so that the diffusion preventing effect can be further enhanced in the amorphous state.
On the other hand, in particular, when the microcrystals constituting the barrier layer can be provided with an orientation, the orientation of the barrier layer with respect to the ferroelectric film formed on the upper layer is better when the microcrystal is used. It is possible to improve.

  Next, as a third embodiment of the present invention, for the case where iridium was used as the electrode and the case where platinum was used, the composition of the barrier layer was changed and the resistivity after annealing was measured.

First, as shown in FIG. 11, a titanium layer 31 having a thickness of 40 nm and a titanium nitride layer 32 having a thickness of 80 nm are formed as an adhesive layer on the surface of the silicon substrate 1 with the silicon oxide film 2 interposed therebetween. An amorphous Ir _0.4 Ta _0.6 layer having a thickness of 100 nm was formed as the barrier layer 40 on the tungsten film 3 having a thickness of 800 nm, and an electrode 15 made of an iridium layer having a thickness of 100 nm was formed.

  After film formation with this structure, in order to observe the change in resistivity due to oxidation of the barrier material after heat treatment, oxygen annealing is performed at 400 ° C. for 30 minutes in a horizontal furnace, and then annealing is performed at 625 ° C. to 50 ° C. in RTA. The sheet resistance at each temperature was measured. The measurement result is shown by a curve a in FIG. Further, cross-sectional observation by SEM was performed in order to observe the state of oxidation of W and IrTa and film peeling after annealing.

  As a result, it can be seen that the sheet resistance does not increase up to about 700 ° C. and is maintained well without oxidation of tungsten. At 775 ° C., film peeling occurred. Although it seemed that the oxidation of IrTa started slightly at RTA of 675 ° C., the oxidation of W was suppressed to about 700 ° C. At 775 ° C., film peeling occurred.

Next, the amorphous Ir _0.4 Ta _0.6 layer having a film thickness of 100 nm as the barrier layer 40 was changed to form an amorphous Ir _0.5 Ta _0.5 layer, and the same measurement was performed for the same formed thereafter. The result is shown as curve b.

As a result, in the above structure, the oxidation of IrTa starts slightly at RTA 625 ° C., and the oxidation of W occurs at about 775 ° C.
Further, the same measurement was performed on an amorphous Ir _0.4 Ta _0.6 layer having a film thickness of 100 nm as the barrier layer 40 and the electrode layer 15 being a platinum layer having a film thickness of 100 nm and then formed in exactly the same manner. The result is shown as curve c.

  As a result, in the above structure, the oxidation of IrTa starts slightly at RTA 625 ° C., and the oxidation of W occurs at about 775 ° C. The reason why the oxidation of IrTa starts slightly at RTA 625 ° C. is because the barrier property of iridium itself is higher than that of platinum in the structure shown in the curve a.

As a further comparative example, to form the iridium oxide Ir0 ₂ layer having a thickness of 100nm as a barrier layer 40, the iridium electrodes 15 each thickness 100nm, and platinum, the same measurement for those just as formed after Went. The results are shown as curves d and e.

  As a result, in the structure of the above comparative example, IrTa is slightly oxidized and expanded at RTA 725 ° C., and film peeling occurs at the W interface.

  From the above comparison, when iridium oxide was used as the barrier layer, the oxidation of tungsten could not be stopped at the stage of RTA 625 ° C. In IrTa, the sheet resistance did not change, but it was found by SEM observation that the oxidation of IrTa itself occurred from RTA 625 ° C.

  It can also be seen that iridium has a higher oxygen barrier property, and that iridium can be used as an electrode better than platinum than in platinum.

  Furthermore, iridium oxide is formed on the surface, but since the specific resistance of iridium oxide is low and the oxygen barrier property is extremely high, an excellent barrier effect can be obtained.

  Next, a fourth embodiment of the present invention will be described. Since the oxidation of the barrier layer itself could not be prevented in the third embodiment, a structure capable of preventing the oxidation of the barrier layer itself will be described in the fourth embodiment.

As shown in FIG. 13, the barrier layer thickness is halved to form an amorphous Ir _0.4 Ta _0.6 layer 40a having a thickness of 50 nm, and an amorphous Ir _0.2 Ta _0.8 layer 40b having a thickness of 50 nm is laminated thereon. It is a barrier layer. A platinum layer 25 having a thickness of 100 nm was used as the electrode. Other structures were formed in the same manner as in the third embodiment.

And the resistivity after annealing was measured.
As a result, it was found that a slight oxidation of the barrier layer occurred at about RTA 675 ° C., and the oxidation of tungsten progressed at 725 ° C.
Next, the same measurement was performed by changing the composition of the upper layer side of the double barrier structure. That is, the barrier layer is halved to form an amorphous Ir _0.4 Ta _0.6 layer 40a having a thickness of 50 nm, and an amorphous Ir _0.8 Ta _0.2 layer 40b having a thickness of 50 nm is laminated on the upper layer, and the upper layer side And a double-layered barrier layer having an amorphous IrO ₂ layer 40b with a thickness of 50 nm.

As a result, it was found that oxidation of W occurred at RTA 625 ° C. in the Pt / IrO ₂ / Ir _0.4 Ta _0.6 / W structure.
Further, the _{Pt / Ir 0.8 Ta 0.2 / Ir} 0.4 Ta 0.6 / W structure, has occurred W oxide in Ir _0.4 oxidation of Ta _{0. 6} proceeds RTA675 ° C. at RTA625 ℃.

Further, in the Pt / Ir _0.2 Ta _0.8 / Ir _0.4 Ta _0.6 / W structure, oxidation of Ir _0.2 Ta _0.8 and Ir _0.4 Ta _0.6 proceeds at RTA 675 ° C., and oxidation of W occurs at RTA 725 ° C.

Therefore, it can be seen that this structure has a high barrier effect when Ir _0.2 Ta _0.8 is laminated. Also, good characteristics can be maintained without oxidation of tungsten in a low temperature process of 625 ° C. or lower.

  In the second to fourth embodiments, the electrode including the barrier layer has been described. However, a ferroelectric layer or a high dielectric constant dielectric layer is formed on the electrode to form a capacitor. In the case of forming another device such as an EL element, the electrode of the present invention is effective, and provides an electrode having low resistance and high reliability even when a high-temperature process step is included in a later step. It is possible.

Next, a fifth embodiment of the present invention will be described. In this example, as shown in FIG. 14, the barrier layer has a three-layer structure, a platinum layer having a thickness of 100 nm is used as the electrode 15, and the ferroelectric layer 6 made of a PZT layer is formed. Here to be able to withstand the 740 ° C. RTA, as an oxygen barrier which exits the electrode 15 made of Pt, a first barrier layer 41 made of IrO _2, the oxygen and IrO ₂ from the IrO ₂ itself A three-layer barrier using IrTa as a third barrier layer 43, in which an Ir layer is added as a second barrier layer 42 in order to barrier oxygen that has escaped, and an adhesion layer of Ir and W (tungsten plug layer 3) is also used. A structure was formed.

That is, as shown in FIG. 14, from the electrode 15 side made of a platinum layer, a first barrier layer 41 made of an IrO ₂ layer having a thickness of 65 nm and a _second barrier layer made of an iridium layer having a thickness of 50 nm below this layer. 42, and a three-layer barrier layer in which an amorphous Ir _0.4 Ta _0.6 layer 43 having a thickness of 50 nm is further laminated. The underlying structure was formed in exactly the same way as in the third embodiment.

Next explained is a method for manufacturing a ferroelectric capacitor using the electrode structure according to the fifth embodiment of the invention.
First, the surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide layer 2. Here, the thickness of the silicon oxide layer 2 was 600 nm.

Next, using titanium as a target, a titanium layer 31 with a thickness of 40 nm and a titanium nitride layer 32 with a thickness of 80 nm are formed by reactive sputtering.
Then, a W film 3 is formed by a CVD method using WF ₆ .

Thereafter, using iridium and tantalum as targets, a third barrier layer 43 made of an amorphous Ir _0.4 Ta _0.6 layer having a thickness of 50 nm is formed by reactive sputtering, and a second barrier made of an iridium layer having a thickness of 50 nm is formed thereon. A first barrier layer 41 made of an IrO ₂ layer having a thickness of 65 nm is formed on the layer 42 and further thereon, and an electrode 6 made of a platinum layer having a thickness of 100 nm is further formed on the upper layer.

Next, a PZT layer is formed as the ferroelectric layer 6 on the (lower) electrode 15 by a sol-gel method. As a starting material, a mixed solution of Pb (CH ₃ COO) ₂ .3H ₂ O, Zr (t-OC ₄ H ₉ ) ₄ , Ti (i-OC ₃ H ₇ ) ₄ was used. After spin-coating this mixed solution, it was dried at 150 ° C. (Celsius, the same applies hereinafter), and pre-baked at 400 ° C. for 30 seconds in a dry air atmosphere. After repeating this five times, heat treatment was performed at 400 ° C. for 30 minutes in an O ₂ atmosphere. Then, RTA 740 ° C. crystallization annealing was performed to form a ferroelectric layer 6 composed of a PZT layer having a thickness of 210 nm. Here, in PbZr _x Ti _1-x O ₃ , x is set to 0.52 (hereinafter referred to as PZT (52 · 48)) to form a PZT layer.

Further, an Ir layer and an IrO ₂ layer are formed on the ferroelectric layer 6 by reactive sputtering to form a two-layer upper electrode (not shown). Here, it was formed to a thickness of 200 nm. In this way, a ferroelectric capacitor is obtained.

In the ferroelectric capacitor thus formed, the tungsten plug 3 is not oxidized even after crystallization, and the oxidation of each layer does not occur.
FIG. 15C shows the hysteresis characteristics of this ferroelectric capacitor (PZT (210 nm) / Pt (100 nm) / IrO ₂ (65 nm) / Ir (50 nm) / Ta (50 nm) / W (100 nm)) structure. Results are shown. For comparison, four structures were prepared assuming that only the composition of the barrier layer was changed without changing the electrode, the ferroelectric layer, and the underlayer.

That is, the second structure: PZT (210 nm) / Pt (100 nm) / IrO ₂ (65 nm) / Ir (50 nm) / Ir _0.4 Ta _0.6 layer (50 nm) / W (100 nm), the third structure: PZT (210 nm) ) / Pt (50 nm) / IrO ₂ (65 nm) / Ir (50 nm) / Ir _0.4 Ta _0.6 layer (50 nm) / W (100 nm), fourth structure: PZT (210 nm) / Pt (100 nm) / Ir O ₂ (65 nm) / Ir (50 nm) / Ir _0.4 Ta _0.6 layer (50 nm) / W (100 nm), fifth structure: PZT (210 nm) / Pt (100 nm) / IrO ₂ (65 nm) / Ir (25 nm) / FIGS. 15B to 15E show the results of measuring the hysteresis characteristics of Ir _0.4 Ta _0.6 layer (50 nm) / W (100 nm). FIG. 15F shows the hysteresis characteristics of a ferroelectric memory formed on a silicon oxide layer instead of a tungsten plug for comparison.
In both cases, slight oxidation of W and IrTa occurred, but good hysteresis characteristics could be obtained in both cases.

Film peeling occurred at the portion where the film thickness of the first barrier layer was thin.
Since the crystallization annealing temperature was as high as 745 ° C., some oxidation was observed, but it was found that both were practically usable.

  It is also clear that the degradation of Pr is considerably improved with respect to remanent polarization. In particular, it is clear that when an IrTa barrier layer is formed on both the upper electrode and the lower electrode, the deterioration hardly occurs until 100 cycles.

  By the way, IrTa is amorphous, but by forming a platinum layer on the upper layer, the ferroelectric film formed on the upper layer is also well oriented.

  Instead of the platinum layer, a conductor layer with good orientation such as an iridium layer or an alloy of platinum and iridium may be provided. In particular, an alloy of platinum and iridium can select the lattice constant by changing the compounding ratio, and can easily match the lattice constant with the ferroelectric layer.

Moreover, in the said Example, although the two-layer structure film of the titanium layer and the titanium nitride layer was used as a joining layer, what kind of thing may be used as long as it is a material which improves joining property. For example, a platinum layer may be used.
Next, with regard to the composition ratio of IrTa, the peak characteristics change greatly as shown in FIG. 16 by slightly changing the composition ratio. Therefore, it can be seen that optimum characteristics can be obtained by slightly adjusting the composition ratio.

In each of the above embodiments, PZT is used as the ferroelectric film, but any oxide ferroelectric may be used. For example, Ba ₄ Ti ₃ O ₁₂ or SrBi ₂ Ta ₂ O ₉ may be used.

A capacitor using a dielectric layer having a high dielectric constant instead of the ferroelectric layer 6 is also effective as a capacitor according to another embodiment of the present invention. A high dielectric constant thin film having a perovskite structure of SrTiO ₃ and (Sr, Ba) TiO ₃ on which a platinum lower electrode including the barrier layer of the present invention is provided on a tungsten plug formed on the silicon oxide layer 2 Was formed as a dielectric layer. In this case, the dielectric property could be improved as in the case of the ferroelectric material. That is, it has been clarified that what has been described about the ferroelectric layer is applicable to a dielectric layer having a high dielectric constant.

  Although the ferroelectric capacitor has been described in the above embodiment, it is needless to say that the present invention is not limited to the capacitor and can be applied to other processes such as wiring through a high temperature process.

The semiconductor device of the present invention also has the following configuration.
The following formula between the electrode and the dielectric layer: M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
It is made to include the barrier layer which consists of an amorphous or microcrystal represented by these.

  According to such a configuration, since the barrier layer made of amorphous or microcrystal has no clear grain boundary, the barrier effect is large, and interdiffusion of oxygen or the like and spikes are prevented. Further, such a compound can maintain an amorphous or microcrystalline state without being crystallized at the deposition temperature of the dielectric layer. Therefore, the escape of oxygen from the dielectric layer can be prevented, and the secular change of dielectric characteristics can be suppressed. In addition, the dielectric thin film formed on these amorphous or microcrystalline films has good orientation and can provide a highly reliable dielectric structure.

  In particular, when the electrode surface is a material that oxidizes at the crystallization temperature of the dielectric layer, there is a problem in that the electrode surface is oxidized and the specific resistance increases when the barrier layer of the present invention is not interposed. According to the present invention, due to the presence of the barrier layer, escape of oxygen from the dielectric layer can be reliably prevented, and secular change in dielectric characteristics can be suppressed.

  The ferroelectric layer is made of PZT. In the case of PZT, the film formation by the sol-gel method requires a heat treatment at 700 ° C. for 1 to 60 minutes after coating. Further, according to the sputtering method, the substrate temperature or the heat treatment temperature is about 700 ° C. Further, according to the MOCVD method, the substrate temperature is about 600 to 650 ° C. However, according to such a method, even when the substrate temperature reaches about 700 ° C., the barrier layer of the present invention maintains an amorphous or microcrystalline state, does not generate gas, and is stable and increases in specific resistance. Can be suppressed.

Moreover, although the barrier layer of the present invention is amorphous or microcrystalline, when a dielectric layer is formed as an upper layer, a dielectric layer having good crystal orientation can be formed.
Therefore, it is possible to provide a dielectric capacitor with good ferroelectricity and high dielectric property.

  Preferably, in the semiconductor device manufacturing method, the electrode includes at least one of titanium, tungsten, cobalt, molybdenum, copper, or a silicide or alloy thereof.

  Preferably, in the method for manufacturing a semiconductor device, the dielectric layer is a ferroelectric layer.

  Preferably, in the semiconductor device manufacturing method, the ferroelectric layer forming step is a step of forming PZT by a sol-gel method.

Desirably, forming a lower electrode on the surface of the semiconductor substrate;
Forming a dielectric layer made of a ferroelectric material or a dielectric material having a high dielectric constant on the lower electrode;
Forming an upper electrode on the dielectric layer,
The step of forming the lower electrode further includes the following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
Including a step of forming a barrier layer made of amorphous or microcrystal represented by:
A dielectric capacitor is formed.

Preferably, in the method for manufacturing a semiconductor device, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x .

Desirably, forming a lower electrode on the semiconductor substrate surface;
Forming a dielectric layer made of a ferroelectric or a dielectric having a high dielectric constant on the lower electrode; and the following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
A dielectric capacitor is formed, including a step of forming a barrier layer made of amorphous or microcrystal represented by: and a step of forming an upper electrode on the barrier layer.

Preferably, in the above method, the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x .

  Preferably, in the method for manufacturing a semiconductor device, the barrier layer forming step includes a sputtering step of changing a target temperature, gradually changing a composition ratio, and forming a grading layer.

Preferably, including an electrode formed on the surface of the semiconductor substrate,
The electrode comprises a conductive layer having orientation,
Furthermore, the following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
It is comprised by the amorphous or microcrystal single layer represented by these.

  Preferably, in the method for manufacturing a semiconductor device, the barrier layer includes a trace amount of a constituent element of a base material.

  Similarly, according to the method of the present invention, the escape of oxygen from the dielectric layer can be surely prevented by the presence of the barrier layer, and not only the film formation but also the secular change of the dielectric characteristics can be suppressed.

  In particular, IrTa has a crystallization temperature of 900 ° C. or higher, does not generate gas even when oxidized, does not lower the conductivity, and forms a dielectric film as an upper layer. The state can be maintained, and a thin film with good orientation on the upper layer can be formed.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Tungsten plug 4 Barrier layer 5 Electrode 6 Ferroelectric layer 7 Electrode

Claims (20)

Including an electrode formed on a semiconductor substrate surface;
The electrode is composed of a conductor layer having orientation,
In addition to the electrodes,
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
A semiconductor device including a barrier layer made of amorphous or microcrystalline represented by:   2. The semiconductor device according to claim 1, wherein the composition ratio of the barrier layer is determined such that the grain boundary is indefinite so as to prevent diffusion or spike of oxygen.   The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate is any one of a tungsten plug, a copper plug, and a polysilicon plug formed on the semiconductor substrate.   3. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate is made of a material that is likely to be oxidized at a crystallization temperature of the dielectric layer.   The conductive layer having the orientation is composed of any one of platinum, an iridium layer, an iridium layer, or an alloy of platinum and iridium, and further, titanium, tungsten, cobalt, molybdenum, copper, a silicide or alloy thereof, or The semiconductor device according to claim 1, comprising at least one kind of polysilicon.   6. The semiconductor device according to claim 1, further comprising a dielectric layer formed on the electrode surface.   The semiconductor device according to claim 6, wherein the dielectric layer is PZT. A lower electrode formed on the surface of the semiconductor substrate;
A dielectric layer formed on the lower electrode and made of a ferroelectric or a dielectric having a high dielectric constant;
An upper electrode formed on the dielectric layer,
The lower electrode is composed of a conductive layer having orientation,
In addition to the lower electrode,
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu,
Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
A semiconductor device comprising a dielectric capacitor including a barrier layer made of amorphous or microcrystalline. The semiconductor device according to claim 8, wherein the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1).   The semiconductor device according to claim 8, wherein the barrier layer includes a grading layer whose composition ratio changes. The barrier layer is made of iridium tantalum layer formed on the tungsten plug _{Ir x Ta 1-x (0} <x <1), the lower electrode semiconductor device of claim 8, wherein the Ir layer. The barrier layer is made of iridium tantalum layer formed on the tungsten plug _{Ir x Ta 1-x (0} <x <1), the lower electrode semiconductor device according to claim 8 which is a platinum layer. A lower electrode formed on the surface of the semiconductor substrate;
A dielectric layer formed on the lower electrode and made of a ferroelectric or a dielectric having a high dielectric constant;
An upper electrode formed on the dielectric layer,
Between the dielectric layer and the upper electrode,
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu,
Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
A semiconductor device comprising a dielectric capacitor including a barrier layer made of amorphous or microcrystalline. The semiconductor device according to claim 13, wherein the barrier layer is formed of an iridium tantalum layer Ir _x Ta _1-x (0 <x <1).   The semiconductor device according to claim 13, wherein the barrier layer contains a trace amount of a constituent element of a base material. A step of forming an electrode on the surface of the semiconductor substrate, and a step of forming a dielectric film on the upper layer;
Forming an electrode comprising a conductive layer having orientation; and
The following formula M1 _x M2 _1-x (0 <x <1)
M1: Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr
M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb
A method for manufacturing a semiconductor device, comprising a step of forming a barrier layer made of amorphous or microcrystal represented by: The composition ratio of the barrier layer is determined so that the grain boundary is indefinite to the extent that oxygen diffusion or spikes can be prevented,
The method of manufacturing a semiconductor device according to claim 16, wherein the forming of the dielectric layer is a step of forming a film at a temperature lower than a crystallization temperature of the barrier layer.   18. The method of manufacturing a semiconductor device according to claim 16, wherein at least a surface layer of the electrode is formed on a material that may be oxidized at a crystallization temperature of the dielectric layer. Including an electrode formed on a semiconductor substrate surface;
The electrode is composed of a conductor layer having orientation,
In addition to the electrodes,
A first group of Au, Pt, Ir, Pd, Os, Re, Rh, Tu, Cu, Co, Fe, Ni, V, Cr;
A semiconductor device including a barrier layer made of amorphous or microcrystal containing at least one element selected from the second group consisting of Ta, Ti, Zr, Hf, W, Y, Mo, and Nb.   The semiconductor device according to claim 19, wherein the barrier layer is IrTaPt.

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