JP2011258943A5 - Method of manufacturing transistor - Google Patents
Method of manufacturing transistor Download PDFInfo
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- JP2011258943A5 JP2011258943A5 JP2011106452A JP2011106452A JP2011258943A5 JP 2011258943 A5 JP2011258943 A5 JP 2011258943A5 JP 2011106452 A JP2011106452 A JP 2011106452A JP 2011106452 A JP2011106452 A JP 2011106452A JP 2011258943 A5 JP2011258943 A5 JP 2011258943A5
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- reaction chamber
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- transistor
- impurity
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Claims (5)
装置内の反応室の内壁を加熱して、前記反応室の内壁から不純物を放出させた後、
前記反応室内にフッ素化合物ガスを導入して、プラズマを形成し、前記反応室の内壁から放出した不純物および前記反応室に残留していた不純物を除去し、
前記不純物を除去した反応室の内壁を加熱し続けながら、前記反応室にシリコン元素を含む堆積性気体を導入し、電力を供給して前記ゲート絶縁膜を形成することを特徴とするトランジスタの作製方法。 In a transistor in which a gate electrode and an oxide semiconductor film overlap with each other through a gate insulating film,
After heating the inner wall of the reaction chamber in the apparatus to release impurities from the inner wall of the reaction chamber,
A fluorine compound gas is introduced into the reaction chamber to form a plasma, and the impurities released from the inner wall of the reaction chamber and the impurities remaining in the reaction chamber are removed.
While continuously heating the inner wall of the reaction chamber from which the impurities have been removed, a deposition gas containing a silicon element is introduced into the reaction chamber, and power is supplied to form the gate insulating film. Method.
装置内の反応室の内壁を加熱して、前記反応室の内壁から不純物を放出させた後、
前記反応室内を排気して、前記反応室の内壁から放出した不純物および前記反応室に残留していた不純物を除去し、
前記不純物を除去した反応室の内壁を加熱し続けながら、前記反応室にシリコン元素を含む堆積性気体を導入し、電力を供給して前記ゲート絶縁膜を形成することを特徴とするトランジスタの作製方法。 In a transistor in which a gate electrode and an oxide semiconductor film overlap with each other through a gate insulating film,
After heating the inner wall of the reaction chamber in the apparatus to release impurities from the inner wall of the reaction chamber,
The reaction chamber is evacuated to remove impurities released from the inner wall of the reaction chamber and impurities remaining in the reaction chamber.
While continuously heating the inner wall of the reaction chamber from which the impurities have been removed, a deposition gas containing a silicon element is introduced into the reaction chamber, and power is supplied to form the gate insulating film. Method.
前記反応室の内壁は、前記反応室の外壁面に密着させた加熱装置により、１００℃以上３５０℃以下の温度に加熱して、
前記反応室の内壁から放出した不純物および前記反応室に残留していた不純物を除去することを特徴とするトランジスタの作製方法。 In claim 1 or 2,
The inner wall of the reaction chamber is heated to a temperature of 100 ° C. or more and 350 ° C. or less by a heating device in close contact with the outer wall surface of the reaction chamber,
A method for manufacturing a transistor, comprising removing an impurity released from an inner wall of the reaction chamber and an impurity remaining in the reaction chamber.
前記反応室の内壁は、前記反応室の内壁面に密着させた加熱装置により、１００℃以上３５０℃以下の温度に加熱して、
前記反応室の内壁から放出した不純物および前記反応室に残留していた不純物を除去することを特徴とするトランジスタの作製方法。 In claim 1 or 2,
The inner wall of the reaction chamber is heated to a temperature of 100 ° C. or more and 350 ° C. or less by a heating device closely attached to the inner wall surface of the reaction chamber,
A method for manufacturing a transistor, comprising removing an impurity released from an inner wall of the reaction chamber and an impurity remaining in the reaction chamber.
前記反応室の内壁は、前記反応室の内壁中に埋設させた加熱装置により、１００℃以上３５０℃以下の温度に加熱して、
前記反応室の内壁から放出した不純物および前記反応室に残留していた不純物を除去することを特徴とするトランジスタの作製方法。 In claim 1 or 2,
The inner wall of the reaction chamber is heated to a temperature of 100 ° C. or more and 350 ° C. or less by a heating device embedded in the inner wall of the reaction chamber,
A method for manufacturing a transistor, comprising removing an impurity released from an inner wall of the reaction chamber and an impurity remaining in the reaction chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011106452A JP5697534B2 (en) | 2010-05-14 | 2011-05-11 | Method for manufacturing transistor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010111694 | 2010-05-14 | ||
| JP2010111694 | 2010-05-14 | ||
| JP2011106452A JP5697534B2 (en) | 2010-05-14 | 2011-05-11 | Method for manufacturing transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011258943A JP2011258943A (en) | 2011-12-22 |
| JP2011258943A5 true JP2011258943A5 (en) | 2014-05-22 |
| JP5697534B2 JP5697534B2 (en) | 2015-04-08 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011106452A Expired - Fee Related JP5697534B2 (en) | 2010-05-14 | 2011-05-11 | Method for manufacturing transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5697534B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI567823B (en) * | 2014-12-22 | 2017-01-21 | 群創光電股份有限公司 | Display panel and method for manufacturing the same |
| US10622214B2 (en) | 2017-05-25 | 2020-04-14 | Applied Materials, Inc. | Tungsten defluorination by high pressure treatment |
| US10179941B1 (en) | 2017-07-14 | 2019-01-15 | Applied Materials, Inc. | Gas delivery system for high pressure processing chamber |
| JP6947914B2 (en) | 2017-08-18 | 2021-10-13 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Annealing chamber under high pressure and high temperature |
| US10276411B2 (en) | 2017-08-18 | 2019-04-30 | Applied Materials, Inc. | High pressure and high temperature anneal chamber |
| CN117936420A (en) | 2017-11-11 | 2024-04-26 | 微材料有限责任公司 | Gas delivery system for high pressure processing chamber |
| JP2021503714A (en) | 2017-11-17 | 2021-02-12 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Capacitor system for high pressure processing system |
| KR20230079236A (en) | 2018-03-09 | 2023-06-05 | 어플라이드 머티어리얼스, 인코포레이티드 | High pressure annealing process for metal containing materials |
| US10950429B2 (en) | 2018-05-08 | 2021-03-16 | Applied Materials, Inc. | Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom |
| US10748783B2 (en) | 2018-07-25 | 2020-08-18 | Applied Materials, Inc. | Gas delivery module |
| WO2020117462A1 (en) | 2018-12-07 | 2020-06-11 | Applied Materials, Inc. | Semiconductor processing system |
| JP7304966B2 (en) * | 2019-04-25 | 2023-07-07 | アプライド マテリアルズ インコーポレイテッド | Moisture barrier film with low refractive index and low water vapor transmission rate |
| JP7359000B2 (en) | 2020-01-20 | 2023-10-11 | 東京エレクトロン株式会社 | Apparatus for processing a substrate and method for processing a substrate |
| US11901222B2 (en) | 2020-02-17 | 2024-02-13 | Applied Materials, Inc. | Multi-step process for flowable gap-fill film |
Family Cites Families (12)
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| KR0145302B1 (en) * | 1988-04-28 | 1998-08-17 | 카자마 젠쥬 | Plasma processing method |
| JPH05198515A (en) * | 1992-01-23 | 1993-08-06 | Fujitsu Ltd | Semiconductor treatment device and semiconductor pretreatment device |
| JPH05335248A (en) * | 1992-05-29 | 1993-12-17 | Toshiba Corp | Thin film manufacture |
| JP3279459B2 (en) * | 1995-07-20 | 2002-04-30 | 株式会社日立製作所 | Single wafer processing apparatus and gas supply control method for single wafer processing apparatus |
| JPH09148322A (en) * | 1995-11-22 | 1997-06-06 | Sharp Corp | Method for forming silicon oxide film and plasma cvd film forming apparatus |
| JPH11243222A (en) * | 1998-02-26 | 1999-09-07 | Canon Inc | Semiconductor film-forming device, method for manufacturing semiconductor film, and method for manufacturing photovoltaic element |
| JP2000012463A (en) * | 1998-06-17 | 2000-01-14 | Mitsubishi Electric Corp | Film formation device |
| JP2002346367A (en) * | 2001-05-23 | 2002-12-03 | Nec Corp | Vacuum apparatus, method for controlling degree of vacuum in the apparatus, and program for controlling degree of vacuum |
| JP4482319B2 (en) * | 2003-12-15 | 2010-06-16 | 日本碍子株式会社 | Reaction vessel |
| JP2006097080A (en) * | 2004-09-29 | 2006-04-13 | Hitachi Kokusai Electric Inc | Substrate treatment device |
| JP4720266B2 (en) * | 2005-04-08 | 2011-07-13 | 東京エレクトロン株式会社 | Film forming method, film forming apparatus, and computer program |
| JP5377940B2 (en) * | 2007-12-03 | 2013-12-25 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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2011
- 2011-05-11 JP JP2011106452A patent/JP5697534B2/en not_active Expired - Fee Related
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