JP2011257989A - Image compression encoding apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an expanded function by changing software and firmware.SOLUTION: An image compression encoding apparatus for performing a predetermined encoding process on an inputted image frame to compress an information amount of the image frame has a CPU and a FPGA and comprises an expanded function management function for determining propriety of function expansion and providing a function by using a plurality of registers relating expanded function management built in at least one of the CPU and the FPGA.

Description

  The present invention relates to an image compression encoding apparatus that compresses an information amount of an image frame by performing a predetermined encoding process on the input image frame.

  Conventionally, in the field of video data compression technology, an object is to provide a device capable of generating compressed video data having an appropriate amount of data and reducing the time required for video data compression processing. Proposals made are known. In this proposal, preprocessing, flatness, and intra AC generation for compressing and encoding video data (flats and intra AC are parameters indicating the difficulty level of a picture to be compressed into an I picture) Each process such as calculation of a prediction error amount (ME residual) of video motion prediction and delay processing of each picture of input video data is executed. In the proposal, after the delay processing of each picture of the video data, the approximation processing of the actual difficulty data indicating the difficulty of the picture pattern of each picture by ME residual, flatness, and intra AC is further performed. From the actual difficulty level data, the process of calculating the target data amount of the compressed video data and the compression encoding process so that the data amount of the compressed video data becomes substantially the target data amount are also executed.

  In order to reduce the bandwidth required for data transfer between the encoding processing LSI and external memory, considering application to high-resolution applications using the MPEG-4 / AVC standard that requires low delay. The first delay memory receives the input image frame output from the motion detection processing unit, and delays the output to the first adder for performing the prediction residual generation process for a predetermined time. The second delay memory receives the inter predicted luminance image frame and delays the output to the prediction selection circuit for a predetermined time. The third delay memory receives the motion vector information output from the motion detection processing unit, and delays the output of the motion vector information to the inter prediction color difference image creation processing unit for a predetermined time (Patent Document 1). reference).

  In the conventional method for providing an extended function of an image compression coding apparatus, it has been common to provide a target function by newly adding a board or a module that realizes a necessary function.

  Technologies and man-hours related to the installation of new boards and modules for providing extended functions, module integration, ensuring the reliability of the combined interface in that case, operation confirmation method by incorporating, construction of confirmation environment, confirmation man-hours, etc. It is necessary to solve the problem.

JP 2010-81498 A (Built-in Lab.)

  An object of the present invention is to provide an extended function by changing software and firmware.

  In order to achieve the above object, the present invention provides a software and firmware in an image compression encoding apparatus that compresses an information amount of an image frame by performing a predetermined encoding process on the input image frame. It has a means to expand the function by at least one of the software, and determines whether or not the function can be expanded by using a plurality of registers related to the extended function management built in the means for extending the function by at least one of the software and the firmware In addition, the present invention is an image compression coding apparatus characterized by having an extended function management function for providing a function.

  As described above, according to the present invention, an extended function can be easily provided by changing software and firmware.

1 is a block diagram showing the configuration of an image compression coding apparatus that realizes an extended function by changing the firmware of an FPGA according to an embodiment of the present invention. 1 is a block diagram showing a configuration of an image compression coding apparatus that realizes an extended function by changing CPU software according to an embodiment of the present invention. FIG. 1 is a schematic diagram of realizing an extended function of an image compression coding apparatus according to an embodiment of the present invention. The schematic diagram of the extended function provision register of the provided function classification of one Example of this invention The schematic diagram of the system setting area | region of the system memory map of one Example of this invention Schematic diagram of the vendor area of the system memory map of one embodiment of the present invention

  The block diagram which shows the structure of the image compression encoding apparatus which implement | achieves an extended function implementation | achievement operation | movement by the change of the firmware of FPGA of 1 Example of this invention about the operation | movement of extended function implementation | achievement of the image compression encoding apparatus of 1 Example of this invention FIG. 1, FIG. 2 is a block diagram showing the configuration of an image compression coding apparatus that realizes an extended function by changing the software of the CPU of one embodiment of the present invention, and the image compression coding apparatus of one embodiment of the present invention FIG. 3 of the schematic diagram for realizing the extended function of FIG. 4, FIG. 4 of the schematic diagram of the extended function providing register of the first embodiment of the present invention, and the schematic diagram of the system setting area of the system memory map of the first embodiment of the present invention. 5 and FIG. 6 which is a schematic diagram of a vendor area of a system memory map according to an embodiment of the present invention.

FIG. 1 is a block diagram showing a configuration of an image compression encoding apparatus that realizes an extended function by changing the firmware of the FPGA according to an embodiment of the present invention. In FIG. Realized.
The F / W management register is a register that manages the installation status of a function implementation module of firmware (FPGA or the like). (In this specification, “1” is treated as a mounted state, and “0” is treated as unmounted.)

The extension function is not limited to the F / W of the FPGA, and the extended function may be realized by a management register of any hardware such as a logic IC (hereinafter, H / W).
The H / W management register is a register that manages the mounting state of devices, modules, and the like that can be provided in the hardware constituting the product. (In this specification, “1” is treated as a mounted state, and “0” is treated as unmounted.)

  In the block diagram showing the configuration of an image compression coding apparatus that realizes an extended function by changing the software of the CPU according to one embodiment of the present invention, the extended function is realized by a software (hereinafter referred to as S / W) management register of the CPU. Is done.

  In order to realize extended functions, it is necessary to enable or disable function expansion in all registers, and it is basic to provide products in a situation where H / W management registers are enabled at the minimum. It becomes.

  The S / W management register is a register that manages the state of incorporation of the software function implementation module. (In this specification, “1” is treated as a mounted state, and “0” is treated as unmounted.)

  Here, an extended function providing method is shown in FIG. Here, as an example, a method for providing the extended function 2 that requires H / W as a function extension and the extended function 4 that can be realized only by F / W without requiring H / W will be described. The configuration of the products currently provided is shown on the left, and only the basic functions are provided. Accordingly, the function expansion modules 1, 2, and 3 as the H / W configuration are displayed in broken lines because there is an H / W that realizes the function but is not provided as a function. Similarly, whether the function is provided in the FPGA (F / W function) or the function expansion 4 is also indicated by a broken line. At this time, when the request for the function expansions 2 and 4 occurs as the requested function expansion, provision of the expansion functions 2 and 4 is realized by performing only the S / W upgrade and the F / W upgrade from the outside. (At this time, it is not possible to make a general judgment, but by mounting the functional module 2 in some cases, it may be possible to avoid the board division loss of the main body board configuration.) The product configuration example after providing the extended function is shown on the right side. Function module 2 is enabled by S / W update (extended function 2 control software, function extension 4 control software), and F / W update (function extension 4 realization Firmware), resulting in new functions without changing the hardware configuration. Can be provided.

  In other words, all functions provided in this specification are managed by S / W, and the decision to provide or not to provide that function is managed by software. Therefore, H / W management registers and S / W management related to extended functions It has a register and F / W management register (Fig. 4).

  The general system memory map is roughly divided into the vendor area and user area (Fig. 5). The hardware management register, S / W management register, and F / W management register are the device area information as the contents of the vendor area. It is the same as the manufacturer information, etc., and is provided in a situation where it cannot be rewritten by the user. In addition, for the sake of simplification of explanation, the detailed description is described with the bit position (horizontal axis) unified, but as a countermeasure against erroneous writing of software, a method in which the bit position is not unified is also possible. This will be described with reference to FIG. Simple management is realized by securing the extended H / W, F / W, and S / W setting areas in a continuous area and unifying the horizontal position for the bit position. As a countermeasure against erroneous writing, a discontinuous area is provided in the vendor area, and the bit position is shifted. In the case of this figure, the extended H / W management register is mapped to the upper vendor area, the F / W management register to the middle, and the S / W management register to the lower. For example, the bit position for the extended function 2 is stored in each register. What is necessary is just to carry out like LSB, LSB + 1, and LSB + 2.

  In this explanation, the configuration example in which all the management registers are arranged in the vendor area has been explained. However, the H / W management register is similarly the vendor area, the S / W management register is the software work area, and the F / W management register. A similar proposal can be realized by configuring a register in the FPGA and providing a register capable of providing a function by itself.

  There are two types of S / W upgrade methods: common upgrade and individual upgrade. In the former case, it is possible to adapt to all products with one upgrade compatible file, and the latter is an upgrade file specifying individual products. The individual recognition information of the individual update file at this time is realized by using a unique code such as a manufacturing number or a MAC address that can be individually recognized. Regarding the proper use of the two, the upgrade to the additional function as the basic function is performed in the former, and the latter in the individual correspondence such as the function expansion, such as the latter.

  Technologies and man-hours related to the installation of new boards and modules for providing extended functions, module integration, ensuring the reliability of the combined interface in that case, operation confirmation method by incorporating, construction of confirmation environment, confirmation man-hours, etc. The extended function can be realized by changing only the software and firmware.

1, 2, 3, 4: Image compression encoding device,

Claims (1)

In an image compression encoding apparatus that compresses the amount of information of the image frame by performing a predetermined encoding process on the input image frame,
Means for extending the function by at least one of software and firmware, and a plurality of registers for managing the extended function incorporated in the means for extending the function by at least one of the software and firmware. An image compression coding apparatus comprising an extended function management function for determining availability and providing a function.