JP2011257840A - Data regeneration device and data regeneration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of being unable to transfer a serial data signal through multiple repetitions per basic cycle.SOLUTION: A data regeneration device 4 according to an embodiment comprises: a personal computer body 4a which has a nonvolatile memory unit 16 for holding recorded data, a CPU 19, a volatile memory unit 23 and an input-output bus 20; and a serial transmission card 15 which generates multiple serial data signals from regeneration data transferred from the volatile memory unit 23 respectively and transmits each of the serial data signals to a signal processor 2 per basic cycle via a transmission path 3. The serial transmission card 15 generates each of the serial data signals within a period longer than a response processible time of the CPU 19, which is obtained by multiplying the basic cycle by the preset number of transmissions, and after a lapse of the period, it serially transmits each of the serial data signals per processing cycle at regular intervals within a subsequent period longer than the time.

Description

  One embodiment relates to a data reproducing apparatus and a data reproducing method.

  A radar device that calculates the distance and direction of the moving target is provided with a signal processing device, and DSP software using a DSP card or the like is mounted on the signal processing device. When debugging DSP software, the DSP card performs signal processing operations on serial data signals for N channels output from the antenna unit. In debugging, data control is performed until serial data signals for each channel are transferred or processed at a predetermined timing, whether a correct answer is output, or until a correct answer is output. It is verified whether or not. Data control means that each serial data signal is read from a storage medium and output within a basic period having a time value in the range of, for example, 50 to 100 μs, and signal processing operations for each channel are executed for each basic period. Point to.

  The radar apparatus detects a radar reception wave and outputs a large amount of data. Conventionally, a data collection apparatus that collects data measured by a remote radar apparatus and accumulates the measured data is known (see Patent Document 1). In the actual environment, the data output by the radar device is stored as actual measurement data in a large-capacity external storage device. The recorded data is read out by the data reproducing apparatus and used for debugging. In debugging, recorded data in an actual environment is read from an external storage device by a data reproducing device and sent to a signal processing device, and the output of the DSP on the DSP card is monitored. The signal processing apparatus performs a signal processing operation, and it is verified whether the result matches the result derived from the arithmetic expression.

  In the debugging, it is further verified whether the data control is correctly performed from the time when the recording data at a high rate is input to the signal processing apparatus until the calculation is output. High-speed recording data refers to a train of pulse signals having a repetition period of 50 μs, for example. When the given measured data is sequentially signal-processed, it is necessary to verify the process of data processing, the operation of each process, the control of the operation timing, and the like.

  Real-time control is required for a radar apparatus or an image processing apparatus that visualizes the position of an object using radar information. The radar device and the image processing device have a feature that the transfer rate of input serial data to be processed is as high as 100 to 400 Mbytes / sec.

  In the radar apparatus, the data processing cycle is as short as several tens of microseconds to several hundreds of milliseconds, the amount of data to be processed is huge, and the data rate is as high as 100 to 400 Mbytes / sec. For this reason, it is important to transmit the test data and the data stored in the actual environment at the same control timing as the operation cycle on the DSP card which is this device.

  Currently, various data reproducing apparatuses are commercially available. A commercially available data reproducing apparatus has a mechanism that absorbs the high speed of data communication and the low speed of an external storage device (for example, RAID HDD, silicon DISK, etc.), and this mechanism is realized by a technology unique to each company.

  Regarding the data reproduction method in which the data to be collected is human system response data and the data generation cycle is long and the data generation density is low, conventionally, radar information on aircraft etc. and operation data corresponding to input operations by controllers etc. There is known a radar information processing apparatus that enables recording / reproducing output of drawing data displayed in conformity with a radar screen (for example, Patent Document 2).

JP 2009-199315 A JP 2007-193516 A

  However, the common point between commercially available data playback devices is that each company's proprietary technology realizes a mechanism that absorbs the high speed of data communication and the low speed of external storage devices (for example, RAID HDD, silicon DISK, etc.). This point leads to non-genericity and high cost of the device.

  A personal computer equipped with a general-purpose operating system (OS) cannot execute processing for reading and transferring a serial data signal at a high rate. Since the control is transferred to the OS from when the data read command is received from the host device to when the data is read, the personal computer CPU reads a huge amount of data from the RAID HDD or silicon disk within an extremely short time. Cannot be transferred to the debug target via the communication bus. A personal computer CPU cannot transfer a serial data signal 1000 times continuously at a transmission interval in the range of 50 to 100 μs such that the radar device outputs.

  With a general-purpose personal computer and a general-purpose communication bus, recording data cannot be read from an external storage device, no matter how good a processor or data bus is used. It is impossible to reproduce or transfer recording data of a plurality of channels, each of which has a short time interval and is generated at a constant period.

  In order to solve such a problem, according to one embodiment, a nonvolatile memory that holds recording data for verifying the operation of a signal processing device that repeatedly executes a process on a data signal at a plurality of basic cycles of the process. And a non-volatile storage unit that is accessed via an internal bus and has a time longer than the basic cycle as a response processable time. A personal computer body having an input / output bus connected to the CPU and the volatile storage unit via a bus protocol conversion unit, and the personal computer body via the input / output bus of the personal computer body, respectively. A plurality of serial data signals are generated from the reproduction data transferred from the volatile storage unit, and each serial data signal is transmitted through the transmission path for each basic period. A serial transmission card that transmits to the signal processing device, and the serial transmission card is a period longer than a time during which the CPU can perform response processing obtained by multiplying the basic cycle by a preset number of transmissions. The serial data signals are generated in the serial data signal, and the serial data signals are serially transmitted at regular intervals for each processing cycle within the next period longer than the time after the elapse of this period. A playback device is provided.

  According to another embodiment, a serial transmission card connected via a transmission line is mounted on a signal processing device that repeatedly executes a process on a data signal for each basic period of the process, and this signal The CPU of the personal computer main body connected to the non-volatile storage unit that holds the recording data for verifying the operation of the processing device instructs the serial transmission card to start transmission, and sets the number of transmissions set in advance in the basic period. The serial transmission card serially transmits a plurality of serial data signals at regular intervals for each processing cycle within a first period longer than the CPU's response processing time obtained by multiplication, and the nonvolatile memory Generating a plurality of other serial data signals from the reproduction data reproduced and output by the CPU, and after the first period, the CPU response processing Provided is a data reproduction method in which the serial transmission card serially transmits the plurality of other serial data signals at regular intervals for each processing cycle within a second period longer than an effective time. .

1 is a configuration diagram of a data reproduction system including a data reproduction apparatus according to an embodiment. It is a functional block diagram of a serial transmission card. (A)-(c) is a timing chart which shows the timing which outputs the transmission completion interruption acknowledgment in a data reproducing | regenerating apparatus. It is a timing chart which shows the timing of the process in each part in a signal processing apparatus, and each part in a data reproduction apparatus. It is a flowchart for demonstrating the transmission completion interruption process by a device driver. It is a figure which shows an example of the memory map of an external storage device. It is a 1st flowchart for demonstrating the data reproduction process by CPU. It is the 2nd flowchart following FIG.

  Hereinafter, a data reproducing apparatus and a data reproducing method according to an embodiment will be described with reference to FIGS. 1 to 8. In the drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a configuration diagram of a data reproduction system including a data reproduction apparatus according to an embodiment. The data reproduction system 1 reads out a DSP card 2 (signal processing device) to be debugged, N data buses 3 connected to the DSP card 2, and serial data signals for N channels from a storage medium. And a data reproducing device PC4 (data reproducing device) for outputting the serial data signal to the data bus 3 of each channel.

  The data reproducing apparatus PC4 includes a personal computer main body 4a that holds recorded data recorded in advance in a real environment, and a high-speed serial communication card that is attached to the personal computer main body 4a and generates and outputs synchronous serial digital data for N channels. 15 (serial transmission card) and a CPU 19 in the personal computer main body 4a. The process executed by the high-speed serial communication card 15 is a process of generating an interrupt to the CPU 19 once after repeating a process of one basic period for a preset number of times. One basic period is a transmission period of each serial data signal. One basic period is a fixed value and is determined by the setting at the time of activation.

  In the present embodiment, the data reproducing apparatus PC4 multiplies the basic period by a preset number of transmissions to extend the time when the CPU 19 can respond to processing, and transmits each time within the time when the CPU processing response is possible. A serial data signal is set, and reproduction data for N channels is transmitted to the DSP card 2 on the data bus 3. Within the time when this CPU processing response is possible, the data reproducing apparatus PC4 reads the recorded data from the personal computer main body 4a, converts the format of the read recorded data into the reproduced data, and sets the reproduced data in the transmission buffer. Process.

  In the data reproduction method according to this embodiment, the CPU 19 in the data reproduction apparatus PC4 sets the number of transmissions of the serial data signal to the high-speed serial communication card 15, for example, 1000, and then starts transmission to the high-speed serial communication card 15. Is commanded. The high-speed serial communication card 15 repeats the processing of one basic cycle 1000 times. This is a method in which the high-speed serial communication card 15 causes the CPU 19 to generate an interrupt when the high-speed serial communication card 15 finishes executing 1000 processes.

  For example, by setting the basic period to 50 μsec and the CPU 19 causes the high-speed serial communication card 15 to execute the processing of 50 μsec 1000 times, and then causing the high-speed serial communication card 15 to output a completion interrupt to the CPU 19 only once. The data reproducing apparatus PC4 reduces the frequency of interrupts to the CPU 19 from a rate of once every 50 μs to a rate of once every 50 milliseconds. The high-speed serial communication card 15 thins out the number of interruptions. The interrupt generation interval to the CPU 19 is extended to a time order within a range that can be processed by the CPU 19 and the CPU peripheral circuit, thereby enabling high-speed data transfer and data reproduction using a personal computer.

  The DSP card 2 shown in FIG. 1 reads a signal processing calculation program from the flash ROM 5 and performs signal processing calculations such as digital filter processing and FFT processing. A metal cable or an optical cable is used for the data bus 3. Different substrates of the DSP card 2 and the data reproducing apparatus PC4 are connected by a serial communication path.

  The DSP card 2 includes K DSPs 8 each having an internal memory 6 and a DMA controller (DMAC) 7, a first data bus 9 connected to each DMA controller 7, and a bus protocol connected to the data bus 9. The conversion function unit 10, the external storage device 12 connected to the bus protocol conversion function unit 10 via the second data bus 11, and the bus protocol conversion function unit 10 connected to the bus protocol conversion function unit 10 via the third data bus 13. And a high-speed serial communication device 14 (serial transmission card).

  For example, each internal memory 6 of five DSPs 8 has a small storage area. The DMA controller 7 DMA transfers the data stored in the internal memory 6. The flash ROM 5 holds a signal processing program for each DSP 8. Each program is transferred to the internal memory 6 by each DMA controller 7 after the DSP card 2 is activated. After the activation, each DSP 8 performs arithmetic processing of the assigned DSP software in accordance with a program calculation instruction stored in the internal memory 6.

  The bus protocol conversion function unit 10 converts data between the data buses 9, 11, and 13 having different bus widths and data transfer units according to the protocol of these buses and then transfers the data. The external storage device 12 is a volatile storage device and uses a large-capacity memory such as a page memory. The high-speed serial communication device 14 receives a serial data signal having a high transfer rate.

  Thus, when debugging the DSP card 2, serial data signals for N channels are sent to the high-speed serial communication device 14 from the data reproduction device PC4 at basic cycle intervals and transferred to the DSP card 2. Any one of the DSPs 8 writes these serial data signals to the external storage device 12 via the bus protocol conversion function unit 10. The K DSPs 8 read data from the external storage device 12 and perform signal processing operations. For example, an output result or the like is monitored using a printf statement or the like.

  The personal computer main body 4a constituting the data reproducing apparatus PC4 has a slot part and a mother board. The high-speed serial communication card 15 is inserted into this slot portion.

  The personal computer main body 4a includes, for example, a hard disk drive 16 (nonvolatile storage unit) in which a radar device at a remote location holds a radar reception wave as recording data, and a hard disk drive that controls reading and writing of data accessed to the hard disk drive 16 A control card 18, a CPU 19 as a host processor, a bus protocol conversion function unit 22 that interfaces between the CPU 19 and the high-speed serial communication card 15, and a volatile external storage device 23 (volatile storage unit) are provided. .

  The hard disk drive 16 is a non-volatile external storage device that stores recording data that is a source of reproduction data transmitted to the DSP card 2. The hard disk drive 16 has an OS such as Windows (registered trademark) or Linux (registered trademark), an application (application program) for operating on the OS, setting the number of transmissions of serial data signals, and instructing transmission, and an external storage A device driver for transferring the recording data read to the device 23 to the high-speed serial communication card 15 is held. The device driver operates in a state incorporated in the memory space of the OS kernel, and accepts a processing request from an application via the OS kernel. In the hard disk drive 16, these device drivers and application programs are loaded from the hard disk drive 16 to the external storage device 23 and executed by the CPU 19 at the time of booting. The functions of the hard disk drive 16 are realized by a RAID hard disk drive or a silicon disk.

  When the hard disk drive control card 18 receives a command from the CPU 19, it reads the recorded data from the hard disk drive 16 and writes it to the external storage device 23. The bus protocol conversion function unit 22 includes a data bus 20 (input / output bus) on the high-speed serial communication card 15 side, a data bus 21a on the CPU 19 side, a data bus 17 on the hard disk drive control card 18 side, and a volatile external storage device 23. The data bus 21b on the side is bridged. The data bus 20 is an input / output bus compliant with PCI (Peripheral Component InterConnect) Express, and the data buses 17, 21a, and 21b are all internal buses. The bus protocol conversion function unit 22 converts data between four data buses 20, 17, 21a, and 21b having different bus widths and data transfer units according to the protocol of these buses and then transfers the data. The external storage device 23 is a DRAM and has a large-capacity storage area such as a page memory.

  The structure of the high-speed serial communication card 15 is an FPGA (Field Programmable Gate Array) having a buffer control function, a DMA (Direct Memory Access) transfer function, and the like, and this FPGA is wired on the substrate surface and an edge electrode is formed on one side end thereof. And a connector provided on an end of the substrate surface opposite to the direction in which the substrate is inserted and connected to a metal cable or the like.

  A card-type PCI expansion adapter is mounted on the motherboard of the personal computer main body 4a in a standing state on the motherboard via a motherboard-side connector. A plurality of adapter-side connectors with conductive contacts arranged at equal intervals in the vertical direction are attached to the surface of the PCI expansion adapter, and the high-speed serial communication card 15 is fitted to any one of the adapter-side connectors. Thus, the edge electrode of the high-speed serial communication card 15 and the conductive contact are electrically connected. The high-speed serial communication card 15 is manufactured in-house by the present inventor and has substantially the same size as a PCI card, a LAN card, a USB card, a RAID card, a SCSI card, or a graphics card.

  The high-speed serial communication card 15 reads and transfers each serial data signal every basic period. Each serial data signal has the same amount of data.

  FIG. 2 is a functional block diagram of the high-speed serial communication card 15. The above described symbols represent the same elements. The high-speed serial communication card 15 DMAs data on the bus interface (PCI express interface) 24 for interface processing access requests from the CPU 19 to each part in the high-speed serial communication card 15 and data on the data bus 20 in the data reproducing apparatus PC4. And a DMA controller (DMAC) 25 for transfer. Furthermore, the high-speed serial communication card 15 performs parallel-serial conversion on N transmission buffers 27 each storing reproduction data for N channels, and parallel data format reproduction data stored in these transmission buffers 27 to obtain a serial data signal. And N serial data transmission units 26 that output to the DSP card 2.

  The bus interface 24 interfaces a bus protocol. The DMA controller 25 reads the reproduction data stored in the external storage device 23 in the format-converted state from the data bus 20, and writes the read reproduction data to each transmission buffer 27 in a parallel data format. Each transmission buffer 27 is a DRAM and has a large-capacity storage area such as a page memory. Each of the transmission buffers 27 for channel numbers 1 to N has a double buffer configuration having a first bank and a second bank. Each serial data transmission unit 26 reads the reproduction data stored in each transmission buffer 27 for each basic period. When each serial data transmission unit 26 receives a control signal from a control function unit 29 described later, each serial data transmission unit 26 converts parallel data into a serial data signal and outputs N serial data signals to the data bus 3.

  Furthermore, the high-speed serial communication card 15 includes an I / O register 28 for passing control information between the personal computer main body 4a and the data reproducing apparatus PC4, and a control function unit 29 for controlling the N serial data transmission units 26. Is provided. The application on the personal computer side controls the high-speed serial communication card 15 via the device driver based on the control parameter such as the number of transmissions 1000 times input by the user, and the I / O register 28 has a status (device information). And a plurality of types of control parameters. The value in the I / O register 28 is read and written by both the device driver and the control function unit 29. When the device driver reads the status value written by the control function unit 29, the application determines whether transmission is in progress. When the control function unit 29 reads the values of various control parameters written by the device driver, the control function unit 29 controls the transmission operation and transmission stop of each serial data transmission unit 26. The application on the personal computer side controls each serial data transmission unit 26 which is hardware via the I / O register 28 and the device driver.

  In the present embodiment, after the CPU 19 notifies the high-speed serial communication card 15 of a transmission command, when each serial data transmission unit 26 finishes transmitting each serial data signal 1000 times, the high-speed serial communication card 15 detects the CPU 19. A transmission completion interrupt is output once.

  FIGS. 3A to 3C are timing charts for explaining the timing of outputting a transmission completion interrupt acknowledgment in the data reproducing apparatus PC4. When the control function unit 29 rewrites the status of the I / O register 28 and the device driver reads this status, a transmission completion interrupt acknowledgment is performed. The device driver executed by the CPU 19 outputs a transmission completion notification to the application executed by the CPU 19. One transmission completion is notified to the application from the high-speed serial communication card 15 via the device driver for 1000 times of reproduction data transmission.

  The status stored in the I / O register 28 is information indicating whether reproduction data is being transmitted in the transfer section from the high-speed serial communication card 15 to the DSP card 2. The control parameters stored in the I / O register 28 are the number of transmissions of 1000 times, the start address of the reproduction data written in each transmission buffer 27, the data size of the reproduction data, and the transmission operation for N channels are valid. The number of channels to be transmitted, for example, communication conditions such as a communication rate, and transmission cycle information for changing the basic cycle. The control function unit 29 has a transmission management down counter.

  Specifically, the control parameters are written by the device driver executed by the CPU 19. When the number of transmissions is set in the I / O register 28, the control function unit 29 sets the value of the number of transmissions to the counter value of the down counter. The control function unit 29 decrements the down counter every time reproduction data for each basic period is transmitted. The control function unit 29 notifies the bus interface 24 when the counter value becomes zero. The bus interface 24 outputs an interrupt signal to the CPU 19 only once. The address is updated by the control function unit 29. The control function unit 29 passes this address to each serial data transmission unit 26. Each serial data transmitter 26 outputs a serial data signal from the address.

  A status value 0 indicates an initial state in which transmission is not performed. When the CPU 19 writes 1 to the I / O register 28, the control function unit 29 is called from a circuit attached to the I / O register 28. The control function unit 29 instructs each serial data transmission unit 26 to perform transmission. The serial data transmission unit 26 starts transmitting data from each transmission buffer 27.

  When the control function unit 29 finishes transferring the reproduction data 1000 times, the control function unit 29 rewrites the status value from 0 to 1. The device driver reads the status value. When the status value is 1, the device driver detects an interrupt. That is, the device driver has a function of receiving an interrupt on behalf of the application. While the device driver does not detect an interrupt, the device driver is in an infinite loop. When an interrupt is detected, an acknowledgment is sent to the control function unit 29 and a value indicating interrupt detection is returned to the application.

  In other words, the device driver mediates between the application and each serial data transmission unit 26. The application instructs the serial data transmission unit 26, which is hardware, to start transmission by the device driver. This is because it takes time for the CPU 19 to copy the recording data from the hard disk drive 16 to each serial data transmission unit 26, and processing cannot be performed in a short time of 50 μs in the first place. By interposing the device driver, even when the DMA copy is being executed by the DMA controller 25, the CPU 19 can execute other generated work. While the CPU 19 is performing other work, the CPU 19 can pick up an interrupt indicating that 1000 transmissions have been completed.

  Control by the control function unit 29 instructs each serial data transmission unit 26 to send data to the DSP card 2, instructs each serial buffer 27 to read the storage area of each transmission buffer 27, and receives a command from the CPU 19. The DMA controller 25 is activated. When the CPU 19 writes necessary control information into the I / O register 28, a circuit associated with the I / O register 28 notifies the control function unit 29 that the writing has been performed.

(Function)
The operation of the data reproduction apparatus PC4 when the data reproduction apparatus PC4 having such a configuration transmits serial digital data to the DSP card 2 will be described in detail.

(1) Overall Processing Timing FIG. 4 is a timing chart showing processing timings in each part in the DSP card 2 and each part in the data reproducing apparatus PC4. 4 (a) to 4 (d), a DSP card from when the DSP card 2 receives each serial data signal from the data reproducing device PC4 until each DSP 8 of the DSP card 2 starts a signal processing operation is shown. Two side timing is shown. In FIG. 4 (e) to FIG. 4 (i), three types of processing timings in the data reproducing apparatus PC4 are shown in a superimposed manner. The three types of processing timings are a transmission completion interrupt acknowledgment response timing, a timing at which reproduction data is transferred from the external storage device 23 to each transmission buffer 27, and a recording data read from the hard disk drive 16 to the external storage device 23. Refers to the timing at which data is written.

  As shown in FIGS. 4 (c) and 4 (d), when the DSP card 2 receives the serial data signals of channels 1 to N, as shown in FIGS. 4 (a) and 4 (b), After the K DSPs 8 have passed the basic period (1), signal processing operations are performed on the serially received data of each channel.

  Within the time shown in FIG. 4 (i), the high-speed serial communication card 15 reads the recording data of the hard disk drive 16, converts the format, adds header information to the recording data, and converts the playback data after the format conversion to the external storage device 23. Write to. The high-speed serial communication card 15 assigns a value of a transmission condition indicating, for example, from which address of each transmission buffer 27 the reproduction data is transmitted.

  The reproduction data generated within the time shown in FIG. 4 (i) is transferred by the high-speed serial communication card 15 to one bank of the double buffer of each transmission buffer 27 within the time shown in FIG. 4 (h). In the example of FIG. 4 (h), two front and rear reproduction data D1 and D2 are shown. The reproduction data D2 is data for N channels just generated in FIG. 4 (i) and transferred to one bank. Prior to this reproduction data D2, N channels of reproduction data D1 are stored in the other bank. When the transmission data interruption acknowledgment is received at time t1 in FIG. 4 (g), the high-speed serial communication card 15 sends the reproduction data D1 to the reproduction data D1 at the time shown in FIGS. 4 (e) and 4 (f). At t2, the data is read and serial transmission to the DSP card 2 is started. Transmission of serial data signals of channels 2 to N-1 is the same as that of channels 1 and N in FIG.

  Each serial data transmission unit 26 of channels 1 to N executes data transmission based on the transmission cycle, data size, and number of transmissions designated by the CPU 19. The DSP card 2 performs signal processing in the next basic period after reception as shown in (3) and (4) of FIG.

  In addition, each process in the DSP card 2, the process of the serial data transmission unit 26 in the data reproducing apparatus PC4, and the process in which the device driver detects a transmission interrupt acknowledgment is all performed in synchronization with the basic period. The reproduction data transfer process of the data reproduction apparatus PC4 and the data reproduction / format conversion process of the hard disk drive 16 are asynchronous with this basic cycle.

  Hereinafter, details of the data reproducing apparatus PC4 will be described in (2), (3), (4), and (5).

(2) Operation of High-Speed Serial Communication Card 15 In FIG. 2, the solid line indicates the data flow, and the dotted line indicates the control flow. Wide arrows indicate the interface between the devices. As shown in (1) and (2) of FIG. 1, the high-speed serial communication card 15 is provided independently for each channel after the format of the data read from the hard disk drive 16 is converted according to the request on the receiving side. Temporarily stored in the transmission buffer 27.

  The transmission buffer 27 for channel number 1 will be described. While the serial data transmission unit 26 is outputting the serial data signal for channel number 1 stored in one bank to the data bus 3, the DMA controller 25 Data to be transmitted next time from the external storage device 3 is written in the other bank. The serial data transmission unit 26 transmits a serial data signal for channel number 1 (a serial data signal having a data size of a set number of bytes) once within one basic period, and repeats this 1000 times. While the serial data transmission unit 26 repeats data transmission from one bank 1000 times, the DMA controller 25 stores data to be transmitted next time in the other bank. By the time the serial data transmission unit 26 completes 1000 data transmissions, serial data signals for the next transmission are arranged in the other bank.

  When the serial data transmission unit 26 completes transmission of the serial data signal from one bank, the serial data transmission unit 26 starts transmission of the serial data signal from the other bank without any delay. Subsequently, while the serial data transmission unit 26 repeats data transmission from the other bank 1000 times, the DMA controller 25 accumulates data to be transmitted next time in one bank, and 1000 data transmission from the other bank. By the time, the DMA controller 25 aligns serial data signals for next transmission in one bank. With the double buffer configuration, there is no time lag between the completion of 1000 transmission units currently being executed and the start of 1000 transmission units to be executed next, and data can be transferred in real time. The transmission buffers 27 for channel numbers 2 to N each have two banks. Each of the two banks is switched in the same manner as the transmission buffer 27 for channel number 1.

  As described above, after the CPU 19 specifies the transmission cycle, the data size, and the number of transmissions, the high-speed serial communication card 15 starts transmission processing, and the high-speed serial communication card 15 performs all transmissions according to the transmission control parameters. , Send a transmission completion interrupt once. The high-speed serial communication card 15 functions as a component of the host CPU 19 via PCI express or the like.

(3) Transmission Completion Interrupt Processing Processing by the device driver executed by the CPU 19 and processing by the application will be described in detail with reference to FIGS. FIG. 5 is a flowchart for explaining a transmission completion interrupt process by the device driver. FIG. 6 is a diagram showing an example of a memory map of the external storage device 23, and shows a memory configuration on the CPU 19 side. The above described symbols represent the same elements.

  As shown in FIG. 6, processing upstream of the processing for transferring data to the external storage device 23 is performed by a device driver and an application that is a playback program. The processing downstream of the processing for transmitting data from the external storage device 23 is performed by hardware.

  In FIG. 5, after the data reproduction system 1 is turned on, in step A1, the CPU 19 loads a device driver program from the hard disk drive 16 to the RAM when the OS is activated, and incorporates and executes it as a device driver. The transmission flag (flag information) is set to 0. In steps A2 and A3, the device driver waits until a transmission completion interrupt occurs (NO route in step A3). When the transmission completion interrupt occurs, the device driver performs an affirmative response to the transmission completion interrupt in step A4 through the YES route in step A3. In steps A5 and A6, the device driver sets the transmission flag to 1 and ends the process.

(4) In the data reproduction processing, the CPU 19 performs initial setting and communication setting processing for each serial data transmission unit 26 of channels 1 to N of the high-speed serial communication card 15 prior to data reproduction.

  After the CPU 19 incorporates the device driver when the OS is started, the data reproduction processing by the CPU 19 reads the transmission data file from the hard disk drive 16 as shown in FIGS. 1 (1), (2), and FIG. Format conversion is performed in accordance with the high-speed serial communication card 14 on the receiving side such as creation. The application converts the recording data format to the reproduction data format.

  After the format conversion, the data is transferred to each transmission buffer 27 in the high-speed serial communication card 15. The data reproduction process is performed by starting the transmission process after the CPU 19 designates the transmission start address, the transmission cycle, the data size, and the number of transmissions to the high-speed serial communication card 15. The CPU 19 waits until a transmission completion interrupt is generated from the channels corresponding to the number of channels that are validated for transmission among all the channels of the high-speed serial communication card 15.

  Next, in the transmission completion interrupt process, after the CPU 19 receives the transmission completion interrupt, the CPU 19 clears the interrupt output from the high-speed serial communication card 15 once. Further, the CPU 19 updates flag information shared between the device driver and the data reproduction process.

(5) Data Reproduction Process The data reproduction procedure and transmission completion interrupt process by the CPU 19 will be described with reference to FIGS. FIG. 7 is a first flowchart for explaining the data reproduction processing by the CPU 19. FIG. 8 is a second flowchart following FIG.

  When the reproduction process is started, in step B1, the CPU 19 loads an application for data reproduction from the hard disk drive 16 and executes the application.

  In step B2, the CPU 19 sets the transmission flag to 0.

  In step B <b> 3, the CPU 19 sets an effective channel and communication conditions in the I / O register 28. With this setting, the high-speed serial communication card 15 is enabled so that the high-speed serial communication card 15 performs data reproduction processing for one channel, several channels, or all channels. A serial communication connection from the data reproducing apparatus PC4 to the DSP card 2 is established and communication is started.

  Subsequently, in step B4, the CPU 19 sets the number of transmission repetitions. In step B5, the CPU 19 sets the transmission flag to 0.

  In subsequent step B6 of FIG. 8, the CPU 19 sets the transmission start address, the transmission cycle, the data size, and the number of transmissions in the I / O register 28. In this setting, the CPU 19 creates a transmission start address or the like as an internal variable in the external storage device 23 in advance, and writes this transmission start address or the like in the I / O register 28.

  In step B7, the CPU 19 notifies the transmission start to the high-speed serial communication card 15, and the high-speed serial communication card 15 starts transmission.

In step B8, the CPU 19 reads the recording data to be transmitted next time from the hard disk drive 16, and converts the format of the recording data to the format of the reproduction data on the external storage device 23.

  In step B9, the CPU 19 reads the reproduction data from the external storage device 23, and DMA-transfers this reproduction data to the next transmission buffer among the double buffers of any one of the transmission buffers 27 as the next transmission data.

  In step B10, the CPU 19 determines whether or not the transmission flag is 1. If the transmission flag is not 1, the CPU 19 waits through the NO route. If the CPU 19 detects that the transmission flag is 1, the YES route is taken.

  In step B11, the CPU 19 increments the repetition variable i. Returning to step B4 again, the CPU 19 executes a loop of processing from step B4 to step B11. When the iteration variable i reaches the specified number of times, the process loops out of step B11 at that time, and in step B12, the CPU 19 performs a process of ending the communication between the CPU 19 and the high-speed serial communication card 15. The CPU 19 performs communication end processing such as disabling the state of the high-speed serial communication card 15. The high-speed serial communication card 15 finishes transmitting the serial data signal.

  Reading recorded data from the hard disk drive 16 and writing it to the external storage device 23, performing format conversion on the external storage device 23, and writing the format-converted reproduction data to the transmission buffer 27 of the high-speed serial communication card 15. These processes are controlled by the personal computer OS. The speed of each processing such as reading, writing, and conversion may be faster than 50 milliseconds or slower than 50 milliseconds depending on the processing load of the OS. That is, there is a fluctuation in the processing speed while the control is transferred to the personal computer OS. In the present embodiment, by selecting and using the personal computer main body 4a whose processing speed has been evaluated in advance, even if the processing speed of the process controlled by the OS of the selected personal computer main body 4a fluctuates, the read / write of recorded data is performed. The time required for each processing such as conversion is kept within 50 milliseconds. Each process under the control of the personal computer OS is executed while the high-speed serial communication card 15 is transmitting the serial data signal from the transmission buffer 27. It does not affect the timing.

  The buffer size of the N transmission buffers 27 and the buffer size of the external storage device 23 are such that reading and transmitting data from these transmission buffer 27 and external storage device 23 is within the range of 50 milliseconds. Can be decided. Processing to transfer a large amount of serial data signals at regular intervals within a certain period is established so that the maximum value of the processing speed fluctuation is accommodated within the time from when the CPU 19 is started until the transmission completion interrupt response is issued. I am letting. As described above, the reproduction data transfer of the data reproduction device PC4 and the reproduction / format conversion processing of the hard disk drive 16 satisfy the allowable range of the transmission buffer in the high-speed serial communication card 15 and the buffer provided in the external storage device 23. As a condition, the basic cycle of the DSP card 2 side and the serial data transmission unit 26 is asynchronous processing.

  In the radar apparatus, the radar antenna rotates 360 degrees in the azimuth direction. The radar antenna makes one turn in 6 to 12 seconds. The number of data obtained by dividing 6 to 12 seconds by 50 μs is enormous. In debugging, the data reproducing apparatus PC4 sends a huge amount of serial data signals to the DSP card 2. Using the same data by the DSP card 2 does not verify the process. The hard disk drive 16 holds recording data for a plurality of rounds that differ for each round. An environment in which recorded data can be read from the hard disk drive 16 every time is necessary. The data reproducing apparatus PC4 according to the present embodiment can perform a series of processes such as reading, writing, and conversion within a desired 50 ms while reading the data from the hard disk drive 16 with the help of a general-purpose OS. Became.

  According to the data reproducing device and the data reproducing method according to the embodiment, a data reproducing function with low cost and high speed / low fluctuation can be realized for a data reproducing device using serial communication. In addition, since data is reproduced by a combination of a general-purpose PC and a general-purpose OS, the cost can be reduced. Using an inexpensive general-purpose personal computer, the recording data can be transferred at a high transfer rate and at a constant interval, and the recording data can be supplied to the DSP card 2 at the same timing as the processing of the DSP card 2 as this device. become. A function for repeatedly transmitting data at a fixed transmission time interval can be constructed at a low cost by using software for reproducing data and using hardware (high-speed serial communication card) and recorded data read from the external storage device 23. It becomes like this.

  In order to confirm whether or not each equipment constituting the radar apparatus is operating at every basic period, it is necessary to emit radio waves. It is difficult to reproduce the actual environment that radiated the test radio wave in terms of laws and procedures. Therefore, using recorded data actually measured by the radar apparatus at a remote location can create a situation in a real environment that satisfies a desired collection condition, and can be debugged. High-speed data transfer of signal processing operations can be reproduced, and operation check by debugging can be performed correctly. The radar apparatus can be debugged using actual measurement data under the condition that the radio wave is reflected by the radio wave reflector generated in the actual environment.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Data reproduction system, 2 ... DSP card (signal processing device), 3 ... Data bus (transmission path), 4 ... Data reproduction device PC (data reproduction device), 4a ... PC main body, 5 ... Flash ROM, 6 ... Inside Memory, 7 ... DMA controller, 8 ... DSP, 9, 11, 13 ... Data bus, 10 ... Bus protocol conversion function unit, 12 ... External storage device, 14 ... High-speed serial communication device (serial transmission card), 15 ... High-speed serial Communication card (serial transmission card), 16... Hard disk drive (nonvolatile storage unit), 17, 21a, 21b... Data bus (internal bus), 18... Hard disk drive control card, 19. Bus), 22 ... Bus protocol conversion function unit, 23 ... External storage device (volatile storage unit), 24 ... Bus interface Face, 25 ... DMA controller, 26 ... serial data transmission unit, 27 ... transmission buffer, 28 ... I / O register, 29 ... control function unit.

Claims (4)

A non-volatile storage unit that holds recording data for verifying the operation of the signal processing device that repeatedly executes the processing on the data signal for each basic period of the processing;
A CPU that accesses this nonvolatile storage unit via an internal bus and uses a time longer than the basic cycle as a response processable time, and a volatility in which the CPU reproduces the recorded data and stores the reproduced data. A storage unit, and a personal computer body having an input / output bus connected to the CPU and the volatile storage unit via a bus protocol conversion unit;
A plurality of serial data signals are generated from the reproduction data transferred from the volatile storage unit via the input / output bus of the personal computer body, and each serial data signal is transmitted through the transmission path for each basic period. A serial transmission card for transmitting to the processing device,
This serial transmission card generates each serial data signal within a period longer than the time that the CPU can process the response obtained by multiplying the basic cycle by a preset number of transmissions, and after the elapse of this period, A data reproducing apparatus for serially transmitting each serial data signal at a fixed interval for each processing cycle within a next period longer than the time. The serial transmission card is
A plurality of buffers each storing the reproduction data for each of a plurality of channels;
A DMA controller that DMA-transfers the reproduction data to the buffers from the volatile storage unit via the input / output bus;
A plurality of serial data transmission units for transmitting each serial data signal from each buffer DMA-transferred by the DMA controller to the signal processing device in synchronization with the basic period;
A counter for measuring the number of transmission completion interrupts output when these serial data transmission units transmit each serial data signal;
The data reproducing apparatus according to claim 1, further comprising: a control function unit that transmits the transmission completion interrupt to the CPU when a measured value of the counter reaches the number of transmissions. Attach a serial transmission card connected via a transmission line to a signal processing device that repeatedly executes processing on the data signal multiple times per basic cycle of this processing, and retains recording data for operation verification of this signal processing device The CPU of the personal computer connected to the non-volatile storage unit instructs the serial transmission card to start transmission,
The serial transmission card sets a plurality of serial data signals at each processing cycle within a first period longer than the time that the CPU can perform response processing, which is obtained by multiplying the basic cycle by a preset number of transmissions. Serially transmit at intervals, and generate another serial data signal from the reproduction data reproduced and output by the CPU to the nonvolatile storage unit,
After the elapse of the first period, the serial transmission card serializes the plurality of other serial data signals at regular intervals for each processing cycle within a second period longer than the time during which the CPU can process the response. A data reproduction method comprising transmitting the data. After the elapse of the first period, the serial transmission card measures the number of transmissions of each serial data signal,
4. The data reproduction method according to claim 3, wherein when the measured value reaches the number of transmissions, the serial transmission card transmits the transmission completion interrupt for the number of transmissions to the CPU.

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