JP2011254544A - Physical amount detection device and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that 1/f noise and burst noise due to a finite ON resistor of a selection transistor are not considered and a design is not cared since the selection transistor of a pixel is considered to be just a switch.SOLUTION: A selection transistor 25 is set to be a depression-type transistor. When the selection transistor 25 is to be turned off, a gate voltage is set to an off-side compared to a voltage of a well where the selection transistor 25 is formed, to a negative voltage. Thus, 1/f noise and burst noise due to a finite ON resistor of the selection transistor 25 are reduced. The selection transistor 25 is arranged in series to a signal line 122-side against an amplification transistor 24 amplifying a signal detected by a detection portion detecting a physical amount given from outside. Consequently, a potential difference between a gate and a drain is suppressed to be small even if the negative voltage is applied to the gate of the selection transistor 25.

Description

  The present invention relates to a physical quantity detection device that detects a physical quantity given from the outside and an imaging apparatus that uses a solid-state imaging device that detects light given from the outside as a physical quantity.

  As a physical quantity detection device that detects a physical quantity given from the outside, for example, a solid-state imaging device that detects the light intensity of incident light that has passed through the subject as a physical quantity, or according to the unevenness of a fingerprint between the detection electrode and the finger surface A fingerprint detection device (capacitance detection device) that detects a formed capacitance as a physical quantity is known.

  FIG. 7 shows a pixel circuit in the solid-state imaging device. As illustrated in FIG. 7, the pixel 100 includes four transistors, that is, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105 in addition to a photodiode 101 that is a photoelectric conversion element. Many are connected to the signal line 110. Here, N-channel MOS transistors are used as the four transistors 102 to 105.

  Here, the selection transistor 105 is considered. The selection transistor 105 functions as a switch element that selects / deselects the pixel 100. Therefore, it is ideal that the select transistor 105 has a resistance of 0 when turned on regardless of the source / drain voltage, and an infinite resistance when turned off regardless of the source / drain voltage.

  However, in practice, the source / drain voltage that can turn on the selection transistor 105 is limited, and the on-resistance is also finite. In addition to this point, since the selection transistor 105 is connected in series to the amplification transistor 104, the pixel 100 configured as described above has the following two problems.

(1) Since the voltage is lost due to the threshold value drop of the selection transistor 105, it is difficult to lower the power supply voltage Vdd.
(2) Noise (thermal noise, 1 / f noise, burst noise, etc.) caused by the selection transistor 105 gets on the vertical signal line 110.

  Here, 1 / f noise and burst noise become a problem in particularly fine pixels. As shown in FIG. 8, burst noise is noise in which a small amount of pixels arranged in a large number have a large amount of noise, or change randomly between specific binary or ternary values for each pixel. Along with 1 / f noise, it is considered highly likely to originate from the interaction between the gate oxide film of the transistor and the channel.

  The 1 / f noise is a line-dam noise that can be seen in a considerable proportion of pixels over the entire screen. Burst noise is noise in which a very small number of pixels appear to blink. As described above, since the selection transistor 105 is not an ideal switch in reality and its on-resistance is finite, noise due to the selection transistor 105 appears in the output in addition to the noise of the amplification transistor 104.

  Conventionally, as a countermeasure for the above problem (1), a booster circuit for boosting the power supply voltage Vdd is provided in the same chip as the pixel 100, and a voltage boosted by this booster circuit, that is, a voltage higher than the power supply voltage Vdd is supplied to the selection transistor 105. The gate voltage is given (for example, see Patent Document 1).

Japanese Patent No. 3369911

  However, although the above-described conventional technique is effective as a solution to the problem (1), it is not very effective for the problem (2), that is, noise caused by the selection transistor 105. The reason is that by raising the gate voltage of the select transistor 105, the ratio of the current component that flows not at the bulk side but at the oxide film interface increases, so that the noise rather increases under the condition of a constant pixel current. That is, the noise due to the selection transistor 105 increases.

  In addition, mounting a booster circuit on the same chip as the pixel 100 leads to disadvantages such as an increase in cost, generation of defects, or an increase in the size of a module due to the need for an external capacitor.

  In addition, among the four transistors 102 to 105 of the pixel 100, the selection transistor 105 is considered to be only a switch, and conventionally, the 1 / f attributed to the finite on-resistance of the selection transistor 105. No consideration was given to noise and burst noise, and no design care was taken.

  Here, the problem has been described by taking a solid-state imaging device as an example of the physical quantity detection device, but the same can be said for other physical quantity detection devices having a selection transistor for selecting a pixel.

  Therefore, an object of the present invention is to provide a physical quantity detection device and an imaging device capable of reducing 1 / f noise, burst noise, and the like due to a finite on-resistance of a selection transistor in a pixel.

In order to achieve the above object, in the present invention, a detection unit that detects a physical quantity given from the outside, an amplification transistor that amplifies a signal detected by the detection unit, and a signal line that selectively amplifies the signal amplified by the amplification transistor The pixels including the selection transistor that outputs to the two-dimensionally arranged in a matrix form, the selection transistor is a depletion type transistor, and is arranged in series on the signal line side with respect to the amplification transistor , and the selection transistor A configuration is employed in which the gate voltage when the transistor is turned off is set to a voltage on the off side of the voltage of the well in which the selection transistor is formed.

In the physical quantity detection device having the above-described configuration, since the selection transistor is a depletion type transistor, the on-resistance is reduced without setting the gate voltage of the selection transistor to a more on-side voltage. Further, in the selection transistor, the ratio of the current component flowing on the bulk side instead of the oxide film interface is increased.
Further, by arranging the selection transistor in series on the signal line side with respect to the amplification transistor, even if a negative voltage is applied to the gate of the selection transistor, the potential difference between the gate and the drain can be kept small.

According to the present invention, since the selection transistor is a depletion type transistor, the on-resistance of the selection transistor is lowered, and the ratio of the current component flowing in the bulk side in the selection transistor is increased, so that the selection transistor has a finite on-state. It is possible to reduce 1 / f noise and burst noise caused by the resistance. Moreover, this can be compatible with lowering of the power supply voltage.
Furthermore, by arranging the selection transistor in series on the signal line side with respect to the amplification transistor, even if a negative voltage is applied to the gate of the selection transistor, the potential difference between the gate and the drain can be kept small, so the reliability of the selection transistor Can be secured.

1 is a system configuration diagram illustrating an outline of a configuration of a solid-state imaging device according to an embodiment of the present invention. 3 is a circuit diagram illustrating a circuit configuration of a pixel according to Circuit Example 1. FIG. 6 is a circuit diagram illustrating a circuit configuration of a pixel according to a circuit example 2. FIG. It is a block diagram which shows an example of a structure of a vertical drive circuit. It is a timing chart with which it uses for description of operation | movement at the time of applying the method which concerns on 2nd Example. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is a circuit diagram which shows the circuit structure of the pixel of 4 transistors. It is explanatory drawing about burst noise.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Here, as a physical quantity detection device that detects a physical quantity given from the outside, for example, a solid-state imaging device that detects the light intensity of incident light that has passed through a subject will be described as an example.

  FIG. 1 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device according to an embodiment of the present invention. In the present embodiment, a CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described as an example of the solid-state imaging device.

  As shown in FIG. 1, a solid-state imaging device 10 according to this embodiment includes a pixel array unit 12, a vertical drive circuit 13, a column circuit group 14, a horizontal drive circuit 15, and a horizontal signal line on a semiconductor substrate (chip) 11. 16, a system configuration in which an output circuit 17, a control circuit 18, a negative voltage generation circuit 19, and the like are mounted.

  The pixel array unit 12 has a configuration in which a large number of pixels 20 including a photoelectric conversion element that photoelectrically converts incident light into a charge amount corresponding to the light intensity are two-dimensionally arranged in a matrix (matrix). A specific circuit configuration of the pixel 20 will be described later. In the pixel array unit 12, pixel drive wirings 121 are wired for each pixel row and vertical signal lines 122 are wired for each pixel column in a matrix-like pixel arrangement.

  The vertical drive circuit 13 sequentially selects and scans each pixel 20 in the pixel array unit 12 in units of rows, and supplies a necessary drive pulse (control pulse) to each pixel in the selected row through the pixel drive wiring 121. Here, although not shown, the vertical drive circuit 13 sequentially selects the pixels 20 in units of rows and performs a readout operation for performing a readout operation of reading out the signal of each pixel 20 in the selected row, and the readout scanning. A shutter scanning system for performing a shutter operation that discards (resets) charges accumulated so far in the photoelectric conversion elements of the pixels 20 in the same row a time corresponding to the shutter speed before the readout scanning by the system. It is the composition which has.

  The signal charge accumulation in the pixel 20 is from the timing when the unnecessary charge of the photoelectric conversion element is reset by shutter scanning by the shutter scanning system to the timing when the signal of the pixel 20 is read by readout scanning by the readout scanning system. Time (exposure time). That is, the electronic shutter operation is an operation that resets signal charges accumulated in the photoelectric conversion elements and newly starts accumulation of signal charges.

  A signal output from each pixel 20 in the selected row is supplied to the column circuit group 14 through each vertical signal line 122. In the column circuit group 14, each column circuit is arranged for each pixel column of the pixel array unit 12, that is, with a one-to-one correspondence with the pixel column, and a signal output from each pixel 20 for one row is output. A signal processing such as CDS (Correlated Double Sampling) or signal amplification for removing fixed pattern noise peculiar to the pixel is performed on the signal received for each pixel column. It is also possible to adopt a configuration in which each column circuit of the column circuit group 14 has an A / D (analog / digital) conversion function.

  The horizontal drive circuit 15 includes a horizontal scanning circuit 151 and a horizontal selection switch group 152. The horizontal scanning circuit 151 is configured by a shift register or the like, and sequentially selects and scans each switch of the horizontal selection switch group 152, whereby a signal for one row after signal processing in each column circuit of the column circuit group 14 is a horizontal signal. The lines 16 are output in order.

  The output circuit 17 performs various signal processing on signals sequentially supplied from each column circuit of the column circuit group 14 through the horizontal selection switch group 152 and the horizontal signal line 16 and outputs the processed signal as an output signal OUT. In the output circuit 17, for example, only buffering processing may be performed, or black level adjustment, correction of variation for each column, signal amplification, color-related processing, and the like may be performed before the buffering processing.

  The control circuit 18 receives data for instructing the operation mode of the solid-state imaging device 10 from the outside of the substrate through an interface (not shown), outputs data including information on the solid-state imaging device 10 to the outside, and Based on the synchronization signal Vsync, the horizontal synchronization signal Hsync, and the master clock MCK, a clock signal, a control signal, and the like serving as a reference for the operation of the vertical drive circuit 13, the column circuit group 14, and the horizontal drive circuit 15 are generated. Give against.

  The negative voltage generation circuit 19 includes a charge pump circuit or the like, generates a negative voltage based on the power supply voltage Vdd, and supplies the generated negative voltage to the vertical drive circuit 13. In the CMOS image sensor, for example, for the purpose of reducing dark current, the gate voltage when the transfer transistor in the pixel 20 is turned off is set to a voltage on the off side of the voltage of the well in which the transfer transistor is formed. In order to obtain a negative voltage, a negative voltage generation circuit is provided (see, for example, JP-A-2002-217397). This negative voltage generation circuit can be used as the negative voltage generation circuit 19.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a circuit configuration of the pixel 20A according to the circuit example 1. As illustrated in FIG. As shown in FIG. 2, the pixel 20 </ b> A according to the circuit example 1 includes four transistors of a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21 that is a photoelectric conversion element. It has a circuit configuration. Here, as the four transistors 22 to 25, for example, N-channel MOS transistors are used.

  For this pixel 20A, a transfer wiring 121A, a reset wiring 121B, and a selection wiring 121C are wired in common to the pixels in the same row as the pixel driving wiring 121.

  In FIG. 2, a photodiode 21 photoelectrically converts received light into photocharges (here, electrons) having a charge amount corresponding to the light intensity. The cathode of the photodiode 21 is electrically connected to the gate of the amplification transistor 24 through the transfer transistor 22. A node electrically connected to the gate of the amplification transistor 24 is referred to as an FD (floating diffusion) portion 26. The FD unit 26 has a function of holding the signal charge transferred from the photodiode 21 and converting the signal charge into a voltage.

  The transfer transistor 22 is connected between the cathode of the photodiode 21 and the FD unit 26, and is turned on when a transfer pulse TRF is applied to the gate via the transfer wiring 121A. The photocharge stored in the FD unit 26 is transferred to the FD unit 26.

  The reset transistor 23 is turned on when the drain is connected to the power supply wiring of the power supply voltage Vdd, the source is connected to the FD unit 26, and the gate is supplied with the reset pulse RST via the reset wiring 121B. Prior to the transfer of the signal charge to the unit 26, the FD unit 26 is reset by discarding the charge of the FD unit 26 to the power supply (Vdd) wiring.

  The amplification transistor 24 has a gate connected to the FD unit 26 and a drain connected to the power supply wiring of the power supply voltage Vdd, and outputs the potential of the FD unit 26 after being reset by the reset transistor 23 as a reset level. Thus, the potential of the FD portion 26 after the signal charge is transferred from the photodiode 21 is output as a signal level.

  For example, the selection transistor 25 has a drain connected to the source of the amplification transistor 24 and a source connected to the vertical signal line 122. That is, the selection transistor 25 is connected in series with the amplification transistor 24 between the amplification transistor 24 and the vertical signal line 122. The selection transistor 25 is turned on when a selection pulse SEL is applied to the gate via the selection wiring 121C, and the signal amplified by the amplification transistor 24 is output to the vertical signal line 122 with the pixel 20A selected.

  FIG. 3 is a circuit diagram showing a circuit configuration of the pixel 20B according to the circuit example 2. In FIG. 3, the same parts as those in FIG.

  As illustrated in FIG. 3, the pixel 20 </ b> B according to the circuit example 2 is similar to the pixel 20 </ b> A according to the circuit example 1 in addition to the photodiode 21 that is a photoelectric conversion element, a transfer transistor 22, a reset transistor 23, and an amplification transistor. The circuit configuration includes four transistors 24 and a selection transistor 25.

  The pixel 20B according to the circuit example 2 is different from the pixel 20A according to the circuit example 1 in that the selection transistor 25 is connected in series to the amplification transistor 24 between the power supply (Vdd) wiring and the amplification transistor 24. It is a point that has been. That is, the selection transistor 25 is turned on when the drain is connected to the power supply (Vdd) wiring, the source is connected to the drain of the amplification transistor 24, and the selection pulse SEL is applied to the gate via the selection wiring 121C. The pixel 20B is selected by supplying the power supply voltage Vdd to 24 drains.

(Vertical drive circuit)
FIG. 4 is a block diagram showing an example of the configuration of the vertical drive circuit 13. As shown in FIG. 4, the vertical drive circuit 13 includes a row selection circuit 131, a multiplexer 132, a level shifter 133, and a buffer 134. Here, the ground and power supply input systems are not shown.

  The row selection circuit 131 is configured by a shift register, a decoder, or the like, and selectively scans a pixel row of the pixel array unit 12 according to a scanning signal or an address signal supplied from the control circuit 18. The multiplexer 132 outputs the pixel drive pulse supplied from the control circuit 18 as a transfer pulse TRF, a reset pulse RST, and a selection pulse SEL to the pixel row that has been selectively scanned by the row selection circuit 131.

  The level shifter 133 shifts (level-converts) the high level and low level of the pixel drive pulse supplied from the multiplexer 132 to predetermined levels. The level shifter 133 is supplied with the negative voltage generated by the negative voltage generation circuit 19. The pixel drive pulse level-shifted by the level shifter 133, that is, the transfer pulse TRF, the reset pulse RST, and the selection pulse SEL are passed through the low impedance buffer 134 to the pixel drive wiring 121 (that is, the transfer wiring 121A, the reset wiring 121B, and the selection wiring 121C. ).

  In the solid-state imaging device 10 configured as described above, the present invention is characterized in that a depletion type transistor is used as the selection transistor 25 in the pixel 20. Since the selection transistor 25 is a depletion type transistor, it is possible to operate at a low voltage by reducing the threshold drop without increasing the gate voltage of the selection transistor 25 as in the prior art. The on-resistance can be lowered.

  Further, unlike the prior art that boosts the gate voltage, 1 / f noise and burst noise are reduced. This is presumably because depletion increases the ratio of the current component that flows not on the oxide film interface but on the bulk side in the select transistor 25.

  By the way, a depletion type transistor is not normally used as a switch element because it has a characteristic that current cannot be cut off, that is, cannot be turned off with respect to a ground (ground) voltage, that is, the same voltage as a well in which the transistor is formed. The selection transistor 25 has a role of a switch, and its source side is set to become a ground voltage through the load transistor 31 of the constant current source 30 connected to the vertical signal line 122 as shown in FIG. This is not an example.

  However, in the present invention, a configuration using a depletion type transistor as the selection transistor 25 is used. Even the depletion type transistor can perform the function of selecting a row by the potential difference between the state in which the selection transistor 25 is turned on and the state in which the selection transistor 25 is turned off. Here, the current value flowing through the selection transistor 25 is not a large current because the current value of the constant current source is, for example, several μA per one vertical signal line, but it is desirable to cut off the current at the selection transistor 25. This is because power consumption may increase, current may flow to a specific pixel, the characteristics of the pixel may change, or a thermionic white spot may occur.

Therefore, in the present invention, when a depletion type transistor is used as the selection transistor 25, it is effective to employ at least one of the following two methods in order to cut off the current in the selection transistor 25.
The constant current source 30 is also turned off when all the selection transistors 25 of the pixels 20 connected to one vertical signal line 122 are turned off.
A negative voltage is applied to the gate when the selection transistor 25 is turned off.

  By adopting one or both of these two methods, even if the selection transistor 25 is a depletion type transistor, the current can be cut off by the selection transistor 25. Therefore, an increase in power consumption or some pixels In addition, the effect of the depletion type transistor, that is, the effect of reducing 1 / f noise and burst noise due to the finite on-resistance of the selection transistor 25 can be obtained.

  Subsequently, the latter method, that is, a specific embodiment in which a negative voltage is applied to the gate when the selection transistor 25 is turned off will be described below.

[First embodiment]
In the first embodiment, when the selection transistor 25 in the pixel 20 is turned off, the gate voltage is set to the off side of the voltage of the well in which the selection transistor 25 is formed, in this example, a negative voltage. It is said.

  Specifically, the negative voltage generated by the existing negative voltage generation circuit 19 (see FIG. 1) is used, and the level shift (level conversion) in the level shifter 133 shown in FIG. As for the pulse SEL, the low level is set to the negative voltage of the negative voltage generation circuit 19 so that a negative voltage is applied to the gate when the selection transistor 25 is turned off.

  In the constant current source 30, the load transistor 31 applies a small constant current such as several μA to the selection transistor 25 through the vertical signal line 122 by applying a voltage slightly higher than the threshold value to the gate. Become.

  The reference voltage of the selection transistor 25 is the voltage of the P well which is the back bias. The voltage of the P well is the ground voltage. By applying a negative voltage to the gate with respect to the reference voltage that is the ground voltage, the current can be cut even if the selection transistor 25 is a depletion type transistor.

  As described above, when a depletion type transistor is used as the selection transistor 25, when the selection transistor 25 in the pixel 20 is turned off, the gate voltage is set to the off side with respect to the voltage of the well in which the selection transistor 25 is formed. In this example, by setting the negative voltage, the current is surely cut off when the selection transistor 25 is off, and the operation effect of the depletion type transistor, that is, the finite on-resistance of the selection transistor 25 is caused. The effect of reducing 1 / f noise and burst noise can be obtained.

  Further, by using the existing negative voltage generation circuit 19, the negative voltage generated by the negative voltage generation circuit 19 and applied to the gate voltage when the transfer transistor 22 is turned off is set to the low level of the gate voltage of the selection transistor 25. Since they are shared, there is no need to dispose the negative voltage generation circuit 19 just for adopting this embodiment. Therefore, there are no disadvantages such as an increase in cost and defects due to the adoption of this embodiment, and an increase in the size of the module due to the newly required external capacity.

  In the case of adopting the configuration of this embodiment in which a negative voltage is applied to the gate when the selection transistor 25 is turned off, the pixel 20A according to the circuit example 1 as the pixel 20, that is, the selection transistor 25 is connected to the amplification transistor 24 in the vertical signal line 122 It is desirable to adopt a pixel configuration arranged in series on the side.

  The reason is that, in the case of the pixel 20B according to the circuit example 2, the selection transistor 25 has a negative voltage at the gate and a power supply voltage Vdd at the drain, and the potential difference between the gate and the drain becomes large. In contrast, in the case of the pixel 20A according to the circuit example 1, even if a negative voltage is applied to the gate of the selection transistor 25, the potential difference between the gate and the drain can be suppressed to be small. .

  In FIG. 4, the level shifter 133 has a configuration in which a unit circuit having a level shift function is provided for each row corresponding to each of the transfer pulse TRF, the reset pulse RST, and the selection pulse SEL.

  Then, the negative voltage generated by the negative voltage generation circuit 19 is used as a negative power supply voltage in the unit circuit for the transfer pulse TRF for the purpose of reducing the dark current described above. In order to reduce this, the unit circuit for the selection pulse SEL is supplied as a negative power supply voltage (previously, the ground voltage), but the unit circuit for the reset pulse RST is also supplied as a negative power supply voltage. A voltage may be supplied. As a result, a negative voltage can be commonly supplied to the unit circuits for the transfer pulse TRF, the selection pulse SEL, and the reset pulse RST as a negative power supply voltage, so that the configuration of the level shifter 133 is simplified. Can be achieved.

[Second Embodiment]
In the first embodiment, the load transistor 31 is used as the constant current source 30 for supplying a current of about several μA. In the second embodiment, the load transistor 31 operates as a switching element instead of a constant current source. It adopts a configuration to make it. Specifically, in FIG. 2, by applying the switching pulse LOAD shown in FIG. 5 to the gate of the load transistor 31, the load transistor 31 has a role as a switching element.

  Here, since the load transistor 31 simply operates as a switch, a large current of several tens of μA or more can flow when the load transistor 31 is on. Specifically, for example, the high level of the gate voltage at the time of ON, that is, the high level of the switching pulse LOAD is set to the power supply voltage Vdd. As with the first embodiment, the selection transistor 25 is a depletion type transistor, and the gate voltage when the transistor is off is a negative voltage.

  Next, the operation of the pixel 20 and the load transistor 31 when the technique according to the second embodiment is applied will be described with reference to the timing chart of FIG.

  The switching pulse LOAD for switching and driving the load transistor 31 is activated (for example, the power supply voltage Vdd) in a state where the selection transistors 25 of all the pixels connected to the vertical signal line 122 are turned off (the selection pulse SEL is in a low level). And Then, the load transistor 31 is turned on, and the potential of the vertical signal line 122 is set to a predetermined voltage, in this example, the ground voltage. By making the reset pulse RST active (high level) while the potential of the vertical signal line 122 is low, the reset transistor 23 is turned on to reset the FD section 26 of the pixel 20 in the selected row.

  Thereafter, the selection transistor 25 is turned on by making the selection pulse SEL of the selected row active (high level). As a result, the potential of the vertical signal line 122 converges toward a voltage corresponding to the potential of the FD unit 26. This reflects a state in which the FD unit 26 is reset by the reset transistor 23.

  When the potential of the vertical signal line 122 converges to some extent toward the voltage corresponding to the potential of the FD section 26, the corresponding column circuit of the column circuit group 14 (see FIG. 1) sets the potential of the vertical signal line 122 to the reset level. Sampling. Thereafter, the selection pulse SEL is deactivated (negative voltage, for example, −1 V), and the selection transistor 25 is turned off.

  Next, the load transistor 31 is turned on again by the switching pulse LOAD, thereby lowering the potential of the vertical signal line 122 and activating the transfer pulse TRF while the potential of the vertical signal line 122 is low ( (High level), the transfer transistor 22 is turned on, and the signal charge photoelectrically converted by the photodiode 21 is transferred to the FD unit 26.

  Thereafter, the selection transistor 25 is turned on by activating the selection pulse SEL of the selected row. As a result, the potential of the vertical signal line 122 converges toward a voltage corresponding to the potential of the FD unit 26. This time, the state in which the signal charge is transferred from the photodiode 21 and held in the FD unit 26 is reflected.

  When the potential of the vertical signal line 122 converges to some extent, the previous column circuit samples the potential of the vertical signal line 122 as the signal level. Thereafter, the selection pulse SEL is deactivated, and the selection transistor 25 is turned off.

  The column circuit corresponding to the column circuit group 14 performs processing for removing fixed pattern noise unique to the pixel by taking the difference between the reset level sampled at the first time and the signal level sampled at the second time, The signal does not contain noise.

  As described above, the load transistor 31 is operated as a switch rather than a constant current source, and after the potential of the vertical signal line 122 is lowered to a low level by a short pulse, a signal is read from the pixel 20 without a constant current flowing. Since the voltage loss in the load transistor 31 can be eliminated, the voltage can be lowered, and since only the charge / discharge current flows through the vertical signal line 122, the power consumption can be reduced.

  Note that the load transistor 31 is not a constant current source but a low impedance switch in order to set the potential of the vertical signal line 122 to a low level by a short pulse. In this case, if the selection transistor 25 is simply depleted, the selection transistor 25 cannot be turned off during the active period of the switching pulse LOAD applied to the load transistor 31, and is, for example, 10 to 100 times larger than in the case of the first embodiment. Current will flow. At this time, in addition to the serious problem similar to the case where the selection transistor 25 is simply depleted in the first embodiment, the voltage drop of the ground wiring and the power supply wiring also becomes a problem. Therefore, it is particularly effective to switch the selection transistor 25 by switching the current by setting the gate voltage when the selection transistor 25 is turned off to a negative voltage.

  In the above embodiment, an example in which N-channel MOS transistors are used as the four transistors 22 to 25 of the pixels 20A and 20B in the circuit examples 1 and 2 has been described. However, a configuration using P-channel MOS transistors is used. It is also possible to adopt. In this case, a booster circuit may be provided in place of the negative voltage generation circuit 19, and the gate voltage when the selection transistor 25 is turned off may be a voltage exceeding the power supply voltage Vdd.

  In the above embodiment, a solid-state imaging device that detects the light intensity of incident light that has passed through a subject has been described as an example of a physical quantity detection device that detects a physical quantity given from the outside. However, the present invention is not limited to a solid-state imaging device. , A fingerprint detection device (capacitance detection device) that detects the capacitance formed between the detection electrode and the surface of the finger according to the unevenness of the fingerprint, or a physical quantity given from outside such as pressure or chemical substance A detection device that detects a distribution or the like may be used, and pixels including a detection unit that detects a physical quantity given from the outside and a selection transistor that selectively outputs a signal of the detection unit to a signal line are two-dimensionally arranged in a matrix The present invention is applicable to all physical quantity detection devices.

[Application example]
The solid-state imaging device 10 according to the above-described embodiment is suitable for use as an imaging device (image input device) in an imaging device such as a digital still camera or a video camera.

  Here, the imaging device includes a solid-state imaging device as an imaging device, an optical system that forms image light of a subject on an imaging surface (light-receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device. A camera module (for example, used by being mounted on an electronic device such as a mobile phone) and a camera system such as a digital still camera or a video camera equipped with the camera module.

  FIG. 6 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 6, the imaging apparatus according to the present example includes an optical system including a lens 41, an imaging device 42, a camera signal processing circuit 43, and the like.

The lens 41 forms image light from the subject on the imaging surface of the imaging device 42. The imaging device 42 outputs an image signal obtained by converting the image light imaged on the imaging surface by the lens 41 into an electrical signal in units of pixels. As the imaging device 42, the solid-state imaging device 10 according to the above-described embodiment is used. The camera signal processing circuit 43 performs various signal processing on the image signal output from the imaging device 42.

  As described above, by using the solid-state imaging device 10 according to the above-described embodiment as the imaging device 42 in an imaging device such as a video camera, an electronic still camera, and a camera module for a mobile device such as a mobile phone, Since the solid-state imaging device 10 can reduce 1 / f noise and burst noise caused by the finite on-resistance of the selection transistor in the pixel, a captured image with extremely little noise can be obtained.

  DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device, 11 ... Semiconductor substrate, 12 ... Pixel array part, 13 ... Vertical drive circuit, 14 ... Column circuit group, 15 ... Horizontal drive circuit, 16 ... Horizontal signal line, 17 ... Output circuit, 18 ... Control circuit , 19 ... Negative voltage generation circuit, 20, 20A, 20B ... Pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor, 25 ... Selection transistor, 26 ... FD (floating diffusion) part, 30 ... Constant current source, 31 ... Load transistor

Claims (8)

Pixels including a detection unit that detects a physical quantity given from the outside, an amplification transistor that amplifies a signal detected by the detection unit, and a selection transistor that selectively outputs the signal amplified by the amplification transistor to a signal line are arranged in a matrix Two-dimensionally arranged,
The selection transistor is a depletion type transistor, and is arranged in series on the signal line side with respect to the amplification transistor,
A physical quantity detection device, wherein a gate voltage when turning off the selection transistor is set to a voltage on an off side of a voltage of a well in which the selection transistor is formed. The physical quantity detection device according to claim 1, wherein a gate voltage when the selection transistor is turned off is a negative voltage. A constant current source is connected to the signal line,
The physical quantity detection device according to claim 1, wherein the constant current source is turned off when all of the selection transistors in the pixel corresponding to the signal line are off. A switch element for selectively setting the potential of the signal line to a predetermined voltage is connected to the signal line,
The physical quantity detection device according to claim 1, wherein the signal of the pixel is output to the signal line by turning on the selection transistor after setting the potential of the signal line to the predetermined voltage through the switch element. The pixel includes a charge holding unit and a transfer transistor that transfers a signal charge corresponding to the physical quantity detected by the detection unit to the charge holding unit,
When the gate voltage when the transfer transistor is turned off is set to a voltage on the off side of the voltage of the well in which the transfer transistor is formed, the gate voltage when the selection transistor is turned off The physical quantity detection device according to claim 1, which is used in common with a gate voltage when turning off. Amplifier transistor for amplifying the photoelectric conversion element for converting incident light from the outside to the signal charges, a voltage corresponding to the signal charge of the photoelectric conversion elements, and the selection of the amplification transistor outputs to selectively signal line signal amplification A solid-state imaging device in which pixels including transistors are two-dimensionally arranged in a matrix;
An optical system for guiding light from a subject onto the imaging surface of the solid-state imaging device,
The selection transistor is a depletion type transistor, and is arranged in series on the signal line side with respect to the amplification transistor,
The gate voltage when turning off the selection transistor is an off-side voltage with respect to a voltage of a well in which the selection transistor is formed. The imaging device according to claim 6 , wherein a gate voltage when the selection transistor is turned off is a negative voltage. A constant current source is connected to the signal line,
The imaging apparatus according to claim 6 , wherein the constant current source is turned off when all of the selection transistors in the pixel corresponding to the signal line are turned off.

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