JP2011250000A - Burst optical signal processing unit and burst optical signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid base line drift without need for synchronizing a burst electric signal with a dummy signal during guard time of the burst electric signal.SOLUTION: A burst optical signal processing unit includes: a conversion means for converting a received burst optical signal into the burst electric signal; a coding means generating a coding signal from a first electric pulse signal and the burst electric signal by an exclusive OR operation to output the signal; a reproducing means for logically identifying and reproducing the coding signal and reproducing a clock signal; a first signal generating means synchronizing a phase with the reproduced clock signal and generating the first electric pulse signal and a second electric pulse signal, which have smaller code transition density than the burst electric signal, and outputting the first electric pulse signal and the second electric pulse signal during a non-signal period of the burst electric signal and a decoding means for decoding the coding signal by using the second electric pulse signal.

Description

  The present invention relates to a burst optical signal processing device and a burst optical signal processing method.

  Currently, Passive Optical Network (PON) is widely used as a service by Fiber To The Home (FTTH). A network configuration of the PON is shown in FIG. In the PON network, an optical network unit (ONU) 801, which is a plurality of subscriber terminal devices, is connected to an optical line terminal (OLT) 803, which is a central office device, via an optical splitter 802 via an optical fiber. It is the composition which is. The PON is an economical optical network because a plurality of ONUs 801 can share a transmission path between the optical splitter 802 and the OLT 803.

  Currently, GEPON (Gigabit Ethernet (registered trademark) -Passive Optical Network) having a bandwidth of 1 Gbps is used in Japan. Non-Patent Document 1 discloses this GEPON technology. In recent years, 10G-EPON (10 Gigabit-Ethernet (registered trademark) Passive Optical Network) having a bandwidth 10 times that of GEPON has been standardized for further broadbandization. Non-Patent Document 2 discloses this 10G-EPON technology.

  In order to avoid collision of signals from each ONU 801, a burst transmission technique is used for the upstream signal of the PON. The receiver of the OLT 803 receives the burst optical signal transmitted from each ONU 801 by performing level drawing and clock synchronization.

  As shown in FIG. 27, a burst optical signal frame 900 includes a preamble 901 composed of a fixed pattern for level pulling and clock synchronization at the receiver of the OLT 803, a burst delimiter 902 indicating the end of the preamble, and a payload 903. Consists of. The preamble length includes time for level pull-in and time for clock synchronization of Clock and Data Recovery (CDR). Generally, the preamble 901 is an overhead made up of a predetermined fixed pattern. Therefore, there is a need for a burst optical receiver that can perform level pull-in and clock synchronization at high speed in order not to degrade the effective throughput of the system.

  In a burst optical receiver for PON (burst receiver) that requires cost reduction, it is desirable to use a resetless burst optical receiver circuit that has a small circuit scale and is suitable for cost reduction. FIG. 28 shows a configuration of a general burst optical signal receiving circuit. The burst optical signal receiving apparatus 1001 is mainly composed of two components. One is a 2R (Re-shaping, Re-generating) receiver (2R-Rx) 1002, and the other is a CDR 1003. The 2R-Rx 1002 and the CDR 1003 are AC-coupled by a capacitor C (capacitor) 1004. Yes.

  The 2R-Rx 1002 includes a photodiode (PD), a transimpedance amplifier (TIA), and a limiting amplifier (LIMAMP), and performs high-speed level pull-in and 2R reproduction. Non-Patent Document 3 describes an example of a high-speed level pull-in technique. The CDR performs Re-timing by a Phase Locked Loop (PLL) circuit, and performs 3R (Re-shaping, Re-generating, Re-timing) reproduction of a signal together with 2R-Rx.

  The output bias level of 2R-Rx 1002 and the input bias level of CDR 1003 are not necessarily equal. Therefore, it is desirable to ensure versatility of the design by AC coupling between the 2R-Rx 1002 and the CDR 1003 with the capacitor C1004.

  When AC coupling is performed between the 2R-Rx 1002 and the CDR 1003 with the capacitor C 1004 as described above, the following problems occur. This problem will be described with reference to FIG.

  FIG. 29 shows signal behavior when 2R-Rx 1002 and CDR 1003 are AC coupled. When the optical input signal 1101 is input, the 2R-Rx 1002 performs photoelectric conversion and level pull-in, limiting amplification, and a 2R-Rx output signal 1102 is output. Here, when the 2R-Rx 1002 and the CDR 1003 are AC-coupled, the signal level of the CDR input signal 1103 is determined by the time constant determined by the AC coupling capacitance and the line resistance during the no-signal interval (guard time) due to the influence of low-frequency cutoff. (Baseline) drift occurs.

  When the next burst optical signal is input in a state where the baseline is drifted, the reception sensitivity of the CDR 1003 deteriorates. Here, since the 2R-Rx output signal 1102 and subsequent signals are logic signals, the AC signal coupling between the 2R-Rx 1002 and the CDR 1003 causes the code (1 or 0) of the logic signal to fluctuate to near the code identification level. Therefore, it is not allowed to deteriorate the reception sensitivity.

  The influence of the baseline drift of the signal due to the low-frequency cutoff of the AC coupling circuit is generally known as reception sensitivity deterioration.

  The following methods have been proposed for the purpose of removing the low frequency cutoff of the AC coupling circuit and the baseline drift of the signal.

  Patent Document 1 describes a method of scrambling a transmission signal by Manchester encoding on the transmission side.

  Patent Document 2 discloses a method for suppressing baseline drift of a signal by inserting an optical clock signal during a guard time on the receiver side.

  In Patent Document 3, a scrambler using XOR (exclusive OR) and a descrambler are installed on both sides of AC coupling in a burst optical signal receiving circuit, and scrambled using a dummy signal during a guard time. Thus, a method for avoiding baseline drift of signals due to AC coupling is shown.

JP-A-8-191269 JP 2004-222116 A JP 2010-098425 A

IEEE 802.3ah-2004 IEEE 802.3av-2009 S. Takahashi et al., “Over 25-dB Dynamic Range 10- / 1-Gbps Optical Burst-mode Receiver using High-power-tolerant APD,” NME2, OFC2009.

  With the technique described in Patent Document 1, it is impossible to avoid the baseline drift of the signal during the guard time described above.

  In the technique described in Patent Document 2, there is a problem of deterioration of reception sensitivity with respect to an original burst optical signal due to insertion loss in an optical coupler.

  According to the technique described in Patent Document 3, it is possible to avoid baseline drift of a signal without causing deterioration of reception sensitivity with respect to the signal.

  However, in the technique described in Patent Document 3, it is necessary to output a dummy signal synchronized with the burst electric signal while receiving the burst electric signal. Therefore, there is a problem that frequency synchronization and phase synchronization between the burst electrical signal and the dummy signal must be obtained while receiving the burst electrical signal.

  An object of the present invention is to provide a burst optical signal processing apparatus and burst optical signal processing method capable of solving the above-described problems.

  The burst optical signal processing apparatus according to the present invention includes a converting means for converting a received burst optical signal into a burst electric signal, and an encoded signal from the first electric pulse signal and the burst electric signal by exclusive OR operation. Generating and outputting encoding means, reproducing means for performing logical identification reproduction of the encoded signal and reproduction of the clock signal, phase-synchronized with the reproduced clock signal, and having a code transition density higher than that of the burst electric signal. A small number of the first electric pulse signal and the second electric pulse signal are generated, and the first electric pulse signal and the second electric pulse signal are output at least during the no-signal period of the burst electric signal. First signal generating means for decoding, and decoding means for decoding the encoded signal using the second electric pulse signal.

  The burst optical signal processing method of the present invention includes a conversion step of converting a received burst optical signal into a burst electrical signal, and an encoded signal from the first electrical pulse signal and the burst electrical signal by exclusive OR operation. An encoding step for generating and outputting; a reproduction step for performing logical identification reproduction of the encoded signal and reproduction of a clock signal; and phase synchronization with the reproduced clock signal, and a code transition density higher than that of the burst electric signal. A small number of the first electric pulse signal and the second electric pulse signal are generated, and the first electric pulse signal and the second electric pulse signal are output at least during the no-signal period of the burst electric signal. A first signal generation step, and a decoding step of decoding the encoded signal using the second electric pulse signal.

  According to the present invention, it is possible to automatically synchronize the burst electric signal and the dummy signal, and it is possible to avoid the baseline drift during the guard time without deterioration of the signal quality.

It is a figure which shows the structure of the burst optical signal processing apparatus in 1st Embodiment. It is a figure which shows the frequency synchronization and phase synchronization of this invention. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 1st Embodiment. It is a block diagram at the time of arrange | positioning the frequency divider 115 and the dummy signal generator 1102-1 in 1st Embodiment in the burst optical receiver circuit 100-2. FIG. 5 is a configuration diagram when a frequency divider 115 and a dummy signal generator 1102-1 in the first embodiment are arranged in a dummy signal generating circuit 1100. It is a figure which shows the structure of the burst optical signal processing apparatus in 2nd Embodiment. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 2nd Embodiment. It is a figure which shows the structure of the burst optical signal processing apparatus in 3rd Embodiment. It is a figure which shows the structure of the delay control circuit in 3rd Embodiment. It is a time chart of each signal in a 3rd embodiment. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 3rd Embodiment. It is a flowchart which shows operation | movement of the delay control circuit in 3rd Embodiment. It is a figure which shows the structure of the burst optical signal processing apparatus in 4th Embodiment. It is a figure which shows the structure of the delay control circuit in 4th Embodiment. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 4th Embodiment. It is a flowchart which shows operation | movement of the delay control circuit in 4th Embodiment. It is a figure which shows the structure of the burst optical signal processing apparatus in 5th Embodiment. It is a figure which shows the structure of the delay control circuit in 5th Embodiment. It is a figure which shows the structure of the code state determination circuit in 5th Embodiment. It is a time chart of each signal in a 5th embodiment. It is a determination / control circuit truth table in the fifth embodiment. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 5th Embodiment. It is a flowchart which shows operation | movement of the delay control circuit and code | symbol state determination circuit in 5th Embodiment. It is a figure which shows the structure of the burst optical signal processing apparatus in 6th Embodiment. It is a flowchart which shows operation | movement of the burst optical signal processing apparatus in 6th Embodiment. It is a figure which shows the general network structure of PON. It is a figure which shows the frame structure of the burst signal used for PON. It is a figure which shows the structure of a general burst optical signal receiver. It is a figure which shows the mode of the baseline drift of the signal by AC coupling.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
(Configuration and operation)
The configuration and operation of the first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a burst optical signal processing apparatus 1000-1 according to the first embodiment of the present invention. FIG. 3 is a flowchart showing a flow of operations according to the first embodiment of the present invention.

  In FIG. 1, a burst optical signal processing apparatus 1000-1 includes a burst optical receiving circuit 100-1 and a logic circuit 110-1. The AC coupling circuit C0 120 connects the burst light receiving circuit 100-1 and the logic circuit 110-1.

  The burst light receiving circuit 100-1 includes 2R-Rx 101 and XOR1 103. 2R-Rx 101 and XOR1 103 are connected by DC coupling (not shown in FIG. 1).

  The 2R-Rx 101 receives the burst optical signal (STP 1001 in FIG. 3), performs photoelectric conversion and limiting amplification on the burst optical signal, generates a burst electric signal S01-1, and supplies it to the XOR1 103 (FIG. 3). STP1002).

  The XOR1 103 performs an XOR (exclusive OR) operation on the burst electric signal S01-1 and the first dummy signal S02-1 generated in the logic circuit 110-1, and generates a scramble signal S03 ( FIG. 3 STP1003). The first dummy signal S02-1 will be described later.

  The scramble signal S03 is supplied to the logic circuit 110-1 via the AC coupling circuit C0 120.

  The logic circuit 110-1 includes a CDR 111, an XOR2 113, a frequency divider 115, and a dummy signal generator 1 102-1.

  The CDR 111 performs 3R reproduction of the scramble signal S03 and supplies the reproduced scramble signal S03 to the XOR2 113 (STP 1004 in FIG. 3). At the same time, the recovered clock S04 is extracted from the scramble signal S03 and output, and the clock S04 is supplied to the frequency divider 115 (STP 1005 in FIG. 3).

  The frequency divider 115 divides the clock S04 extracted by the CDR 111 by N (N is a natural number), generates a divided clock S04-2 that is synchronized with the clock S04, and uses the divided clock S04-2 as a dummy signal. It supplies to the generator 1 102-1 (FIG. 3 STP1006).

  The dummy signal generator 1 102-1 generates a first dummy signal S02-1 and a second dummy signal S02-2 that are synchronized with the divided clock S04-2, and generates the first dummy signal S02-1. The second dummy signal S02-2 is supplied to the XOR1 103 to the XOR2 113 (STP 1007 in FIG. 3).

  Here, the first dummy signal S02-1 and the second dummy signal S02-2 are generated in synchronization with the frequency-divided clock S04-2 and have an arbitrary code with a mark ratio of ½ having the same sequence. Is used. However, even if it is an arbitrary code, it is necessary to set so that the same code continuous length does not become too long. This is to prevent the frequency components included in the first dummy signal S02-1 and the second dummy signal S02-2 from being affected by the low-frequency cutoff of the AC coupling C0 120.

  The XOR2 113 performs an XOR operation on the 3R regenerated scramble signal S03 and the second dummy signal S02-2 and decodes the burst electric signal S01-2 (STP 1008 in FIG. 3).

  The CDR 111 and the XOR2 113 may be connected by an AC coupling circuit C1 114 having a time constant equivalent to that of the AC coupling C0 120.

  The amount of delay between the dummy signal generator 1 102-1 and the XOR1 103 is such that the code transition timing of the dummy signal S02-1 generated by the divided clock S04-2 is the burst electric signal S01-1 at the input of the XOR1 103. It is assumed that it coincides with the code transition timing.

  Further, the delay amount from the dummy signal generator 1 to the XOR2 113 is a value obtained by adding the propagation delay amount of the scramble signal S03 from the XOR1 103 to the XOR2 113 to the delay amount between the dummy signal generator 1102 and the XOR1 103. To do.

The value of the bit rate ratio N between the first dummy signal S02-1, the second dummy signal S02-2, and the burst electric signal S01-1 is preferably set as follows.
(1) The frequency components included in the first dummy signal S02-1 and the second dummy signal S02-2 are set so as not to be affected by the low-frequency cutoff of the AC coupling capacitor C0 120.
(2) The code transition density of the dummy signal S02-1 is set to be smaller than the code transition density of the burst electric signal S01-1.

(Frequency synchronization, phase synchronization, signal regeneration mechanism)
The mechanism of frequency synchronization and phase synchronization between the burst electric signal S01-1 and the first dummy signal S02-1 and the signal reproduction in this embodiment will be described with reference to the drawings.

  First, frequency synchronization and phase synchronization will be described.

  FIG. 2 shows the burst electrical signal S01-1 (S01-1a, S01-1b), the time of the scramble signal S03 output by the CDR output clock S04, the first dummy signal S02-1, and the XOR1 103 in this embodiment. A chart is shown. Note that the sign transition of the second dummy signal S02-2 is the same as that of the first dummy signal S02-1, and thus the description is omitted in FIG.

  For simplification of the drawing, the bit rate of the first dummy signal S02-1 is shown as 1/4 of the burst electric signal S01-1.

  During reception of the burst electrical signal S01-1a (the first half of the time chart of FIG. 2), the first dummy signal S02-1 is a divided clock S04-2 (FIG. 2) obtained by dividing the CDR output clock S04 output by the CDR 111. 2 is not displayed), and the pattern is synchronized with the burst electric signal S01-1 in frequency synchronization and phase synchronization. Therefore, the scramble signal S03 output from the XOR1 103 maintains an eye pattern without deterioration.

  When the burst electrical signal S01-1a ends and the guard time period is reached, the CDR output clock S04 output by the CDR 111 gradually shifts from the state synchronized with the burst electrical signal S01-1a to the free-run state (FIG. 2). "Free-run section").

  In this state, when the next burst electric signal S01-1b is input, a shift occurs between the code transition timings of the burst electric signal S01-1b and the first dummy signal. Here, when the code transition densities of the first dummy signal S02-1 and the second dummy signal S02-2 are equal to the code transition density of the burst electric signal S01-1, the first dummy signal S02-1 The influence of the code transition of becomes dominant. For this reason, clock recovery in synchronization with the burst electric signal S01-1b in the CDR 111 is impossible.

  However, in the present embodiment, as shown on the time chart of the scramble signal S03 in FIG. 2, the ratio of occurrence of an extra cross point due to the phase mismatch periodically is the ratio of 1 bit in N bits of the scramble signal S03. It becomes possible to suppress to.

  In the burst optical signal processing apparatus according to the present embodiment, the bit rate is reduced to 1 / N by using the divided clock S04-2 as the signal source of the first dummy signal S02-1 and the second dummy signal S02-2. (In FIG. 2, it was set to 1/4 for simplification). By supplying a signal generated using the divided clock S04-2, the influence of the code transition of the CDR output clock S04 becomes more dominant than that of the first dummy signal S02-1. As a result, the frequency information and phase information of the 2R-Rx output signal S01-1b are correctly transmitted to the CDR 111 in the N-1 bit among the N bits. Therefore, the frequency and phase of the CDR output clock S04 gradually coincide with the burst electric signal S01-1b, and following this, an extra cross point due to the phase mismatch is reduced, and the state shifts to the synchronous state.

  When the CDR 111 outputs the CDR output clock S04 synchronized with the burst electric signal S01-1b, the frequency divider 115 supplies the frequency-divided clock S04-2 obtained by dividing the CDR output clock S04 to the dummy signal generator 1102-1. Supply. As a result, the frequency and phase information of the burst electric signal S01-1b is transmitted to the dummy signal generator 1102-1, and the first dummy signal S02-1 with respect to the burst electric signal S01-1 and the scramble signal S03. And the second dummy signal S02-2 can be synchronized in frequency and phase.

  When the synchronization between the first dummy signal S02-1 and the burst electric signal S01-1 is completed, the XOR1 103 generates a scramble signal S03 without eye pattern degradation (payload section in FIG. 2). The CDR 111 receives the scramble signal S03 via the AC coupling circuit C0 120.

  In the CDR 111, the scramble signal S03 is 3R reproduced, and the reproduced scramble signal S03 is supplied to the XOR2 113. In the XOR2 113, the second dummy signal S02-2 having the same pattern as the first dummy signal S02-1 and the scrambled signal S03 reproduced by 3R are XORed to perform the descrambling, and the burst electric signal S01- 2 is decrypted.

  As described above, even in a long guard time interval, a signal passing through the AC coupling circuit C0 120 does not have a guard time longer than the same code continuous length of the first dummy signal S02-1. Therefore, when 2R-Rx 101 and CDR 111 are connected only by AC coupling, it is possible to avoid baseline drift of the signal that occurred during the guard time of burst electric signal S01-1.

  Further, the first dummy signal S02-1 can be synchronized with the burst electric signal S01-1 without generating a dummy signal during the guard time of the burst electric signal S01-1. Therefore, it is possible to reproduce the signal without causing erroneous identification in the CDR 111.

  The present embodiment has the same configuration as that of the present embodiment even when the burst electrical signal S01-1 has no guard time and another burst signal having a phase shifted from the burst electrical signal S01-1 is input. The same effect is produced.

  In this embodiment, the frequency divider 115 and the dummy signal generator 1102-1 are provided in the logic circuit 110-1. However, the installation locations are not limited to the logic circuit 110-1. Absent. As shown in FIG. 4, the frequency divider 115 and the dummy signal generator 1102-1 can be provided in the burst light receiving circuit 100-2. Further, as shown in FIG. 5, it can be provided in a circuit other than the burst light receiving circuit 100 and the logic circuit 110 (for example, the dummy signal generating circuit 1100 in FIG. 5). The operations in the configurations shown in FIGS. 4 and 5 are substantially the same as the operations of the present embodiment described above, and thus detailed description thereof is omitted.

  In this embodiment, the frequency divider 115 divides the clock S04 extracted by the CDR 111 by N. However, the first dummy signal S02-1 and the second dummy signal S02-2 are output so that the influence of the code transition of the CDR output clock S04 is more dominant than the first dummy signal S02-1. If it is possible, frequency division by the frequency divider 115 is not necessarily performed.

  Consider the case where the bit rate ratio N of the first dummy signal S02-1, the second dummy signal S02-2, and the burst electric signal S01-1 is 4, as in the example described in FIG. . In the above example, the CDR output clock S04 has been divided by four. However, the dummy signal generator 1102-1 makes the same code 4 bits continuous, performs code transition, and makes the same code 4 bits continuous. It is conceivable to perform control such that code transition is performed again. Specifically, the CDR output clock S04 is divided by four by generating a sequence in which “1” is continued four times, then “0” is continued four times, and the transition is made to “1” again. It is possible to obtain the same signal as the case.

<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram showing the configuration of the burst optical signal processing apparatus 1000-4 of the present embodiment. FIG. 7 is a flowchart showing an operation flow of the present embodiment.

  In the first embodiment (FIG. 1), one dummy signal generator (dummy signal generator 1 102-1) is connected to the first dummy signal S02-1 and the second dummy with respect to XOR1 103 and XOR2 113. The signal S02-2 is supplied.

  However, as shown in FIG. 6, in the burst optical signal processing apparatus 1000-4 in the present embodiment, the output of the CDR 111 is parallel-converted by a serial / parallel converter (S / P) 116, and signal processing is performed in parallel processing. Can be taken.

  In this case, in addition to the dummy signal generator 1102 (FIG. 1) in the first embodiment described above, a dummy signal generator composed of a parallel processing circuit is required.

  In order to solve this problem, the burst optical signal processing apparatus 1000-4 in the present embodiment has a dummy signal generator 1102-2 installed in the burst optical receiving circuit 100-4 as shown in FIG. The logic circuit 110 includes a dummy signal generator 2112. Since other configurations are the same as those of the first embodiment (FIG. 1), description thereof is omitted.

  Hereinafter, only the difference from the first embodiment will be described with reference to FIGS. 6 and 7 for the configuration and operation of the present embodiment.

  As described above, the burst optical signal processing apparatus 1000-4 of this embodiment includes two dummy signal generators (dummy signal generator 1102-2 and dummy signal generator 2 112).

  The dummy signal generator 1 102-2 outputs the first dummy signal S02-1 in synchronization with the frequency-divided clock S04-2 output from the frequency divider 115, and supplies it to the XOR1 103 (STP1007-1).

  In parallel with the STP 1007-1, the dummy signal generator 2 112 generates a second dummy signal S02-2 having the same pattern as the first dummy signal S02-1, and supplies it to the XOR2 113 ( STP1007-2). Further, the dummy signal generator 2 112 refers to the trigger signal from the dummy signal generator 1 102-2 and sets the phase of the second dummy signal S02-2 to the transmission timing of the first dummy signal S02-1. Transmission timing control is performed so that they match.

  The S / P 116 converts the output signal of the CDR 111 into a parallel signal and supplies it to the XOR2 113 (STP 1009). Thereafter, the XOR2 113 performs an XOR operation on the signal received at the STP 1009 and the second dummy signal S02-2 output from the dummy signal generator 2112, and decodes the burst electric signal S01-2 (STP1008).

  According to this embodiment, even when two XOR circuits having different processing methods are used, the same effect as that of the first embodiment can be obtained.

<Third Embodiment>
The configuration and operation of the third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 8 is a block diagram showing the configuration of the burst optical signal processing apparatus 1000-5 of this embodiment. FIG. 11 is a flowchart showing an operation flow of the present embodiment.

  In the first and second embodiments, the burst electrical signal S01-1 and the first dummy signal S02-1 are in an ideal phase relationship.

  However, when there is a temperature characteristic or a mounting error in the circuit delay, the first dummy signal S02-1 does not have an optimal phase, which may cause erroneous identification in the CDR 111.

  In order to solve this problem, the burst optical reception processing apparatus 1000-5 according to the third embodiment of the present invention includes a delay control circuit 106 in the burst optical reception circuit 100-5 as shown in FIG. . The delay control circuit 106 monitors the burst electric signal S01-1 and the first dummy signal S02-1, thereby detecting a phase shift and controlling the delay amount of the delay 104. This operation corresponds to the STP 1010 in the flowchart of FIG. Since other components and operations are substantially the same as those in the first embodiment, description thereof is omitted.

  As the delay 104, for example, a programmable delay line that is a well-known technique can be used. The same applies to all delays in the following embodiments.

  The delay control circuit 106 according to the present embodiment is realized by the configuration shown in FIG. FIG. 12 is a flowchart showing details of the operation in the delay control circuit (STP 1010 in FIG. 11). Hereinafter, the delay control circuit 106 in the present embodiment will be described with reference to FIGS. 9 and 12.

  As shown in FIG. 9, the delay control circuit 106 according to the present embodiment includes an FF (flip-flop) 6 401, a 1-bit delay 1 402, an FF 7 403, a 1-bit delay 2 404, and a half-bit delay 1 405. , FF8 406, half-bit delay 2 407, and decision / control circuit 408.

  The FF6 401 makes a logical determination of the burst electric signal S01-1 using the rising edge of the first dummy signal S02-1 as a trigger (STP1010-01). The 1-bit delay 1 402 gives a 1-bit delay to the signal S12 after the determination, and supplies it to the determination / control circuit 408 (STP1010-02).

  The 1-bit delay 2 404 gives a 1-bit delay to the first dummy signal S02-1 (STP1010-03). The FF7 403 makes a logical determination of the burst electric signal S01-1 using the rising edge of the first dummy signal S02-1 input via the 1-bit delay 2404 as a trigger, and determines / controls the signal S13 after the determination. It supplies to the circuit 408 (STP1010-04).

  Half-bit delay 1 405 gives a half-bit delay to the first dummy signal S02-1 (STP1010-05). The FF8 406 makes a logical determination of the burst electric signal S01-1 using the rising edge of the first dummy signal S02-1 input through the half-bit delay 1405 as a trigger (STP1010-06). Thereafter, the half-bit delay 2 407 gives a half-bit delay to the signal S14 after the determination, and supplies it to the determination / control circuit 408 (STP1010-07).

  The determination / control circuit 408 has a truth table indicating the relationship between the input of the signals S12, S13 and S14 and the output signal S15. From the input of the signals S12, S13, and S14, the phase advance or delay of the first dummy signal S02-1 with respect to the burst electrical signal S01-1 is determined (STP1010-08). Thereafter, the output signal S15 is output so as to cancel the phase difference between the first dummy signal S02-1 and the burst electric signal S01-1, and the delay 104 is controlled (STP1010-09).

  FIG. 10 shows the state of signals at various parts in the delay control circuit 106 according to the present embodiment when the first dummy signal S02-1 has a phase shift.

  Comparing the three signals (S12, S13, S14) input to the determination / control circuit 408, when the dummy signal is delayed, the signal patterns of S12 and S14 coincide with each other. The signal patterns of S14 match.

  The determination / control circuit 408 detects the advance or delay of the first dummy signal by referring to the truth table described in the determination / control circuit 408 of FIG. 9 from the states of the signals S12, S13, and S14. Then, the delay amount of the delay 104 is changed in the direction to cancel the phase difference.

  At this time, for stable operation of the delay control, an output signal S15 of the determination / control circuit may be smoothed by an LPF (Low-Pass Filter) 409, and the change in the delay amount of the delay 104 may be moderated.

  As described above, the advance or delay of the first dummy signal S02-1 can be detected. Therefore, even when there is a circuit delay temperature characteristic, a mounting error, or the like, the phase of the first dummy signal S02-1 can automatically follow the phase of the burst electric signal S01-1.

  Also in the present embodiment, it is possible to provide a dummy signal generator in the configuration of the second embodiment, that is, in the burst light receiving circuit 100-5.

<Fourth Embodiment>
The configuration and operation of the fourth embodiment of the present invention will be described in detail with reference to FIGS.

  In the third embodiment, two phase shifts are detected by monitoring the burst electrical signal S01-1 and the first dummy signal S02-1 that are inputs of the XOR1 103.

  This configuration can also be applied to the case where the first dummy signal S02-1 is compared with the output S03 of the XOR1 103 in place of the burst electric signal S01-1.

  FIG. 13 shows a burst optical reception processing apparatus 1000-6 in the present embodiment. FIG. 14 shows details of the delay control circuit 106 in the present embodiment. The configurations of FIGS. 13 and 14 are substantially the same as the configuration of the burst optical reception processing apparatus 1000-5 (FIG. 8) and the configuration of the delay control circuit 106 (FIG. 9) in the third embodiment. Explanation of elements is omitted.

  15 and 16 show the operation of the present embodiment and the operation of the delay control circuit 106 in the present embodiment, respectively. Since these operations are also similar to the operations in the third embodiment (FIGS. 11 and 12), description of similar operations is omitted.

  The difference from the third embodiment is that a 1-bit delay 107 is newly provided. In the present embodiment, the number of bits giving the delay is 1, but the present invention is not limited to this. For example, when the frequency divider 115 divides the frequency by N (N is a natural number), the same operation can be performed as long as it is an integer bit from 1 to N-1.

  When comparing the output signal S03 of the XOR1 103 with the first dummy signal S02-1, when the phases of the two signals are out of phase, the bits without the extra code transition due to the first dummy signal S02-1. Make a decision. Therefore, a 1-bit delay T107 is added to the signal obtained by branching the first dummy signal, and the resultant signal is supplied to the delay control circuit 106 (STP1011 and STP1012 in FIG. 15).

  According to the present embodiment, the same effect as that of the third embodiment can be obtained.

  Also in this embodiment, the configuration of the second embodiment can be applied. That is, a dummy signal generator different from the dummy signal generator 1102-1 can be provided in the burst light receiving circuit 100-6.

<Fifth Embodiment>
As another means for achieving phase synchronization between the burst electric signal S01-1 and the first dummy signal S02-1, the configuration shown in the present embodiment can be adopted.

  FIG. 17 is a block diagram showing a configuration of a burst optical signal reception processing apparatus 1000-7 according to the fifth embodiment of the present invention.

  The burst optical signal processing apparatus 1000-7 in this embodiment includes a delay control circuit 105 in place of the delay control circuit 106 in the configuration of the fourth embodiment (FIG. 13), and excludes the 1-bit delay 107 in FIG. It has a configuration. Since the basic configuration and operation are substantially the same as those in the fourth embodiment, description of the same configuration and operation is omitted.

  Hereinafter, the configuration and operation of the delay control circuit 105 will be described with reference to the configuration diagrams of FIGS. 17, 18, and 19, the truth table of FIG. 21, and the flowcharts of FIGS.

  The delay control circuit 105 monitors the output signal S03-2 of the XOR1 103, the output S02-1 of the delay 104, and the output clock S04 of the CDR 111, as shown in FIG. The phase difference from the first dummy signal S02-1 is detected, and the delay amount of the delay 104 is controlled (STP1013 in FIG. 22).

  The detailed configuration and operation (STP 1013) of the delay control circuit 105 will be described with reference to the configuration diagram of FIG. 18 and the flowchart of FIG.

  The delay control circuit 105 includes an FF1 201, an XOR3 202, an LPF1 203, a subtractor 204, an LPF2 205, an FF2 206, a code state determination unit 207, and a delay 208 t1.

  The FF1 201 performs a logical determination of the scrambled signal S03-2 obtained by branching the output signal S03 of the XOR1 103 using the rising edge of the output clock S04 of the CDR 111 as a trigger, and supplies the determined signal S05 to the XOR3 202 and the subtractor 204. (STP1013-01).

  The XOR3 202 performs an exclusive OR operation (XOR) on the scramble signal S03-2 obtained by branching the output of the XOR1 103 and the signal S05 on which the logic determination is performed by the FF1 201, and outputs a signal S06 (STP1013-04). . The output signal S06 is supplied to the code state determination unit 207 via the LPF1 203 (STP1013-05).

  LPF1 203 may be replaced with an element that can convert the pulse width of the XOR3 202 output into a voltage, such as a charge pump.

  The subtractor 204 performs subtraction between the scramble signal S03-2 branched from the output of the XOR1 103 and the output signal S05 of the FF1 201, and outputs a signal S07 (STP1013-02). The signal S07 is supplied to the code state determination unit 207 via the LPF2 205 (STP1013-03).

  The LPF2 205 makes it easy to detect the thin pulse output from the subtracter 204 in the subsequent code state determination unit 207. Note that an element capable of performing a sufficiently high-speed operation may be used instead of the LPF2 205.

  The delay t1 208 gives a minute delay to the scramble signal S03-2 obtained by branching the output signal S03 of the XOR1 103, and outputs a signal S03-3. If a minute delay is not given here, the code transition timings of the scramble signal S03-2 and the first dummy signal S02-1 coincide with each other, and the FF2 206 does not operate normally. The minute delay may be a value that allows the input D to be read correctly at the rising timing of the signal S03-3 in the FF2 206.

  The FF2 206 uses the signal S03-3 as a trigger, performs logic determination of the first dummy signal S02-1, and outputs a signal S08 (STP1013-06). The signal S08 is supplied to the code state determiner 207.

  The code state determination unit 207 determines the code state from the output signal S06 of the XOR3 202, the output signal S07 of the subtractor 204, and the output signal S08 of the FF2 206 when the dummy signal S02-1 rises, and controls the delay 104. To do.

  The code state determiner 207 can be realized by the configuration shown in FIG. The operation of the code state determiner 207 is shown together with the operation of the delay control circuit 105 in FIG.

  The code state determination unit 207 includes a first comparator 301, a second comparator 302, FF3 303, FF4 304, FF5 305, a determination / control circuit 306, and a delay t2 308.

  The first comparator 301 detects a positive pulse of the output S07 of the subtractor 204 at the rising edge of the first dummy signal S02-1 (STP1013-07). The FF3 303 supplies the determination / control circuit 306 with a signal S09 that is “+1” when there is a positive pulse and “−1” otherwise (STP1013-08).

  The second comparator 302 detects a negative pulse of the output S07 of the subtractor 204 when the first dummy signal S02-1 rises (STP1013-09). The FF4 304 supplies the determination / control circuit 306 with a signal S10 that is “+1” when there is a negative pulse and “−1” otherwise (STP1013-10).

  The delay t2 308 gives a minute delay to the first dummy signal S02-1, and outputs a signal S02-3. If a minute delay is not given here, the code transition timings of the first dummy signal S02-1 and the FF2 output signal S08 coincide with each other, and the FF5305 does not operate normally. The minute delay at the delay t2 308 must satisfy the following two conditions. (1) In FF5305, the value is such that the input D can be read correctly at the rising timing of the signal S02-3. (2) A value larger than the delay given to the scramble signal S03-2 at the delay t1 208.

  The FF5 305 makes a logical determination of the output S08 of the FF2 206, triggered by the rise of the signal S02-3 that gives a delay to the first dummy signal S02-1, and supplies the determination result S11 to the determination / control circuit 306. (STP1013-11).

  The determination / control circuit 306 determines the advance or delay of the first dummy signal S02-1 with respect to the burst electric signal S01-1 from the output S09 of the FF3 303, the output S10 of the FF4 304, and the output S11 of the FF5 305. (STP1013-12). Thereafter, a change in the delay amount is calculated from the determination result in STP 1013-12 and the average value of the output S06 of XOR3 202, and given to delay 104 (STP 1013-13).

  A phase synchronization method between the burst electric signal S01-1 and the first dummy signal S02-1 according to the present embodiment will be described below.

  As for the phase synchronization between the burst electric signal S01-1 and the first dummy signal S02-1, the sign of the burst electric signal S01-1 is “0 → 1” or “1” before and after the rising of the first dummy signal S02-1. This is possible by monitoring the state of the bit that transitions to “0”.

  FIG. 20 shows the state of the output signal of each part in the delay control circuit 105 when the phase synchronization is completed and when the first dummy signal S02-1 is advanced or delayed.

  An example will be described in which the phase of the first dummy signal S02-1 is delayed at the time of the sign transition of the rising edge of the first dummy signal S02-1 and the falling edge of the burst electric signal S01-1. This corresponds to the “dummy delay” (underlined) section of the “burst electrical signal falling” section of FIG.

  When the XOR1 102 performs an exclusive OR operation between the burst electric signal S01-1 and the first dummy signal S02-1 in a state where the clock phase of the first dummy signal S02-1 is delayed, the XOR1 102 A short “0” section is generated in the continuous “1” pulse of the scramble signal S03-2 obtained by branching the output signal S03. FIG. 20 shows a signal S03-3 obtained by adding a delay at the delay t1 208 to the scrambled signal S03-2.

  When the logic determination is performed on the scramble signal S03-2 by the FF1 201 using the clock S04 extracted by the CDR 111, a short “0” is not recognized in the output signal S05, and a continuous “1” pulse is generated. Become.

  In this state, when an exclusive OR operation is performed on the scramble signal S03-2 and the output S05 of the FF1 201 by the XOR3 202, as shown on the chart of the output signal S06 of the XOR3 202, a thin pulse included in the S03-2 Can be extracted.

  Further, when the subtracter 204 takes the difference between the output signal S03 of the XOR1 103 and the output signal S05 of the FF1 201, a signal S07 composed of “+1”, “0”, “−1” can be generated.

  The FF2 206 makes a logical determination of the first dummy signal S02-1 by using the rising edge of the signal S03-3 that gives a minute delay to the scramble signal S03-2 as a trigger by the delay t1 208. In this case, a signal S08 that is “1” is output at a timing that coincides with the rising timing of the signal S03-3.

  In the code state determination unit 207, the phase shift direction between the burst electric signal S01-1 and the first dummy signal S02-1 from the output S06 of the XOR3 202, the output S07 of the subtractor 204, and the S08 of the FF2 206 output. The amount of deviation is determined, and the delay 104 is controlled.

  The first comparator 301 detects a positive pulse from the output S07 of the subtractor 204 input via the LPF2 205 based on a positive threshold. Further, the output of the first comparator 301 is logically determined by the FF3 303 using the rise of the first dummy signal S02-1 as a trigger, and the determination result S09 is supplied to the determination / control circuit.

  The second comparator 302 detects a negative pulse in the output S07 of the subtractor 204 input via the LPF2 205 with a negative threshold. Further, the output of the second comparator 302 is logically determined by the FF4 304 using the rise of the first dummy signal S02-1 as a trigger, and the determination result S10 is supplied to the determination / control circuit.

  The FF5 305 makes a logical determination of the output of the FF2 206 using the rise of the signal S02-3 that gives a small delay to the first dummy signal S02-1 as a trigger by the delay t2 308, and determines the determination result S11. This is supplied to the determination / control circuit 306.

  The determination / control circuit 306 refers to the determination / control circuit truth table 307 shown in FIG. 21 and makes a logical determination from S09, S10, and S11. At the same time, the delay 104 is corrected for the delay amount determined by V_error output from the signal S06 according to the phase difference between the burst electric signal S01-1 and the first dummy signal S02-1.

As an example, when a correction amount Δt proportional to V_error is given, the correction amount Δt is
Δt = k × D × V_error (k: constant, D: determination / control circuit determination result)
It is calculated as follows.

In this example, S09 is “0”, S10 is “1”, and S11 is “1”. Therefore, referring to the determination / control circuit truth table 307, the determination result D is “−1”, and the delay of delay 104 The amount of change Δt of the quantity is
Δt = -k × V_error
It is calculated as follows.

  The delay 104 gives the change amount Δt of the delay amount calculated as described above to the first dummy signal S02-1.

  With the above operation, it is possible to detect a phase shift between the first dummy signal S02-1 and the burst electric signal S01-1, and to provide an appropriate delay for phase synchronization. The first dummy signal S02-1 Can be synchronized with the burst electric signal S01-1.

  According to this embodiment, similarly to the third and fourth embodiments, it is possible to automatically detect and correct the phase shift inside the burst optical signal receiving circuit.

  Also in this embodiment, it is possible to provide a dummy signal generator in the configuration of the second embodiment, that is, in the burst light receiving circuit 100-7.

<Sixth Embodiment>
(Configuration and operation)
A sixth embodiment of the present invention will be described with reference to FIGS. 24 and 25. FIG. FIG. 24 is a block diagram illustrating a configuration of a burst optical signal processing device 6000 according to the sixth embodiment. FIG. 25 is a flowchart showing the operation of the burst optical signal processing device 6000 of the sixth embodiment.

  The burst optical signal processing apparatus 6000 in FIG. 24 includes a conversion unit 601, a signal generation unit 602, an encoding unit 603, a reproduction unit 611, and a decoding unit 613.

  Details of each function will be described below with reference to FIG. First, the conversion unit 601 converts the burst optical signal received by the burst optical signal processing device 6000 into a burst electrical signal S61 (STP6002).

  The encoding unit 603 generates the encoded signal S62 from the burst electric signal S61 using the first electric pulse signal S64 (STP6003).

  Next, the reproducing unit 611 performs logical identification reproduction of the encoded signal S62 and reproduces the clock signal S64 (STP6004).

  The signal generator 602 generates and outputs a first electric pulse signal S64 and a second electric pulse signal S65 that are phase-synchronized with the clock signal S04 and have a lower code transition density than the burst electric signal S61 (STP6007).

  The decoding unit 613 decodes the encoded signal S62 using the second electric pulse signal (STP6008).

(effect)
According to the present embodiment, it is possible to automatically synchronize the burst electric signal and the dummy signal, and it is possible to avoid the baseline drift during the guard time without deterioration of the signal quality.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
Conversion means for converting the received burst optical signal into a burst electrical signal;
Encoding means for generating and outputting an encoded signal from the first electric pulse signal and the burst electric signal by exclusive OR operation;
Reproduction means for performing logical identification reproduction of the encoded signal and reproduction of a clock signal;
The first electric pulse signal and the second electric pulse signal that are phase-synchronized with the regenerated clock signal and have a code transition density lower than that of the burst electric signal, and at least a no-signal section of the burst electric signal First signal generating means for outputting the first electric pulse signal and the second electric pulse signal therein;
Decoding means for decoding the encoded signal using the second electric pulse signal;
A burst optical signal processing apparatus comprising:

(Appendix 2)
The burst optical signal processing device further includes:
Dividing means for dividing the regenerated clock signal to generate and output a divided clock, the first signal generating means includes a first electric pulse signal synchronized with the divided clock and a second The burst optical signal processing apparatus according to appendix 1, wherein the electrical pulse signal is generated and output.

(Appendix 3)
The burst optical signal receiver further comprises:
Detecting means for detecting a phase shift between the burst electric signal and the first electric pulse signal;
Delay control means for giving a delay based on the detected phase shift to the first electric pulse signal, and synchronizing the first electric pulse signal with the burst electric signal in the previous period;
The burst optical signal processing device according to appendix 1 or 2, further comprising:

(Appendix 4)
4. The burst optical signal processing apparatus according to appendix 3, wherein the detection unit detects the phase shift based on the burst electric signal and the first electric pulse signal.

(Appendix 5)
The delay control means further includes
Triggered by a code transition of the first electric pulse signal, first identifying means for performing logical identification of the burst electric signal, generating and outputting a first signal;
First delay means for generating and outputting a second signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first signal;
Second identification means for performing logical identification of the burst electric signal in response to a code transition of the signal given a delay of one bit, generating and outputting a third signal;
Second delay means for generating and outputting a fourth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the third signal;
Triggered by a code transition that gives a delay of 0.5 bits, third identification means for performing logical identification of the burst electric signal, generating and outputting a fifth signal;
From the second signal, the fourth signal, and the fifth signal, the direction of the phase shift of the first electric pulse signal with respect to the burst electric signal is detected, and the increase / decrease in the delay amount is determined. Delay amount determining means to
The burst optical signal processing device according to appendix 4, characterized by comprising:

(Appendix 6)
The burst optical receiver further includes:
Third delay means for giving a constant delay to the first electric pulse signal,
The burst optical signal processing apparatus according to appendix 3, wherein the detecting step detects the phase shift based on the encoded signal and the first electric pulse signal given the delay.

(Appendix 7)
The delay control means further includes
Triggered by a code transition of the first electrical pulse signal, a fourth identification means for performing logical identification of the encoded signal, generating and outputting a sixth signal;
Fourth delay means for generating and outputting a seventh signal obtained by giving a delay corresponding to one bit of the burst electric signal to the sixth output signal;
Fifth delay means for generating and outputting an eighth signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the eighth signal, a fifth identification means for performing logical identification of the encoded signal, generating and outputting a ninth signal;
Sixth delay means for generating and outputting a tenth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the tenth signal, a sixth identification means for performing logical identification of the encoded signal, generating and outputting an eleventh signal;
The burst optical signal processing device according to appendix 6, characterized by comprising:

(Appendix 8)
The burst optical signal according to appendix 3, wherein the detecting means detects the phase shift based on the encoded signal, the regenerated clock signal, and the first electric pulse signal. Processing equipment.

(Appendix 9)
The delay control means further includes
Seventh identification means for performing logical identification on the encoded signal using the clock signal reproduced by the reproduction means, and generating and outputting a twelfth signal;
Logical operation means for calculating an exclusive OR of the twelfth signal and the encoded signal, and generating and outputting a thirteenth signal;
Subtracting means for calculating a difference between the twelfth signal and the encoded signal to generate and output a fourteenth signal;
Averaging means for averaging the fourteenth signal and outputting the fifteenth signal;
A seventh delay means for adding a delay to the encoded signal to generate and output a sixteenth signal;
Triggered by a code transition of the sixteenth signal, an eighth identifying means for performing logical identification of the first electric pulse signal and generating and outputting a seventeenth signal;
An eighth delay means for delaying the first electrical pulse signal to generate and output an eighteenth signal;
Triggered by a code transition of the eighteenth signal, a ninth identification means for performing logical identification of the seventeenth signal and generating and outputting a nineteenth signal;
Determination of phase shift direction of the burst electric signal and the first electric pulse signal from the fourteenth signal and the nineteenth signal, and determination of an amount of phase shift from the thirteenth signal Means,
The burst optical signal processing device according to appendix 8, characterized by comprising:

(Appendix 10)
The processing apparatus further includes:
Parallel conversion means for converting the encoded signal reproduced by the reproduction means into parallel;
The burst optical signal processing apparatus according to any one of appendices 1 to 9, wherein the decoding unit decodes the parallel-converted encoded signal using the second electric pulse signal.

(Appendix 11)
A conversion step of converting the received burst optical signal into a burst electrical signal;
An encoding step of generating and outputting an encoded signal from the first electric pulse signal and the burst electric signal by exclusive OR operation;
A reproduction step for performing logical identification reproduction of the encoded signal and reproduction of a clock signal;
The first electric pulse signal and the second electric pulse signal that are phase-synchronized with the regenerated clock signal and have a code transition density lower than that of the burst electric signal, and at least a no-signal section of the burst electric signal A first signal generating step for outputting the first electric pulse signal and the second electric pulse signal;
A decoding step of decoding the encoded signal using the second electrical pulse signal;
A burst optical signal processing method comprising:

(Appendix 12)
The burst optical signal processing method further includes:
A frequency dividing step of dividing the regenerated clock signal to generate and output a divided clock;
12. The burst optical signal processing according to appendix 11, wherein the first signal generation step generates and outputs the first electric pulse signal and the second electric pulse signal synchronized with the divided clock. apparatus.

(Appendix 13)
A detection step of detecting a phase shift between the burst electric signal and the first electric pulse signal;
A delay control step of giving a delay based on the detected phase shift to the first electric pulse signal, and synchronizing the first electric pulse signal with the burst electric signal in the previous period;
The burst optical signal processing method according to appendix 11 or 12, further comprising:

(Appendix 14)
14. The burst optical signal processing method according to appendix 13, wherein the detecting step detects the phase shift based on the burst electric signal and the first electric pulse signal.

(Appendix 15)
The delay control step includes:
A first identification step of performing logical identification of the burst electric signal triggered by a code transition of the first electric pulse signal, and generating and outputting the first signal;
A first delay step of generating and outputting a second signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first signal;
A second identification step of performing logical identification of the burst electric signal in response to a code transition of the signal given a delay of one bit, generating and outputting a third signal;
A second delay step of generating and outputting a fourth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the third signal;
A third identification step of performing logical identification of the burst electric signal triggered by a code transition given a delay of 0.5 bits, and generating and outputting a fifth signal;
From the second signal, the fourth signal, and the fifth signal, the direction of the phase shift of the first electric pulse signal with respect to the burst electric signal is detected, and the increase / decrease in the delay amount is determined. A delay amount determination step to be performed;
The burst optical signal processing method according to appendix 14, further comprising:

(Appendix 16)
A third delay step of providing a constant delay to the first electrical pulse signal;
14. The burst optical signal processing method according to appendix 13, wherein the detecting step detects the phase shift based on the encoded signal and the first electric pulse signal given the delay.

(Appendix 17)
The delay control step includes:
Triggered by a code transition of the first electric pulse signal, a fourth identification step of performing logical identification of the encoded signal, generating and outputting a sixth signal;
A fourth delay step of generating and outputting a seventh signal obtained by giving a delay corresponding to one bit of the burst electric signal to the sixth signal;
A fifth delay step of generating and outputting an eighth signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the eighth signal, a fifth identification step of performing logical identification of the encoded signal and generating and outputting a ninth signal;
A sixth delay step of generating and outputting a tenth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the tenth output signal, a sixth identification step of performing logical identification of the encoded signal and generating and outputting an eleventh signal;
The burst optical signal processing method according to appendix 16, further comprising:

(Appendix 18)
14. The burst optical signal processing according to appendix 13, wherein the detecting step detects the phase shift based on the encoded signal, the regenerated clock signal, and the first electric pulse signal. Method.

(Appendix 19)
The delay control step further includes:
A seventh identification step of performing logical identification on the encoded signal using the regenerated clock signal and generating and outputting a twelfth signal;
A logical operation step of calculating an exclusive OR of the twelfth signal and the encoded signal, and generating and outputting a thirteenth signal;
Calculating a difference between the twelfth signal and the encoded signal to generate and output a fourteenth signal; and
An averaging step of averaging the fourteenth signal and outputting a fifteenth signal;
A seventh delay step of generating and outputting a sixteenth signal by giving a delay to the encoded signal;
Triggered by a code transition of the sixteenth signal, an eighth identification step of performing logical identification of the first electric pulse signal and generating and outputting a seventeenth signal;
An eighth delay step of generating and outputting an eighteenth signal by giving a delay to the first electric pulse signal;
Triggered by a code transition of the eighteenth signal, a ninth identification step of performing logical identification of the seventeenth signal and generating and outputting a nineteenth signal;
Determination of phase shift direction of the burst electric signal and the first electric pulse signal from the fourteenth signal and the nineteenth signal, and determination of an amount of phase shift from the thirteenth signal Steps,
The burst optical signal processing method according to appendix 18, characterized by comprising:

(Appendix 20)
The burst optical signal processing method further includes:
A parallel conversion step of parallel converting the encoded signal reproduced in the reproduction step;
The burst optical signal processing method according to any one of appendix 11 to appendix 19, wherein the decoding step decodes the parallel-converted encoded signal using the second electric pulse signal. .

  The present invention is applied to a burst optical receiver on a communication network.

100-1, 100-2, 100-3, 100-4, 100-5, 100-6, 100-7 Burst light receiving circuit 101 2R-Rx
102-1 and 102-2 Dummy signal generator 1
103 XOR1
104 delay 105, 106 delay control circuit 107 1 bit delay 1
110-1, 110-2, 110-3, 110-4, 110-7 Logic circuit 111 CDR
112 Dummy signal generator 2
113 XOR2
114 AC coupling C1
115 Divider 116 Serial / Parallel Converter 120 AC Coupling C0
201 flip-flop (FF) 1
202 XOR3
203 LPF1
204 Subtractor 205 LPF2
206 FF2
207 Code state determiner 208 Delay t1
301 First comparator 302 Second comparator 303 FF3
304 FF4
305 FF5
306 Judgment / Control Circuit 307 Judgment / Control Circuit Truth Table 308 Delay t2
401 FF6
402 1 bit delay 2
403 FF7
404 1-bit delay 3
405 Half-bit delay 1
406 FF8
407 Half-bit delay 2
408 judgment / control circuit 409 LPF
601 Conversion unit 602 Signal generation unit 603 Encoding unit 611 Playback unit 613 Decoding unit 801 ONU
802 Optical splitter 803 OLT
900 burst optical signal frame 901 preamble 902 burst delimiter 903 payload 1000-1, 1000-2, 1000-3, 1000-4, 1000-5, 1000-6, 1000-7, 6000 burst optical signal processing apparatus 1001 burst optical signal Receiver 1002 2R-Rx
1003 CDR
1004 AC coupling 1005 Optical fiber 1101 Optical burst signal waveform 1102 2R-Rx output waveform 1103 CDR input waveform S01-1, S61 Burst electrical signal S02-1 First dummy signal S02-2 Second dummy signal S02-3 Delay t2 First dummy signal S03, S62 Scramble signal S03-2 Branched scramble signal S03-3 Scramble signal given delay t1 S04-1, S63 Clock signal S04-2 Divided clock signal S05 FF1 201 Output signal S06 XOR3 202 output signal S07 subtractor 204 output signal S08 FF2 206 output signal S09 FF3 303 output signal S10 FF4 304 output signal S11 FF5 305 output signal S12 FF6 401 output signal S13 FF7 403 output Issue S14 FF8 405 output signal S15 judgment / control circuit 408 outputs the signal S64 a first electric pulse signal S65 a second electric pulse signal

Claims (10)

Conversion means for converting the received burst optical signal into a burst electrical signal;
Encoding means for generating and outputting an encoded signal from the first electric pulse signal and the burst electric signal by exclusive OR operation;
Reproduction means for performing logical identification reproduction of the encoded signal and reproduction of a clock signal;
The first electric pulse signal and the second electric pulse signal that are phase-synchronized with the regenerated clock signal and have a code transition density lower than that of the burst electric signal, and at least a no-signal section of the burst electric signal First signal generating means for outputting the first electric pulse signal and the second electric pulse signal therein;
Decoding means for decoding the encoded signal using the second electric pulse signal;
A burst optical signal processing apparatus comprising: The burst optical signal processing device further includes:
Dividing means for dividing the regenerated clock signal to generate and output a divided clock, the first signal generating means includes a first electric pulse signal synchronized with the divided clock and a second 2. The burst optical signal processing apparatus according to claim 1, wherein the electrical pulse signal is generated and output. The burst optical signal receiver further comprises:
Detecting means for detecting a phase shift between the burst electric signal and the first electric pulse signal;
Delay control means for giving a delay based on the detected phase shift to the first electric pulse signal, and synchronizing the first electric pulse signal with the burst electric signal in the previous period;
The burst optical signal processing device according to claim 1, further comprising:   4. The burst optical signal processing apparatus according to claim 3, wherein the detection unit detects the phase shift based on the burst electric signal and the first electric pulse signal. The delay control means further includes
Triggered by a code transition of the first electric pulse signal, first identifying means for performing logical identification of the burst electric signal, generating and outputting a first signal;
First delay means for generating and outputting a second signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first signal;
Second identification means for performing logical identification of the burst electric signal in response to a code transition of the signal given a delay of one bit, generating and outputting a third signal;
Second delay means for generating and outputting a fourth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the third signal;
Triggered by a code transition that gives a delay of 0.5 bits, third identification means for performing logical identification of the burst electric signal, generating and outputting a fifth signal;
From the second signal, the fourth signal, and the fifth signal, the direction of the phase shift of the first electric pulse signal with respect to the burst electric signal is detected, and the increase / decrease in the delay amount is determined. Delay amount determining means to
The burst optical signal processing device according to claim 4, comprising: The burst optical receiver further includes:
Third delay means for giving a constant delay to the first electric pulse signal,
4. The burst optical signal processing apparatus according to claim 3, wherein the detecting step detects the phase shift based on the encoded signal and the first electric pulse signal given the delay. . The delay control means further includes
Triggered by a code transition of the first electrical pulse signal, a fourth identification means for performing logical identification of the encoded signal, generating and outputting a sixth signal;
Fourth delay means for generating and outputting a seventh signal obtained by giving a delay corresponding to one bit of the burst electric signal to the sixth output signal;
Fifth delay means for generating and outputting an eighth signal obtained by giving a delay corresponding to one bit of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the eighth signal, a fifth identification means for performing logical identification of the encoded signal, generating and outputting a ninth signal;
Sixth delay means for generating and outputting a tenth signal obtained by giving a delay corresponding to 0.5 bits of the burst electric signal to the first electric pulse signal;
Triggered by a code transition of the tenth signal, a sixth identification means for performing logical identification of the encoded signal, generating and outputting an eleventh signal;
The burst optical signal processing device according to claim 6, further comprising:   4. The burst optical signal according to claim 3, wherein the detection unit detects the phase shift based on the encoded signal, the regenerated clock signal, and the first electric pulse signal. Processing equipment. The delay control means further includes
Seventh identification means for performing logical identification on the encoded signal using the clock signal reproduced by the reproduction means, and generating and outputting a twelfth signal;
Logical operation means for calculating an exclusive OR of the twelfth signal and the encoded signal, and generating and outputting a thirteenth signal;
Subtracting means for calculating a difference between the twelfth signal and the encoded signal to generate and output a fourteenth signal;
Averaging means for averaging the fourteenth signal and outputting the fifteenth signal;
A seventh delay means for adding a delay to the encoded signal to generate and output a sixteenth signal;
Triggered by a code transition of the sixteenth signal, an eighth identifying means for performing logical identification of the first electric pulse signal and generating and outputting a seventeenth signal;
An eighth delay means for delaying the first electrical pulse signal to generate and output an eighteenth signal;
Triggered by a code transition of the eighteenth signal, a ninth identification means for performing logical identification of the seventeenth signal and generating and outputting a nineteenth signal;
Determination of phase shift direction of the burst electric signal and the first electric pulse signal from the fourteenth signal and the nineteenth signal, and determination of an amount of phase shift from the thirteenth signal Means,
The burst optical signal processing device according to claim 8, comprising: A conversion step of converting the received burst optical signal into a burst electrical signal;
An encoding step of generating and outputting an encoded signal from the first electric pulse signal and the burst electric signal by exclusive OR operation;
A reproduction step for performing logical identification reproduction of the encoded signal and reproduction of a clock signal;
The first electric pulse signal and the second electric pulse signal that are phase-synchronized with the regenerated clock signal and have a code transition density lower than that of the burst electric signal, and at least a no-signal section of the burst electric signal A first signal generating step for outputting the first electric pulse signal and the second electric pulse signal;
A decoding step of decoding the encoded signal using the second electrical pulse signal;
A burst optical signal processing method comprising:

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