JP2011243736A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is highly integrated by laying out wiring layers in a multilayer manner in a region of a peripheral circuit region which is located nearby a boundary between a memory cell region and the peripheral circuit region, and a method of manufacturing the same.SOLUTION: The semiconductor device includes: local wiring 21 provided on an element layer 16 and in the boundary region 13 of the peripheral circuit region 12 which is located nearby the boundary between the memory cell region 11 and peripheral circuit region 12; a capacitor 31 which is provided on the element layer 16 and has a plurality of first and second lower electrodes 95, 96 and an upper electrode 98; a first support film 26 which couples the plurality of first lower electrodes 95 and is formed extending to a position where it faces a part of local wiring 19; and a first contact plug 37 which couples the upper electrode 98 and first upper wiring 42 provided above it to each other and is located above the local wiring 19 and reaching the first support film 26.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A DRAM (Dynamic Random Access Memory) memory cell includes a combination of a selection transistor and a capacitor.
The capacitor is configured to include a lower electrode, an upper electrode, and a capacitor insulating film (dielectric film) sandwiched between the lower electrode and the upper electrode.
Along with the miniaturization of memory cells due to the advancement of microfabrication technology, a reduction in the amount of charge stored in capacitors has become a problem. In order to solve this problem, a capacitor is provided in a hole (capacitor hole) formed in an insulating film.
In addition, with the progress of further miniaturization in recent years, the aspect ratio of the electrode of the capacitor has increased, making it difficult to process. Therefore, the hole (capacitor hole) for forming the electrode is formed twice in the depth direction. A technique for separately processing has been proposed (see, for example, Patent Document 1).
In addition, when using the outer wall of a high aspect ratio electrode as a capacitor, a support film (beam) is used to prevent the electrode from collapsing during the manufacturing process and shorting (collapse) with the adjacent electrode (lower electrode). A technique for providing and holding an electrode is known (see, for example, Patent Document 2).
A technique is also known in which a part of a wiring layer used when forming an electrode of a capacitor is used as a wiring layer (local wiring) in a region other than a memory cell (for example, see Patent Document 3).

JP 2004-039683 A JP 2008-283026 A JP 2008-251763 A

By the way, in order to give a predetermined potential to the upper electrode of the capacitor, it is necessary to connect to the upper wiring (metal wiring) disposed in the upper layer of the upper electrode through the first contact plug.
Further, the peripheral circuit transistor provided in the peripheral circuit region arranged outside the memory cell region needs to be connected to the upper wiring through the second contact plug.
At this time, in order to simplify the manufacturing process of the semiconductor device, the first contact hole in which the first contact plug is disposed and the second contact hole in which the second contact plug is disposed are simultaneously formed. Is required.
In recent years, a mainstream DRAM is provided with a capacitor at a higher position than a peripheral circuit transistor formed on a semiconductor substrate. Therefore, the second contact plug connected to the peripheral circuit transistor needs to be formed so that the bottom reaches a position deeper than the first contact plug connected to the upper electrode of the capacitor. That is, it is necessary to make the depth of the second contact hole deeper than the depth of the first contact hole.
However, if the first and second contact holes having different depths are formed at the same time, the etching for forming the second contact hole causes the first contact hole to pass through the upper electrode, and the upper electrode Etching proceeds to the lower layer region.
Therefore, there is a problem that a wiring layer for preventing a short circuit cannot be disposed immediately below the formation region of the first contact plug.
The existence of such a region where the wiring layer cannot be arranged has been an obstacle to high integration of semiconductor devices in order to reduce the degree of freedom of wiring layout.

  According to an aspect of the present invention, a semiconductor substrate, an element layer provided on a memory cell region and a peripheral circuit region of the semiconductor substrate, and on the element layer, wherein the peripheral circuit region includes: A local wiring provided in a region located near the boundary between the memory cell region and the peripheral circuit region, an interlayer insulating film formed on the element layer and covering the local wiring, and formed in the interlayer insulating film A plurality of first lower electrodes, a second lower electrode stacked on the first lower electrode, and an upper electrode that is a common electrode for the plurality of first and second lower electrodes A capacitor, a first support film that is in the interlayer insulating film, connects the plurality of first lower electrodes, and extends to a position facing a part of the local wiring; and the upper electrode The first top located above And a first contact plug that connects the upper electrode and the first upper wiring and is located above the local wiring and reaches the first support film. A semiconductor device is provided.

According to the semiconductor device of the present invention, the first support film connecting the plurality of first lower electrodes is extended to a position facing a part of the local wiring, whereby the upper electrode and the first upper wiring are formed. It is possible to dispose the local wiring below the first contact plug connecting the two and the lower wiring to the lower layer of the local wiring.
As a result, in the region located near the boundary between the memory cell region and the peripheral circuit region, the wiring layer can be laid out in multiple layers using the local wiring and the lower wiring arranged below it (wiring) Therefore, the degree of freedom of layer layout can be increased), so that the semiconductor device can be highly integrated.

1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view showing a schematic configuration of the semiconductor device shown in FIG. It is a top view for demonstrating the shape and positional relationship of a landing pad and local wiring shown in FIG. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 1) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 2) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. FIG. 8 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention; FIG. 8 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view (No. 4) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention; FIG. 8 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a plan view in which the structure shown in FIG. 7 is cut in the BB line direction. FIG. 8 is a view for illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view (part 5) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention; FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a plan view in which the structure shown in FIG. 9 is cut in the CC line direction. FIG. 8 is a diagram for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view (No. 6) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention; It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 7) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 8) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 9) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 10) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 11) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 12) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 13) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 14) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 15) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 16) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing (the 17) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the outline of the semiconductor device of a comparative example.

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the semiconductor device according to the embodiment of the present invention. The size, thickness, dimensions, and the like of each part shown in FIG. May be different.

(Embodiment)
FIG. 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. In FIG. 1, a DRAM (Dynamic Random Access Memory) is illustrated as an example of the semiconductor device 10 of the present embodiment. 1 is a diagram for explaining the positional relationship between the memory cell region 11, the peripheral circuit region 12, and the boundary region 13 which is a part of the peripheral circuit region 12. FIG. The illustration of the specific component which comprises the semiconductor device 10 of a form is abbreviate | omitted. In FIG. 1, the XX direction indicates the extending direction of the bit line 65 (not shown), and the YY direction indicates the extending direction of the gate electrode 82 intersecting the XX direction. .
Referring to FIG. 1, the DRAM element of the semiconductor device 10 of the present embodiment has a plurality of memory cell regions 11 and a peripheral circuit region 12 surrounding the plurality of memory cell regions 11.
The memory cell region 11 is a region surrounded by an outermost periphery by first and second guard walls 25 and 28 to be described later, and a plurality of memory cells including selection transistors 53 and 54 and a capacitor 31 to be described later are arranged in a predetermined manner. Arranged according to the rules.
The peripheral circuit region 12 is provided with a sense amplifier circuit (not shown), a drive circuit (not shown) for a word line (gate electrode 82), an input / output circuit (not shown) with the outside, and the like. .
In the following description, an area (a part of the peripheral circuit area 12 adjacent to the memory cell area 11) located near the boundary between the memory cell area 11 and the peripheral circuit area 12 in the peripheral circuit area 12 is referred to as the boundary area 13. Describe. The boundary area 13 is a name provided for convenience of explanation. The arrangement in FIG. 1 is an example, and the number of memory cell regions 11, the arrangement position of the memory cell regions 11, and the like are not limited to the layout in FIG.

FIG. 2 is a cross-sectional view showing a schematic configuration of the semiconductor device shown in FIG. 2, the same components as those of the semiconductor device 10 shown in FIG. 2 indicates a direction (depth direction of the first and second contact holes 34 to 36) orthogonal to the XX direction.
Referring to FIG. 2, the semiconductor device 10 of the present embodiment includes a semiconductor substrate 15, an element layer 16 formed on the surface 15 a side of the semiconductor substrate 15, landing pads 17 and 18, and local wirings 19 and 21. A stopper film 23, a first interlayer insulating film 24, a first guard wall 25, a first support film 26, a second interlayer insulating film 27, a second guard wall 28, 2 support film 29, capacitor 31, third interlayer insulating film 32, first contact hole 34, second contact holes 35 and 36, first contact plug 37, and second contact. Plugs 38 and 39, a first upper wiring 42, second upper wirings 43 and 44, and a protective film 45 are provided.
In the present embodiment, the interlayer insulating film formed on the element layer 16 includes the first interlayer insulating film 24, the second interlayer insulating film 27, and the third interlayer that are sequentially stacked on the element layer 16. The insulating film 32 is used.

The semiconductor substrate 15 includes a memory cell region 11 and a peripheral circuit region 12 (including a boundary region 13 that is a part of the peripheral circuit region 12 adjacent to the memory cell region 11). The semiconductor substrate 15 has a plate shape, and for example, a P-type silicon substrate can be used.
The element layer 16 is formed in the memory cell region 11 and the peripheral circuit region 12 of the semiconductor substrate 15. The element layer 16 includes an element isolation region 51, selection transistors 53 and 54, peripheral region transistor 55, silicon nitride film 57, interlayer insulating films 59 and 71, diffusion layer plugs 61 to 64, bit A line 65, lower wirings 66 to 68, and contact plugs 73 to 75 are provided.
The element isolation region 51 is provided in the semiconductor substrate 15 and partitions the active region. The selection transistors 53 and 54 are MOS (Metal Oxide Semiconductor) transistors, and are arranged adjacent to the active region formed in the memory cell region 11. The selection transistors 53 and 54 include a gate insulating film 81 formed on the surface 15 a of the semiconductor substrate 15, a gate electrode 82 provided on the gate insulating film 81, an impurity diffusion layer 83 formed on the semiconductor substrate 15, 84.
The impurity diffusion layer 83 is provided for each of the selection transistors 53 and 54. The impurity diffusion layer 83 functions as a drain region. The impurity diffusion layer 84 is a common impurity diffusion layer for the selection transistors 53 and 54. The impurity diffusion layer 84 functions as a source region.

The peripheral region transistor 55 is a MOS (Metal Oxide Semiconductor) transistor, and is disposed in an active region formed in the peripheral circuit region 12. The peripheral region transistor 55 includes a gate insulating film 81, a gate electrode 82, and impurity diffusion layers 86 and 87 formed in the semiconductor substrate 15.
The silicon nitride film 57 is provided so as to cover the upper surface and side surfaces of the gate electrode 82. The interlayer insulating film 59 is provided on the surface 15 a of the semiconductor substrate 15 so as to cover the element isolation region 51, the selection transistors 53 and 54, and the peripheral region transistor 55. As the interlayer insulating film 59, for example, a silicon oxide film can be used.

The diffusion layer plugs 61 to 64 are provided so as to penetrate the interlayer insulating film 59. The diffusion layer plug 61 is connected to the impurity diffusion layer 83 and the contact plug 73. The diffusion layer plug 62 is connected to the impurity diffusion layer 84 and the bit line 65. The diffusion layer plug 63 is connected to the impurity diffusion layer 86 and the lower wiring 67. The diffusion layer plug 64 is connected to the impurity diffusion layer 87 and the lower wiring 68.
The bit line 65 is provided on the interlayer insulating film 59 and extends in the direction intersecting with the gate electrode 82 (XX direction). In FIG. 2, only a part of the bit line 65 is schematically shown.
The lower wirings 66 to 68 are provided on the interlayer insulating film 59 formed in the peripheral circuit region 12. The lower wiring 66 is arranged in a region including the region below the first contact plug 37 in the boundary region 13.
The contact plugs 73 to 75 are provided so as to penetrate the interlayer insulating film 71. The contact plug 73 is connected to the landing pad 18 and the diffusion layer plug 61. The contact plug 74 is connected to the local wiring 19 and the lower wiring 66 or the local wiring 19 and the lower wiring 67. The contact plug 75 is connected to the local wiring 21 and the lower wiring 68.

FIG. 3 is a plan view for explaining the shape and positional relationship of the landing pad and the local wiring shown in FIG. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.
2 and 3, the landing pad 17 is provided on the interlayer insulating film 71 so as to surround the outermost periphery of the memory cell region 11. The landing pad 17 has a ring shape. The landing pad 17 surrounds the plurality of landing pads 18. The landing pad 17 is disposed on the outermost periphery of the memory cell region 11 located in the vicinity of the boundary region 13. The landing pad 17 is connected to the lower end of the first guard wall 25 having a frame shape.
A plurality of landing pads 18 are provided in the memory cell region 11 located inside the landing pad 17. The landing pad 18 is surrounded by the landing pad 17. The landing pad 18 may be, for example, a circular pad in plan view. The landing pad 18 is connected to the lower end of a first lower electrode 95, which will be described later, having a cylindrical shape. The landing pad 18 is a pad for optimizing the distance between the first lower electrodes 95 arranged at adjacent positions by adjusting the position of the first lower electrode 95 on the landing pad 18.

The local wirings 19 and 21 are provided on the interlayer insulating film 71 formed in the peripheral circuit region 12. The local wiring 19 is connected to the contact plug 74 and is electrically connected to the impurity diffusion layer 86 constituting the peripheral circuit transistor 55 via the contact plug 74.
A part of the local wiring 19 is arranged in the boundary region 13. The local wiring 19 (part of the local wiring 19) disposed in the boundary region 13 faces the lower end of the first contact plug 37 disposed above the local wiring 19.
The local wiring 21 is arranged at a position farther from the memory cell region 11 than the local wiring 19. The local wiring 21 is connected to the contact plug 75 and is electrically connected to the impurity diffusion layer 87 constituting the peripheral circuit transistor 55 via the contact plug 75.

Referring to FIG. 2, the stopper film 23 is provided on the interlayer insulating film 71 so as to cover the landing pads 17 and 18 and the local wirings 19 and 21. The stopper film 23 is etched to form a first guard wall groove 104 (see FIG. 7) for disposing the first guard wall 25 and a capacitor hole 103 (FIG. 7) for disposing the first lower electrode 95. Reference) is formed so as to penetrate. The stopper film 23 functions as a stopper for preventing the chemical solution from penetrating into the lower layer in the wet etching process for exposing the outer walls of the first and second lower electrodes 95 and 96 constituting the capacitor 31. .
The film also functions as a dry etching stopper when the first contact hole 34 and the second contact holes 35 and 36 are formed. As the stopper film 23, for example, a silicon nitride film can be used.
The first interlayer insulating film 24 is provided so as to cover the upper surface 23 a of the stopper film 23. For example, a silicon oxide film can be used as the first interlayer insulating film 24.
The first guard wall 25 passes through the first interlayer insulating film 24 formed on the landing pad 17, and the lower end is connected to the landing pad 17. The upper end of the first guard wall 25 protrudes from the upper surface 24 a of the first interlayer insulating film 24. The first guard wall 25 prevents the first interlayer insulating film 24 formed in the peripheral circuit region 12 from being etched by wet etching of the first interlayer insulating film 24 performed when the capacitor 31 is formed. It is a wall to do.

The first support film 26 is provided on the upper surface 24 a of the first interlayer insulating film 24. The first support film 26 is composed of a silicon nitride film which is an insulating film different from the silicon oxide film constituting the first to third interlayer insulating films 24, 27 and 32 (interlayer insulating films).
The first support film 26 extends from the memory cell region 11 (specifically, the formation region of the capacitor 31) to the first contact plug 37 formed in the boundary region 13, and a part of the local wiring 19. Is facing.
The first support film 26 formed in the memory cell region 11 is in contact with the outer peripheral side surfaces of the plurality of first lower electrodes 95 protruding from the upper surface 24 a of the first interlayer insulating film 24, thereby The lower electrode 95 is connected. The first support film 26 has a plurality of first lower electrodes 95 when the first interlayer insulating film 24 formed between the plurality of first lower electrodes 95 is etched after the plurality of first lower electrodes 95 are formed. This is a film for preventing the lower electrode 95 from collapsing and short-circuiting.
An opening 91 is formed in the first support film 26 formed in the memory cell region 11. The opening 91 is formed by wet etching in a first space 111 (see FIG. 5) for disposing the capacitor insulating film 97 and the upper electrode 98 constituting the capacitor 31 in the first interlayer insulating film 24 formed in the memory cell region 11. 16) is an introduction portion for introducing an etching solution necessary for forming the substrate.

The first support film 26 formed in the boundary region 13 is disposed so as to cover the formation region of the first contact plug 37 formed in the first contact hole 34. In other words, the first support film 26 is disposed so as to block the formation region of the first contact hole 34 before the first contact hole 34 is formed.
In this manner, the first support film 26 that connects the plurality of first lower electrodes 95 is arranged so as to extend to the boundary region 13 so as to block the region where the first contact plug 37 is formed, thereby performing etching. Thus, when the first contact hole 34 and the second contact holes 35 and 36 deeper than the first contact hole 34 are simultaneously formed, the first support film 26 is caused to function as an etching stopper. Therefore, it is possible to prevent the first contact hole 34 from penetrating the first interlayer insulating film 24 after the second contact holes 35 and 36 are formed.

As a result, the depth of the first contact plug 37 can be made not to penetrate the first interlayer insulating film 24, so that the first contact plug 37 is formed on the interlayer insulating film 71 facing the lower end of the first contact plug 37. It is possible to dispose the local wiring 19 in the lower layer 66 and 67 and connect the lower wirings 66 and 67 electrically connected to the local wiring 19 below the local wiring 19.
Therefore, in the boundary region 13, the wiring layer can be laid out in a multilayer manner using the local wiring 19, the contact plug 74 and the lower wirings 66 and 67 disposed below the local wiring 19 (wiring layer). Therefore, the semiconductor device 10 can be highly integrated.

The second interlayer insulating film 27 is stacked on the first interlayer insulating film 24 so as to cover the first support film 26 connecting the plurality of first lower electrodes 95. For example, a silicon oxide film can be used as the second interlayer insulating film 27.
The second guard wall 28 passes through the second interlayer insulating film 27 formed on the first guard wall 25, and the lower end is connected to the upper end of the first guard wall 25. The second guard wall 28 has a frame shape. The upper end of the second guard wall 28 protrudes from the upper surface 27 a of the second interlayer insulating film 27. The second guard wall 28 prevents the second interlayer insulating film 27 formed in the peripheral circuit region 12 from being etched by the etching of the second interlayer insulating film 27 performed when the capacitor 31 is formed. It is a wall for.

The second support film 29 is provided on the upper surface 27 a of the second interlayer insulating film 27. The second support film 29 is made of a silicon nitride film that is an insulating film different from the silicon oxide films that form the first to third interlayer insulating films 24, 27, and 32.
The second support film 29 extends from the memory cell region 11 (specifically, the region where the capacitor 31 is formed) to the boundary region 13.
The second support film 29 formed in the memory cell region 11 is in contact with the outer peripheral side surfaces of the plurality of second lower electrodes 96 protruding from the upper surface 27 a of the second interlayer insulating film 27, thereby The lower electrode 96 is connected. The second support film 29 has a plurality of second lower electrodes 96 when the second interlayer insulating film 27 formed between the plurality of second lower electrodes 96 is etched after the plurality of second lower electrodes 96 are formed. This is a film for preventing the lower electrode 96 from collapsing and short-circuiting.
An opening 92 is formed in the second support film 29 formed in the memory cell region 11. The opening 92 is formed by wet etching in a second space 112 (see FIG. 5) for disposing the capacitor insulating film 97 and the upper electrode 98 constituting the capacitor 31 in the second interlayer insulating film 27 formed in the memory cell region 11. 16) is an introduction portion for introducing an etching solution necessary for forming the substrate.

The second support film 29 formed in the boundary region 13 is disposed so as to cover the region where the first contact hole 34 is formed. In other words, the second support film 29 is disposed so as to block the formation region of the first contact hole 34 before the first contact hole 34 is formed. On the second support film 29 formed in the boundary region 13, an upper electrode 98 facing the second support film 29 is formed via a capacitive insulating film 97.
The second support film 29 formed in the boundary region 13 functions as a stopper for preventing the first contact hole 34 from reaching the local wiring 19 positioned below even when the first contact hole 34 penetrates the upper electrode 98. It is a film.

The capacitor 31 includes a plurality of first lower electrodes 95, a plurality of second lower electrodes 96, a capacitor insulating film 97, and an upper electrode 98.
The first lower electrode 95 passes through the first interlayer insulating film 24 formed on the landing pad 18, and the lower end is connected to the landing pad 18. Thus, the first lower electrode 95 is electrically connected to the impurity diffusion layer 83 constituting the selection transistors 53 and 54 via the landing pad 18.
The upper end of the first lower electrode 95 protrudes from the upper surface 24 a of the first interlayer insulating film 24. The outer peripheral side surfaces of the plurality of first lower electrodes 95 protruding from the upper surface 24 a of the first interlayer insulating film 24 are connected by the first support film 26.
The second lower electrode 96 passes through the second interlayer insulating film 27 formed on the first lower electrode 95, and the lower end is connected to the upper end of the first lower electrode 95. The upper end of the second lower electrode 96 protrudes from the upper surface 27 a of the second interlayer insulating film 27. The outer peripheral side surfaces of the plurality of second lower electrodes 96 protruding from the upper surface 27 a of the second interlayer insulating film 27 are connected by the second support film 29. The first and second lower electrodes 95 and 96 have a cylindrical shape (pedestal shape). As the first and second lower electrodes 95 and 96, for example, titanium nitride films can be used.

The capacitor insulating film 97 is formed on the upper end surface of the second lower electrode 96, the upper surface of the second support film 29, and the first and second interlayer insulating films 24 and 27 disposed in the memory cell region 11. The outer peripheral side surfaces of the plurality of first and second lower electrodes 95 and 96 exposed in the first and second spaces 111 and 112 (see FIG. 16), the upper surface 23a of the stopper film 23, and the first support film 26 It is provided so as to cover the upper and lower surfaces of the first support film 29 and the lower surface of the second support film 29.
Further, the capacitive insulating film 97 provided on the upper surface of the second support film 29 extends from the memory cell region 11 to the boundary region 13 corresponding to the formation region of the first contact hole 34. The capacitive insulating film 97 is sandwiched between the plurality of first and second lower electrodes 95 and 96 and the upper electrode 98.
As the capacitor insulating film 97, for example, a laminated film made of an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) can be used.
The upper electrode 98 embeds the first and second spaces 111 and 112 so as to cover the capacitive insulating film 97, and the capacitive insulating film formed on the upper end of the second lower electrode 96 and the second support film 29. 97 is provided so as to cover. The upper electrode 98 is a common electrode for the plurality of first and second lower electrodes 95 and 96. As the upper electrode 98, for example, a titanium nitride film can be used.

The third interlayer insulating film 32 is provided on the upper surface 27a of the second interlayer insulating film 27 so as to cover the second support film 29 on which the capacitor insulating film 97 and the upper electrode 98 are formed. For example, a silicon oxide film can be used as the third interlayer insulating film 32.
The first contact hole 34 is formed on the second and third interlayer insulating films 27 and 32, the first and second support films 26 and 29, and the second support film 29 disposed in the boundary region 13. The capacitor insulating film 97 and the upper electrode 98 are formed so as to penetrate, and reach the first support film 26. The upper electrode 98 is exposed on the side surface of the first contact hole 34.
The bottom surface 34 a of the first contact hole 34 is disposed above the stopper film 23 formed in the local wiring 19. The depth of the first contact hole 34 is configured to be shallower than the second contact holes 35, 36 that reach the landing pads 19, 21.

The second contact hole 35 is formed so as to penetrate the stopper film 23 and the first to third interlayer insulating films 24, 27 and 32 formed on the local wiring 19. The second contact hole 35 exposes the upper surface 19 a of the local wiring 19.
The second contact hole 36 is formed so as to penetrate the stopper film 23 and the first to third interlayer insulating films 24, 27 and 32 formed on the local wiring 19. The bottom surface of the second contact hole 36 reaches the local wiring 19, and the upper surface 21 a of the local wiring 21 is exposed.

The first contact plug 37 is provided so as to fill the first contact hole 34 and penetrates the upper electrode 98 and the second support film 29. The first contact plug 37 reaches the first support film 26.
The outer peripheral side surface of the first contact plug 37 is connected to the upper electrode 98. The upper end of the first contact plug 37 is connected to the first upper wiring 42. Thereby, the first contact plug 37 electrically connects (links) the first upper wiring 42 and the upper electrode 98. The lower end of the first contact plug 37 is opposed to the local wiring 19 formed in the boundary region 13.
The second contact plug 38 is provided so as to fill the second contact hole 35. The upper end of the second contact plug 38 is connected to the second upper wiring 43, and the lower end of the second contact plug 38 is connected to the local wiring 19. Thus, the second contact plug 38 electrically connects the local wiring 19 and the second upper wiring 43.
The second contact plug 39 is provided so as to fill the second contact hole 36. The upper end of the second contact plug 39 is connected to the second upper wiring 44, and the lower end of the second contact plug 39 is connected to the local wiring 21. Thereby, the second contact plug 39 electrically connects the local wiring 21 and the second upper wiring 44.

The first upper wiring 42 is a wiring located in an upper layer than the upper electrode 98. The first upper wiring 42 is formed on the upper surface 32 a of the third interlayer insulating film 32 and is connected to the upper end of the first contact plug 37. The first upper wiring 42 is electrically connected to the upper electrode 98 of the capacitor 31 through the first contact plug 37. The first upper wiring 42 is a wiring for supplying a predetermined potential to the upper electrode 98 of the capacitor 31.
The second upper wirings 43 and 44 are provided on the upper surface 32 a of the third interlayer insulating film 32 formed in the peripheral circuit region 12. The second upper wiring 43 is connected to the upper end of the second contact plug 38. The second upper wiring 43 is electrically connected to the impurity diffusion layer 86 constituting the peripheral circuit transistor 55 via the second contact plug 38.
The second upper wiring 44 is connected to the upper end of the second contact plug 39. The second upper wiring 44 is electrically connected to the impurity diffusion layer 87 constituting the peripheral circuit transistor 55 via the second contact plug 39.
The protective film 45 is provided on the upper surface 32 a of the third interlayer insulating film 32 so as to cover the first and second upper wirings 42 to 44.

According to the semiconductor device of the present embodiment, the first support film 26 connecting the plurality of first lower electrodes 95 is extended to a position facing a part of the local wiring 19, thereby The local wiring 19 can be arranged below the contact plug 37 and the lower wirings 66 and 67 can be arranged below the local wiring 19.
Thereby, in the boundary region 13 located near the boundary between the memory cell region 11 and the peripheral circuit region 12, the wiring layers can be laid out in a multilayer manner using the local wiring 19 and the lower wirings 66 and 67 ( The degree of freedom of the layout of the wiring layer can be increased), so that the semiconductor device 10 can be highly integrated.

4 to 22 are views for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention. 4 to 7, 9, and 11 to 22 are views showing a manufacturing process of the semiconductor device according to the embodiment of the present invention, and FIG. 8 is a cross-sectional view of the structure shown in FIG. FIG. 10 is a plan view obtained by cutting the structure shown in FIG. 9 in the CC line direction. 4 to 7, 9, and 11 to 22 are cross-sectional views corresponding to a cut surface of the semiconductor device 10 of the present embodiment shown in FIG. 2. 4 to 22, the same components as those of the semiconductor device 10 shown in FIG.
In the present embodiment, the following description will be given by taking as an example the case where N-type MOS transistors are formed as the selection transistors 53 and 54 and the peripheral circuit transistor 55.

With reference to FIGS. 4-22, the manufacturing method of the semiconductor device 10 of this Embodiment is demonstrated. First, in the step shown in FIG. 4, the element layer 16 is formed on the surface 15 a side of the semiconductor substrate 15. Specifically, for example, a P-type silicon substrate is prepared as the semiconductor substrate 15, and the active region is partitioned by forming the element isolation region 51 in the semiconductor substrate 15. The element isolation region 51 is formed by embedding an insulating film such as a silicon oxide film in a groove (not shown) formed in the semiconductor substrate 15 using an STI (Shallow Trench Isolation) method.
Next, by a well-known method, the selection transistors 53 and 54 including the gate insulating film 81, the gate electrode 82, and the impurity diffusion layers 83 and 84 into which N-type impurities are implanted, the gate insulating film 81, the gate electrode 82, and the N A peripheral region transistor 55 having impurity diffusion layers 86 and 87 implanted with a type impurity is formed.

Next, a silicon nitride film 57 is formed so as to cover the upper surface and side surfaces of the gate electrode 82. As the silicon nitride film 57, for example, a Si ₃ N ₄ film can be used.
Next, a silicon oxide film is formed on the surface 15 a of the semiconductor substrate 15 as an interlayer insulating film 59 that covers the silicon nitride film 57. Next, a through hole (not shown) penetrating the interlayer insulating film 59 is formed, and then the contact plugs 61 to 63 are formed simultaneously by filling the through hole with a conductive film.
Next, for example, a tungsten film is formed on the interlayer insulating film 59 formed in the memory cell region 11 and the peripheral circuit region 12, and the tungsten film is patterned to form the bit line 65 in the memory cell region 11. At the same time, lower wirings 66 to 68 are formed in the peripheral circuit region 12. At this time, the lower wiring 67 is formed so as to be electrically connected to the impurity diffusion layer 86 via the contact plug 63, and the lower wiring 68 is electrically connected to the impurity diffusion layer 87 via the contact plug 64. It is formed so as to be connected to.

Next, a silicon oxide film is formed on the interlayer insulating film 59 to form an interlayer insulating film 71 that covers the bit line 65 and the lower wirings 66 to 68.
Next, a plurality of contact holes (not shown) are formed in the interlayer insulating film 71 formed in the memory cell region 11 and the peripheral circuit region 12, and then a titanium (Ti) film and a nitride are formed in the contact holes. A titanium (TiN) film and a tungsten (W) film are sequentially embedded, and then an extra titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film formed on the upper surface of the interlayer insulating film 71. As a result, the contact plug 73 is formed in the memory cell region 11 and the contact plugs 74 and 75 are formed in the peripheral circuit region 12.

Next, in the process shown in FIG. 5, for example, a tungsten nitride film (not shown) is formed on the upper surface of the structure shown in FIG. 4 as a conductive film that becomes a base material of the landing pads 17 and 18 and the local wirings 19 and 21. Then, a tungsten film (not shown) is sequentially formed to form a laminated film, and then the laminated film is patterned by a photolithography technique and a dry etching technique, thereby landing pads 17 and 18 in the memory cell region 11. And the local wirings 19 and 21 are formed in the boundary region 13 and the peripheral circuit region 12.
As described above, when the landing pads 17 and 18 and the local wirings 19 and 21 are formed at the same time, the step of forming the landing pads 17 and 18 and the step of forming the local wirings 19 and 21 are separately provided. As compared with the above, the manufacturing process of the semiconductor device 10 can be simplified.

Next, in the process shown in FIG. 6, a stopper film 23 that covers the landing pads 17 and 18 and the local wirings 19 and 21 is formed on the interlayer insulating film 71. Specifically, a silicon nitride film having a thickness of 0.1 μm is formed as the stopper film 23.
Next, a silicon oxide film having a thickness of 1 μm, for example, is formed on the stopper film 23 as the first interlayer insulating film 24. Next, a silicon nitride film 101 serving as a base material of the first support film 26 is formed on the first interlayer insulating film 24 by a CVD (Chemical Vapor Deposition) method.

Next, in the process shown in FIG. 7, the capacitor hole 103 and the first guard wall groove 104 are simultaneously formed by etching the first interlayer insulating film 24 and the silicon nitride film 101 by the photolithography technique and the dry etching technique. Form.
At this time, the capacitor hole 103 is formed so as to expose the upper surface of the landing pad 18 having a circular shape, and the first guard wall groove 104 is exposed so as to expose the upper surface of the landing pad 17 having a ring shape. To form. FIG. 8 is a plan view of the structure shown in FIG. 7 cut in the BB line direction.

Next, in the process shown in FIG. 9, titanium nitride is used as a conductive film that becomes a base material for the first guard wall 25 and the first lower electrode 95 in the capacitor hole 103 and the first guard wall groove 104 by CVD. Embed the membrane. Next, the excess titanium nitride film formed on the silicon nitride film 101 is polished and removed by CMP, thereby forming the first guard wall 25 and the plurality of first lower electrodes 95. FIG. 10 is a plan view of the structure shown in FIG. 9 cut along the line CC.
As described above, the first lower electrode 95 constituting the capacitor 31 is formed of a titanium nitride film, which is advantageous in terms of work function as compared with the case where the first lower electrode 95 is formed of a tungsten film. In addition, the leakage current of the capacitor 31 can be reduced.
Therefore, when a DRAM is used as the semiconductor device 10, a high-performance DRAM can be formed.

Next, in the process shown in FIG. 11, the silicon nitride film 101 is patterned by photolithography technology and dry etching technology to extend from the memory cell region 11 (specifically, the formation region of the capacitor 31) to the boundary region 13. A first support film 26 having an opening 91 is formed so as to face a part of the local wiring 19 (a part of the local wiring 19 formed in the boundary region 13). As a result, the plurality of lower electrodes 95 and the first guard wall 25 are connected by the first support film 26. Further, the first support film 26 is formed so as to block the formation region of the first contact hole 34.
In this way, the first support film 26 connecting the plurality of first lower electrodes 95 and the first guard wall 25 is extended to the boundary region 13 so as to block the formation region of the first contact hole 34. As a result, the first support film 26 formed in the boundary region 13 can function as an etching stopper when forming the first contact hole 34, and thus the first and second contact holes 34- When forming 36 at the same time, the first contact hole 34 can be prevented from penetrating the first interlayer insulating film 24.

Next, in the step shown in FIG. 12, a second interlayer insulating film 27 that covers the first support film 26 is formed on the upper surface 24a of the first interlayer insulating film 24 by the CVD method. Specifically, for example, a second interlayer insulating film 27 is formed by forming a silicon oxide film having a thickness of 1 μm.
Next, a silicon nitride film 106 (for example, a thickness of 0.1 μm) serving as a base material of the second support film 29 is formed on the upper surface 27a of the second interlayer insulating film 27 by CVD.

Next, in the step shown in FIG. 13, the capacitor hole 107 and the second guard wall groove 108 are simultaneously formed by etching the second interlayer insulating film 27 and the silicon nitride film 106 by the photolithography technique and the dry etching technique. Form.
At this time, the capacitor hole 107 is formed so as to expose the upper surface of the first lower electrode 95 having a cylindrical shape, and the second guard wall groove 108 is formed in the first guard wall 25 having a ring shape. The upper surface is formed so as to be exposed. The second guard wall groove 108 is formed so as to surround the outermost periphery of the memory cell region 11.

Next, in the process shown in FIG. 14, titanium nitride is used as a conductive film to be a base material for the second guard wall 28 and the second lower electrode 96 in the capacitor hole 107 and the second guard wall groove 108 by the CVD method. Embed the membrane. Next, the second guard wall 28 and the plurality of second lower electrodes 96 are formed by polishing and removing the excess titanium nitride film formed on the silicon nitride film 106 by CMP.
The first and second lower electrodes 95 and 96 only need to be in contact with each other. As shown in FIG. 14, the center position is slightly shifted due to misalignment. The lower electrode 96 may be connected. In this regard, the same applies to the first and second guard walls 25 and 28.

Next, in the step shown in FIG. 15, the second interlayer insulating film 27 is removed by removing a part of the silicon nitride film 106 formed in the memory cell region 11 shown in FIG. 14 by the photolithography technique and the dry etching technique. A second support film 29 having an opening 92 that exposes is formed.
At this time, in the peripheral circuit region 12 including the boundary region 13, the silicon nitride film 106 is left without being patterned. Therefore, as shown in FIG. 15, the second support film 29 at this stage extends to the peripheral circuit region 12 other than the boundary region 13.
In the step shown in FIG. 17 described later, a part of the second support film 29 shown in FIG. 15 (the second support film 29 formed in the peripheral circuit region 12 excluding the boundary region 13) is removed. Thus, the second support film 29 shown in FIG. 2 is formed.

Next, in the step shown in FIG. 16, a wet etching solution (for example, hydrofluoric acid) is applied to the first and second interlayer insulating films 24 and 27 formed in the memory cell region 11 through the openings 92 and 91. (HF)) is supplied, and the first interlayer insulating film 24 surrounded by the first guard wall 25 and the second interlayer insulating film 27 surrounded by the second guard wall 28 are etched. The first space 111 is formed in the first interlayer insulating film 24 formed in the memory cell region 11 and the second space 112 is formed in the second interlayer insulating film 27 formed in the memory cell region 11. To do.
The first space 111 is formed so as to expose the upper surface 23 a of the stopper film 23, the lower surface of the first support film 26, the outer peripheral side surfaces of the plurality of first lower electrodes 95, and the inner wall of the first guard wall 25. To do. The second space 112 includes the upper surface 26 a of the first support film 26, the lower surface of the second support film 28, the outer peripheral side surfaces of the plurality of second lower electrodes 96, and the inner wall of the second guard wall 28. Form to be exposed.
At this time, the stopper film 23 prevents the wet etching solution from penetrating into the lower layer of the memory cell region 11, so that the already formed transistors and the like are not damaged.

Next, in the step shown in FIG. 17, a capacitive insulating film 97 covering the first and second spaces 111 and 112 is formed from the upper surface side of the structure shown in FIG. 16 by an ALD (Atomic Layer Deposition) method. Then, the upper electrode 98 filling the first and second spaces 111 and 112 in which the capacitive insulating film 97 is formed is formed by CVD.
At this time, the capacitor insulating film 97 and the upper electrode 98 are also formed on the second support film 29 formed on the upper surface 32 a of the third interlayer insulating film 32.
As the capacitor insulating film 97, for example, a laminated film made of an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) can be used. As the upper electrode 98, for example, a titanium nitride film can be used.

Next, the upper electrode 98, the capacitor insulating film 97, and the second support film 29 formed in the peripheral circuit region 12 excluding the boundary region 13 are removed by etching, whereby the second support film 29 shown in FIG. In addition, the upper electrode 98, the capacitor insulating film 97, and the second support film 29 are made not to interfere with the formation of the second contact holes 35 and 36.
At this time, the etched upper electrode 98, capacitive insulating film 97, and second support film 29 are opposed to a part of the local wiring 19 (a part of the local wiring 19 formed in the boundary region 13). The above etching is performed.
Next, a third interlayer insulating film 32 is formed by CVD to cover the second support film 29 on which the upper electrode 98 and the capacitor insulating film 97 are formed. For example, a silicon oxide film is used as the third interlayer insulating film 32.

Next, in a step shown in FIG. 18, a resist film 115 having openings 115a, 115b, and 115c is formed on the third interlayer insulating film 32 by photolithography.
At this time, the opening 115 a is formed so as to expose the upper surface 32 a of the third interlayer insulating film 32 corresponding to the formation region of the first contact hole 34, and the opening 115 b is formed in the second contact hole 35. It forms so that the upper surface 32a of the 3rd interlayer insulation film 32 corresponding to a formation area may be exposed. The opening 115 c is formed so as to expose the upper surface 32 a of the third interlayer insulating film 32 corresponding to the formation region of the second contact hole 36.

Next, the opening 116 serving as a part of the first contact hole 34 and the opening 117 serving as a part of the second contact hole 35 are performed by anisotropic etching (for example, dry etching) using the resist film 115 as a mask. , And the opening 118 which becomes a part of the second contact hole 36 is simultaneously formed (first step).
At this time, an etching condition with a small difference in etching rate between the second and third interlayer insulating films 27 and 32, the second support film 29, the capacitor insulating film 97, and the upper electrode 98 and with good detachability is used. The openings 116 to 118 are formed.
The opening 116 penetrates the third interlayer insulating film 32, the second support film 29, the capacitor insulating film 97, and the upper electrode 98, and the bottom surface 116 a of the opening 116 is in the second interlayer insulating film 27. It forms so that it may be arrange | positioned. As a result, the upper electrode 98 is exposed from the side surface of the opening 116.
The etching time is controlled so that the openings 117 and 118 penetrate the second and third interlayer insulating films 27 and 32, and the bottom surfaces thereof are 117 a and 118 a disposed in the first interlayer insulating film 24. To form.

Next, in the step shown in FIG. 19, conditions for selectively etching the second and third interlayer insulating films 27 and 32 that are silicon oxide films (in other words, the first support film 26 that is a silicon nitride film and the stopper). The film is subjected to anisotropic etching (for example, dry etching) through the resist film 115 using a condition in which the film 23 is hardly etched, whereby the opening 121 that becomes a part of the first contact hole 34, the second The opening 122 which becomes a part of the contact hole 35 and the opening 123 which becomes a part of the second contact hole 36 are simultaneously formed (second step).
At this time, the opening 121 is formed so as to form the upper surface 26 a of the first support film 26, and the openings 122 and 123 are formed so as to expose the upper surface 23 a of the stopper film 23.
In the second step, since the etching conditions under which the silicon oxide film is selectively etched with respect to the silicon nitride film are used, the first support film 26 is used as a stopper film when the opening 121 is formed. In addition, the stopper film 23 can be used as a stopper film when the openings 122 and 123 are formed.
Therefore, the opening 121 does not penetrate the first support film 26, and the openings 122 and 123 do not penetrate the stopper film 23.

Next, in the process shown in FIG. 20, a condition is used in which the first support film 26 and the stopper film 23 made of a silicon nitride film are selectively etched with respect to the first interlayer insulating film 24 made of a silicon oxide film. Then, by performing anisotropic etching (for example, dry etching) through the resist film 115, the first contact that penetrates the first support film 26 and has a depth at which the bottom surface 34a does not reach the local wiring 19 is obtained. The second contact hole 35 that penetrates the hole 34 and the stopper film 23 and exposes the upper surface 19a of the local wiring 19 (which reaches the local wiring 19) and the stopper film 23 and the upper surface 21a of the local wiring 21 An exposed second contact hole 36 (which reaches the local wiring 21) is formed at the same time (third step).
At this time, in the third step, the etching condition under which the etching rate of the silicon oxide film is low is used, and therefore the first interlayer insulating film 24 corresponding to the formation region of the first contact hole 34 is hardly etched. Therefore, at the stage where the second contact holes 35, 36 deeper than the first contact hole 34 are formed, the bottom surface 34 a of the first contact hole 34 is formed on the local wiring 19 arranged in the boundary region 13. Never reach.
Therefore, the local wiring 19 can be formed on the interlayer insulating film 71 corresponding to the boundary region 13. As a result, in the boundary region 13, the local wiring 19 and the lower wirings 66 and 67 disposed below the local wiring 19 can be used to lay out the wiring layers in a multilayer manner (the degree of freedom of the wiring layer layout is increased). Therefore, the semiconductor device 10 can be highly integrated.

Next, in the step shown in FIG. 21, a titanium nitride film and a tungsten film are sequentially formed so as to fill the first and second contact holes 34, 35, and 36 by the CVD method.
Next, the first and second contact plugs 37 to 39 are formed by polishing and removing the excess titanium nitride film and tungsten film formed on the upper surface 32a of the third interlayer insulating film 32 by CMP.
The first contact plug 37 formed in the first contact hole 34 is electrically connected to the upper electrode 98. In addition, the second contact plug 38 formed in the second contact hole 35 is electrically connected to the local wiring 19, and the second contact plug 39 formed in the second contact hole 36 is connected to the local wiring 19. 21 is electrically connected.
In addition, by using a tungsten film as a film constituting the first and second contact plugs 37 to 39, compared to the case where the first and second contact plugs 37 to 39 are constituted only by a titanium nitride film. The resistance values of the first and second contact plugs 37 to 39 can be lowered.

Next, in the step shown in FIG. 22, the first upper wiring 42 connected to the upper end of the first contact plug 37 and the upper end of the second contact plug 38 are formed on the upper surface 32 a of the third interlayer insulating film 32. The second upper wiring 43 to be connected and the second upper wiring 44 connected to the upper end of the second contact plug 39 are formed simultaneously. As a material of the first and second upper wirings 42 to 44, for example, aluminum (Al), copper (Cu), or the like can be used.
Next, a protective film 45 is formed on the upper surface 32 a of the third interlayer insulating film 32 so as to cover the first and second upper wirings 42 to 44. Thereby, the semiconductor device 10 of the present embodiment is manufactured.

According to the manufacturing method of the semiconductor device of the present embodiment, the difference in etching rate between the second and third interlayer insulating films 27 and 32, the second support film 29, the capacitive insulating film 97, and the upper electrode 98 is small. In addition, the opening 116 (a part of the first contact hole 34) in which the bottom surface 116a is disposed in the second interlayer insulating film 27 and the bottom surfaces 117a and 118a are the first by using etching conditions having good detachability. The openings 117 and 118 (part of the second contact holes 35 and 36) disposed in the interlayer insulating film 24 are formed, and then the silicon nitride film constituting the first support film 26 and the stopper film 23 On the other hand, the opening 1 that exposes the upper surface 26a of the first support film 26 using etching conditions under which the silicon oxide films constituting the first and second interlayer insulating films 24 and 27 are selectively etched. 1 (a part of the first contact hole 34) and openings 122 and 123 (a part of the second contact holes 35 and 36) exposing the upper surface 23a of the stopper film 23 are formed, and then the silicon oxide film The first and second layers having different depths are used under the condition that the first support film 26 and the stopper film 23 made of a silicon nitride film are selectively etched with respect to the first interlayer insulating film 24 made of By forming the contact holes 34 to 36, the bottom surface 34a of the first contact hole 34 formed in the boundary region 13 penetrates the first support film 26, and the first interlayer insulating film 24 is slightly etched. In order to stop, the local wiring 19 can be formed in the boundary region 13 facing the bottom surface 34 a of the first contact hole 34.
As a result, in the boundary region 13, the local wiring 19 and the lower wirings 66 and 67 disposed below the local wiring 19 can be used to lay out the wiring layers in a multilayer manner (the degree of freedom of the wiring layer layout is increased). Therefore, the semiconductor device 10 can be highly integrated.

FIG. 23 is a cross-sectional view schematically showing a semiconductor device of a comparative example. 23 is a cross-sectional view corresponding to a cut surface of the semiconductor device 10 of the present embodiment shown in FIG. In FIG. 23, the same components as those of the semiconductor device 10 of the present embodiment shown in FIG.
Here, with reference to FIG. 23, a semiconductor device 130 of a comparative example that does not include the first support film 26 described in the present embodiment will be described.
As shown in FIG. 23, the semiconductor device 130 of the comparative example does not have the first support film 26 that functions as a stopper film when the first contact hole 34 is formed by etching. Therefore, in the case where the first and second contact holes 34 to 36 having different depths are formed at the same time, overetching for reliably connecting the second contact holes 35 and 36 to the local wirings 19 and 21 is performed. As a result, the etching of the first contact hole 34 also proceeds, and the bottom surface 34 a reaches the local wiring 19. As a result, a short circuit between the first contact plug 37 and the local wiring 19 occurs.
Therefore, in the semiconductor device 130 of the comparative example shown in FIG. 23, the local wiring 19 cannot be formed on the interlayer insulating film 71 facing the lower end of the first contact plug 37.

The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.
In this embodiment, a DRAM is taken as an example of a semiconductor device. However, the present invention can be applied to a mixed LSI (Large Scale Integration) including a DRAM and a logic element on one semiconductor chip. It is.
In the present embodiment, the case where cylindrical electrodes are used as the first and second lower electrodes 95 and 96 has been described as an example. However, for example, the first lower electrode 95 is a column type (pedestal). Type), and the second lower electrode 96 may be a crown type.

  The present invention is applicable to a semiconductor device and a manufacturing method thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Memory cell area | region, 12 ... Peripheral circuit area | region, 13 ... Boundary area | region, 15 ... Semiconductor substrate, 15a ... Surface, 16 ... Element layer, 17, 18 ... Landing pad, 19, 21 ... Local wiring, 19a, 21a, 23a, 24a, 26a, 27a, 32a ... upper surface, 23 ... stopper film, 24 ... first interlayer insulating film, 25 ... first guard wall, 26 ... first support film, 27 ... second 28 ... second guard wall, 29 ... second support film, 31 ... capacitor, 32 ... third interlayer insulation film, 34 ... first contact hole, 34a, 116a, 117a, 118a ... Bottom surface, 35, 36 ... second contact hole, 37 ... first contact plug, 38, 39 ... second contact plug, 42 ... first upper wiring, 43, 44 ... second upper wiring, 45 ... protection , 51 ... element isolation region, 53 and 54 ... selection transistor, 55 ... peripheral region transistor, 57 ... silicon nitride film, 59, 71 ... interlayer insulating film, 61 to 64 ... diffusion layer plug, 65 ... bit line, 66-68 ... lower wiring, 73-75 ... contact plug, 81 ... gate insulating film, 82 ... gate electrode, 83, 84, 86, 87 ... impurity diffusion layer, 91, 92, 115a, 115b, 115c, 116-118 , 121 to 123 ... opening, 95 ... first lower electrode, 96 ... second lower electrode, 97 ... capacitive insulating film, 98 ... upper electrode, 101, 106 ... silicon nitride film, 103, 107 ... capacitor hole, DESCRIPTION OF SYMBOLS 104 ... 1st guard wall groove | channel, 108 ... 2nd guard wall groove | channel, 111 ... 1st space, 112 ... 2nd space, 115 ... Resist film

Claims (14)

A semiconductor substrate;
An element layer provided on the memory cell region and the peripheral circuit region of the semiconductor substrate;
On the element layer, among the peripheral circuit region, local wiring provided in a region located near the boundary between the memory cell region and the peripheral circuit region;
An interlayer insulating film formed on the element layer and covering the local wiring;
Common to a plurality of first lower electrodes, a second lower electrode stacked on the first lower electrode, and a plurality of the first and second lower electrodes formed in the interlayer insulating film A capacitor having an upper electrode which is an electrode of
A first support film that is in the interlayer insulating film, connects the plurality of first lower electrodes, and extends to a position facing a part of the local wiring;
A first upper wiring located above the upper electrode;
A first contact plug that connects the upper electrode and the first upper wiring, is located above the local wiring, and reaches the first support film;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising a stopper film that covers the local wiring.   The semiconductor device according to claim 2, wherein the first support film and the stopper film are silicon nitride films. A second upper wiring located above the interlayer insulating film;
4. The semiconductor device according to claim 2, further comprising a second contact plug that is located in the interlayer insulating film and connects the second upper wiring and the local wiring.   5. The device according to claim 1, wherein the first contact plug penetrates the first support film, and a bottom surface of the first contact plug is disposed above the local wiring. A semiconductor device according to claim 1.   6. The semiconductor device according to claim 1, wherein a landing pad connected to the first lower electrode is provided on the element layer formed in the memory cell region. .   7. The device element according to claim 1, wherein the element layer includes a lower wiring electrically connected to the local wiring in the peripheral circuit region including a region below the first contact plug. The semiconductor device according to 1. A plurality of the second lower electrodes are connected, and a second support film is provided so that the upper electrode is opposed to the capacitor via a capacitive insulating film, and the second support film is opposed to the local wiring. The support film is extended and arranged,
The semiconductor device according to claim 1, wherein the first contact plug is disposed so as to penetrate the upper electrode and the second support film. Forming an element layer in a memory cell region and a peripheral circuit region on a semiconductor substrate;
Forming a local wiring in a region on the element layer and located near a boundary between the memory cell region and the peripheral circuit region in the peripheral circuit region;
Forming an interlayer insulating film covering the local wiring on the element layer;
Forming a plurality of first lower electrodes to be capacitors in the interlayer insulating film formed in the memory cell region;
Forming a first support film connecting the plurality of first lower electrodes in the interlayer insulating film and extending so as to face a part of the local wiring;
Forming a plurality of second lower electrodes to be the capacitors in the interlayer insulating film located on the plurality of first lower electrodes;
Forming, in the interlayer insulating film, an upper electrode that becomes the capacitor and is an electrode common to the plurality of first and second lower electrodes so as to face a part of the local wiring; ,
Forming a first contact hole penetrating through the upper electrode and reaching the first support film in the interlayer insulating film by etching using the first support film as an etching stopper;
Forming a first contact plug electrically connected to the upper electrode so as to fill the inside of the first contact hole. Providing a step of forming a second support film connecting the plurality of second lower electrodes in the interlayer insulating film and extending so as to face a part of the local wiring;
In the step of forming the upper electrode, the upper electrode is formed on the second support film via a capacitive insulating film,
In the step of forming the first contact hole, the upper electrode and the second support film are penetrated under a condition that a difference in etching rate between the interlayer insulating film, the second support film, and the upper electrode is small. A first step of etching the interlayer insulating film, and etching the interlayer insulating film under a condition that the interlayer insulating film is selectively etched with respect to the first support film. Etching so as to penetrate through the first support film under a second step of exposing the upper surface of the first support film and under the condition that the first support film is selectively etched with respect to the interlayer insulating film The method for manufacturing a semiconductor device according to claim 9, wherein the first contact hole is formed by sequentially performing a third step. Before forming the interlayer insulating film, providing a step of forming a stopper film covering the local wiring,
In the step of forming the first contact hole, the first contact hole and the second contact hole that penetrates the interlayer insulating film and the stopper film and reaches the local wiring are formed simultaneously. The method of manufacturing a semiconductor device according to claim 10.   In the step of forming the first contact plug, a conductive film is embedded in the first and second contact holes to fill the first contact plug and the second contact hole. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the contact plug is formed simultaneously. A step of forming a landing pad connected to the lower end of the first lower electrode between the first lower electrode and the element layer before forming the interlayer insulating film;
10. The step of forming the landing pad includes forming a conductive film on the element layer and patterning the conductive film to form the local wiring together with the landing pad. 12. A method of manufacturing a semiconductor device according to claim 1.   A step of simultaneously forming a first upper wiring connected to the upper end of the first contact plug and a second upper wiring connected to the upper end of the second contact plug in an upper layer than the upper electrode. 14. The method of manufacturing a semiconductor device according to claim 12, wherein a semiconductor device is provided.

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