JP2011234312A - Operation device and central processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operation device capable of enhancing the resistance against power analysis attack.SOLUTION: An operation device 3 has a register group 2 and an ALU 1. Each of the register group 2 and the ALU 1 receives a switching control signal 101, and a switching data signal 102 that changes in time and is irrelevant to source data stored in the resister group 2. The register group 2 outputs one or more selected source data to the ALU 1 in response to that the switching control signal 101 is deactivated, and outputs one or more data based on the switching data signal 102 to the ALU 1 in response to that the switching control signal is activated. The ALU 1 outputs the operation result resulting from arithmetic operation or logical operation to the one or more source data in response to that the switching control signal is deactivated, and outputs the data based on the switching data signal 102 in response to that the switching control signal is activated.

Description

  The present invention relates to an arithmetic unit and a central processing unit, and more particularly to an arithmetic unit and a central processing unit that have improved resistance to power analysis attacks against cryptographic processing.

  In the power analysis attack, the secret information being processed is obtained by analyzing the power consumption of the circuit during the cryptographic process. Typical techniques include DPA (Differential Power Analysis) and CPA (Correlation Power Analysis) (see Non-Patent Documents 1 to 3). As a method for increasing resistance to power analysis attacks, for example, techniques described in the following documents are known.

  A semiconductor integrated circuit described in Japanese Patent Laying-Open No. 2008-269060 (Patent Document 1) includes a memory, a main control unit, a data bus, a usage state determination unit, an invalid data generation unit, and a bus control unit. . The memory stores security data or a data processing procedure thereof. The main control means controls execution of the data processing procedure. The data bus transmits transmission data used in executing the data processing procedure. The use state determination means detects whether or not the data bus is used based on a transmission control signal for controlling input / output of transmission data to / from the data bus for all peripheral devices connected to the data bus. The invalid data generation means generates invalid data. The bus control means outputs invalid data to the data bus when it is determined that the data bus is not used.

  In the encryption method described in Japanese Patent Publication No. 2002-526849 (Patent Document 2), the data bit word generated based on the random number is stored in the memory before the data bit word related to the encryption process is written in the memory cell or the register. Store in cell or register.

  Japanese Patent Laying-Open No. 2006-19872 (Patent Document 3) discloses a cryptographic processing apparatus that executes a cryptographic algorithm including a repetition process of a multi-stage round function such as DES (Data Encryption Standard). In this cryptographic processing apparatus, a random number is input at the time of a round transition to a function calculation unit that executes data processing for each round, and thereafter intermediate data stored in a register is input to perform calculation processing.

JP 2008-269060 A Japanese translation of PCT publication No. 2002-526849 JP 2006-19872 A

Kocher et al., "Differential Power Analysis" CRYPTO 1999. LNCS, vol. 1666, pp. 388-397. Springer, Heidelberg (1999) Brier et al., "Correlation Power Analysis with a Leakage Model" CHES 2004. LNCS, vol. 3156, pp. 16-29. Springer, Heidelberg (2004) Suzuki et al. “DPA Lekage Models for CMOS Logic Circuits” CHES 2005. LNCS, vol. 3659, pp. 366-382, Springer-Verlag (2005)

  The above-mentioned Japanese Patent Application Laid-Open No. 2008-269060 (Patent Document 1) discloses a power analysis attack that focuses on power consumption generated during data transfer between a CPU (Central Processing Unit) and a memory via a data bus. The technique which defends is disclosed. However, with this technology, it is not possible to defend against attacks that focus on power consumption during computations executed inside the CPU.

  The above Japanese translation of PCT publication No. 2002-526849 (Patent Document 2) discloses a technique for protecting an attack against power consumption when a memory or register writes data. However, this technique cannot prevent a power analysis attack based on power consumption when the CPU performs arithmetic processing using data stored in a memory or a register.

  The technique disclosed in the above Japanese Patent Application Laid-Open No. 2006-19872 (Patent Document 3) improves the resistance to a power analysis attack against a cryptographic circuit that executes cryptographic processing for a specific cipher such as DES, and the CPU It is not possible to defend against attacks that focus on power consumption during computations executed internally.

  Furthermore, some embodiments described in the above Japanese Patent Application Laid-Open No. 2008-269060 (Patent Document 1), Japanese Patent Application Publication No. 2002-526849 (Patent Document 2), and Japanese Patent Application Laid-Open No. 2006-19872 (Patent Document). In order to realize each embodiment disclosed in 3), a random number is necessary, and it is difficult to generate a random number having a necessary number of bits at high speed.

  An object of the present invention is to provide an arithmetic device and a CPU that can increase resistance to power analysis attacks without greatly changing the conventional design.

  An arithmetic device according to an embodiment of the present invention includes a storage unit and a calculation unit. The arithmetic unit performs an arithmetic operation or a logical operation using one or a plurality of source data received from the storage unit. Each of the storage unit and the calculation unit receives a switching control signal that is in an active state or an inactive state, and a data signal that changes over time and is irrelevant to one or more source data. The storage unit outputs one or a plurality of source data to the arithmetic unit in response to the switching control signal being inactivated, and the irrelevant data signal in response to the switching control signal being activated. One or a plurality of data based on the above is output to the arithmetic unit. The arithmetic unit outputs an operation result obtained by performing an arithmetic operation or a logical operation on one or a plurality of source data in response to the switching control signal being deactivated, and the switching control signal is activated. In response to the above, data based on the irrelevant data signal is output.

  According to the above embodiment, since the storage unit and the calculation unit constituting the calculation device output data unrelated to the source data used for calculation in response to the activation of the switching control signal, the calculation device Can be more resistant to power analysis attacks.

It is a block diagram which shows the structure of the arithmetic unit 3 according to Embodiment 1 of this invention. It is a figure for demonstrating the design method of an AND gate. It is a figure for demonstrating the design method of a selector. It is a figure for demonstrating the design method of D flip-flop. It is a figure for demonstrating the location which performs conversion of a circuit element in the arithmetic unit. FIG. 6 is a circuit diagram illustrating an example of a configuration of a circuit portion 11_1 that outputs a data signal 1 (109) illustrated in FIG. 5; FIG. 6 is a circuit diagram illustrating an example of a configuration of circuit portions 12_0 to 12_M to which data signals 1 and 2 (109, 110) illustrated in FIG. 5 are input. FIG. 6 is a circuit diagram illustrating an example of a configuration of a circuit portion 13 that outputs a calculation result 111 illustrated in FIG. 5. FIG. 6 is a timing chart showing an example of the operation of the arithmetic device 3 in FIG. 5. It is a block diagram which shows the structure of CPU10 according to Embodiment 2 of this invention. It is a block diagram which shows the structure of CPU10A according to Embodiment 3 of this invention. It is a block diagram which shows the structure of CPU10B according to Embodiment 4 of this invention. It is a block diagram which shows the structure of CPU10C according to Embodiment 5 of this invention. 3 is a diagram for explaining the configuration and operation of a clock buffer 17. FIG. FIG. 14 is a timing diagram illustrating an example of the operation of the CPU 10 </ b> C in FIG. 13. FIG. 15 is a block diagram showing a modification of the clock buffer 17 shown in FIG. It is a block diagram which shows the structure of CPU10D as a modification of CPU10C shown in FIG.

  In general, a CPU selects two data sources from a plurality of data sources when executing an instruction (for example, an arithmetic operation instruction or a logical operation instruction) using an ALU (Arithmetic Logic Unit), As the input data, the ALU executes the operation specified by the instruction using the input data. On the other hand, when an instruction that does not use an ALU is executed, the input data to the ALU does not have to be particularly meaningful data. Typically, (i) in a certain state (for example, a fixed value such as all zero data), and (ii) the data source selected when the ALU was last used is continuously input. There are cases. The output data (calculation result) of the ALU may be the same as (i) above when executing an instruction that does not use the ALU. These are determined depending on the design of the CPU.

  When secret information (for example, key information in cryptographic processing) is handled by a conventional CPU, in the case of (i) above, it appears inside the arithmetic unit (ALU and register group) when an instruction using the ALU is executed. There is a possibility that secret information may be leaked by power analysis using a Hamming weight of data (for example, input data and output data of ALU) as a selection function. This is because in a CMOS (Complementary Metal-Oxide Semiconductor) circuit constituting an arithmetic device, the number of signals changing from “0” to “1” or “1” to “0” (ie, Hamming distance) and power consumption This is because there is a high correlation. In the case of (ii) above, there is a possibility that secret information may be leaked by power analysis using the Hamming distance before and after the change when the contents of the register selected as the data source change as a selection function.

  Such extraction of secret information by power analysis is known as DPA (Differential Power Analysis), CPA (Correlation Power Analysis), or the like. In the case of DPA, a power consumption waveform is acquired for a large number of input data, and the acquired power consumption waveform is classified using a value of an internal variable correlated with an encryption key (referred to as a selection function). If there is a difference in the average value of the power waveform of each group, it can be seen that the predicted value of the key is correct. In CPA, a power consumption value is estimated for a predicted encryption key, and a correlation with an actual power consumption waveform is examined. After calculating correlation values for all encryption key candidates, the key candidate having the highest correlation value is determined to be true.

  The present invention provides a technique capable of enhancing the resistance to the power analysis attack described above without greatly changing the design of a conventional arithmetic device or CPU. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Outline of Configuration of Arithmetic Unit 3]
FIG. 1 is a block diagram showing a configuration of an arithmetic device 3 according to the first embodiment of the present invention. The arithmetic device 3 includes an ALU 1 as an arithmetic unit and a register group 2 as a storage unit, which are parts directly related to execution of arithmetic instructions in the CPU. ALU1 includes (M + 1) operation blocks 1_0 to 1_M (addition block, logical sum block, logical product block) which are included in the inside using two input data (data 1 (109) and data 2 (110)) as an operation source. , An exclusive OR block, etc.) perform the operation. The ALU 1 outputs the calculation result 111 of the type specified by the calculation type selection signal 100. The register group 2 is a register file that stores a plurality of source data that can be selected as input data of the ALU1, and includes (N + 1) registers 2_0 to 2_N.

  The arithmetic device 3 of FIG. 1 is different from the conventional arithmetic device in that a switching control signal 101 and a switching data signal 102 are input to the ALU 1 and the register group 2. In the case of FIG. 1, the switching control signal 101 is a 1-bit signal having an active state (active) and an inactive state (inactive). The switching data signal 102 is a multi-bit signal irrelevant to the source data used for the calculation by the calculation device 3. As illustrated in FIGS. 2 to 8, in a state where the switching control signal 101 is activated (asserted), at least a part of a plurality of circuit elements such as logic gates and flip-flops constituting the arithmetic device 3 is used. The signal output from the circuit element is changed to the switching data signal 102. As a result, all combinations of signals in the arithmetic device 3 (hereinafter referred to as “circuit states”) and output signals of the arithmetic circuit 3 can be set in a state unrelated to the arithmetic operation. On the other hand, in a state where the switching control signal 101 is inactivated (negated), the operation of the arithmetic device 3 is the same as that of the conventional arithmetic device, and is specifically as follows.

  First, in the arithmetic unit 3, prior to the execution of the operation, the register group 2 has one or more (usually two) out of (N + 1) registers 2_0 to 2_N according to the data source selection signals 1 and 2 (104, 105). And the source data stored in the selected register is output to the ALU 1 as input data (data 1 (109) and data 2 (110)). The ALU 1 performs a plurality of operations in parallel on the two input data 109 and 110 supplied from the register group 2 and outputs an operation result 111 corresponding to the operation type specified by the operation type selection signal 100. . Depending on the design of the ALU, valid data is input only to the operation block corresponding to the operation type specified by the operation type selection signal 100 among the (M + 1) operation blocks 1_0 to 1_M in the ALU 1, and the rest Some calculation blocks do not input valid data (for example, input a fixed value of all zeros). As a result, the ALU 1 operates only necessary operation blocks. The calculation result 111 output from the ALU 1 may be used by other than the calculation device 3 or may be written to the register group 2 in the calculation device 3. Writing to the register group 2 is controlled by a write register selection signal 106 and a write enable signal 107. Data (write data signal 108) may be written to the register group 2 from a memory or a register outside the arithmetic unit 3. The register group 2 further receives a clock signal 112 and a reset signal 113 from the outside.

[Problems of conventional arithmetic units]
The operation when the switching control signal 101 is negated as described above, that is, the operation of the conventional arithmetic device has the following problems from the viewpoint of resistance to power analysis attacks.

  The first problem occurs when an input data signal to at least one operation block in the ALU becomes a certain value (for example, all “0”) when an instruction that does not use the operation device 3 is executed. For example, when an instruction not using the arithmetic unit 3 is executed, the register group 2 is designed so as to output certain values as data 1 (109) and data 2 (110), or the arithmetic blocks 1_0 to 1_0 in the ALU 1 are output. In A_M, when ALU1 is designed to input a predetermined value to an operation block that does not correspond to the operation type specified by the operation type selection signal 100, a predetermined value in ALU1 is input. In the following description, it is assumed that the above determined values are all “0”. However, even if the other values are other than the above, the secret information is obtained by power analysis using the bit data of each input data signal as a selection function. There is a possibility of leakage.

  When an instruction not using the arithmetic unit 3 is executed, the input data signals (data 1 (109) and data 2 (110)) of the arithmetic blocks 1_0 to 1_M inside the ALU 1 are all “0” and the arithmetic unit 3 is used. Assume that the input data signal is changed to a value that is actually used for the operation when the instruction to be executed is executed. Then, power consumption depending on the Hamming weight (the number of “1” s in the bit string) of values used for the calculation is generated inside each calculation block. This is because the larger the number of bits that the input data signal changes (that is, the greater the Hamming distance), the more the internal signal of the operation block changes and consumes more power. In the above case, the hamming weight and the hamming distance of the input data signal to the ALU 1 are equal, and there is a possibility that secret information may be leaked by power analysis using the hamming weight of the input data as a selection function. The same applies when all input data signals to the ALU 1 return to “0” again after execution of the arithmetic instruction.

  The arithmetic device 3 is designed so that, when an instruction that does not use the arithmetic device 3 is executed, the value of the output signal of the arithmetic device 3 (that is, the operation result 111) becomes a predetermined value (for example, all “0”). In this case, the same problem as described above occurs. In this case, secret information may be leaked by power analysis using the Hamming weight of the calculation result 111 as a selection function.

  The second problem occurs when an instruction not using the arithmetic device 3 is executed and the data source selected when the arithmetic device 3 is last used continues to be input to the ALU 1. Specifically, when a certain arithmetic instruction is executed, a problem arises when the register for storing the data source of the arithmetic and the register for storing the arithmetic result are designated as the same register. In this case, ALU1 generates power consumption according to the Hamming distance of the contents of the register before and after the calculation. Therefore, secret information may be leaked by power analysis using the Hamming distance as a selection function.

  For example, in a program (c = a + b) in which the addition result of the variable “a” and the variable “b” is assigned to the variable “c”, the variable “c” and the variable “a” are allocated to the same register. In this case, the input data 109 and 110 of the ALU 1 during execution of the calculation are “a” and “b”, but change to “c” and “b” at the timing when the calculation result 111 is stored in the register. As described above, the larger the number of bits that the input data signal changes (that is, the greater the Hamming distance), the more the internal signal of the operation block changes and consumes more power. The changing number of bits of the input data signal is a Hamming distance between “a” and “c”, and there is a possibility that secret information may be leaked by power analysis using the Hamming distance as a selection function.

[Detailed Configuration of Arithmetic Unit 3]
In order to solve these problems, a plurality of selection circuits (selectors) are provided corresponding to at least some of the circuit elements such as logic gates and flip-flops constituting the arithmetic device 3. In this specification, a circuit element means a unit having a logical operation function or a storage function and functionally considered as one unit. Therefore, any of logic gates such as AND elements and OR elements, combinational circuits such as selectors (multiplexers) and adders, and sequential circuits such as flip-flops may be considered as circuit elements.

  Each selection circuit receives an output of a corresponding circuit element, a switching control signal 101, and a switching data signal 102. The selection circuit outputs the switching data signal 102 in response to the switching control signal 101 being asserted, and outputs the signal output from the corresponding circuit element in response to the switching control signal 101 being negated. .

  The design of the arithmetic device 3 (ALU1 and register group 2) does not require a significant change from the design of the conventional arithmetic device, and is typically designed in the following steps.

(1) A conventional ALU and register group circuit is designed.
(2) All of the circuit elements such as flip-flops or logic gates that generate internal signals including input / output signals of the ALU and register group based on the ALU and register group circuit obtained in (1) Alternatively, selectors are connected in series to the output nodes of some circuit elements.

  (3) The switching control signal 101 and the switching data signal 102 are connected to the selector connected in (2). A corresponding bit signal of the switching data signal 102 is input to each selector.

  The timing for asserting and negating the switching control signal 101 may be the same for all circuit elements to be converted. Even if the value of the switching data signal 102 is the same for all the circuit elements to be converted, there is not an effect of improving the resistance to the power analysis attack, but it is preferable that bit data is supplied separately for each circuit element to be converted. . The value of the switching data signal 102 supplied to one circuit element needs to be changed at an arbitrary timing (for example, every time a predetermined time elapses or every time a predetermined number of operations are executed). If the value of the switching data signal 102 is a fixed value that does not change with time, there is a risk that secret information may be leaked by power analysis using individual bits as a selection function. is there. Hereinafter, a design method for a specific circuit element will be described.

  FIG. 2 is a diagram for explaining a method of designing an AND gate. FIG. 2A shows a conventional AND gate 30 that outputs a logical sum of input signals IN1 and IN2, and FIG. 2B shows an AND gate 32 after a design change. The AND gate 32 has a selector 31 connected in series with the output node of the conventional AND gate 30. The selector 31 receives the output of the AND gate 30, the switching data signal 102, and the switching control signal 101. The selector 31 outputs the switching data signal 102 as the output signal OUT in response to the switching control signal 101 being asserted, and outputs the output of the AND gate 30 in response to the switching control signal 101 being negated. Output as OUT.

  FIG. 3 is a diagram for explaining a selector design method. 3A shows a conventional selector 34 that outputs one of the input signals IN1 and IN2 in response to the selection signal SEL, and FIG. 3B shows the selector 36 after the design change. The selector 36 has a selector 35 connected in series with the output node of the conventional selector 34. The selector 35 receives the output of the selector 34, the switching data signal 102, and the switching control signal 101. The selector 35 outputs the switching data signal 102 as the output signal OUT in response to the switching control signal 101 being asserted, and outputs the output of the selector 34 in response to the negation of the switching control signal 101 as the output signal OUT. Output as.

  FIG. 4 is a diagram for explaining a D-flip-flop design method. 4A shows a conventional D-flip flop 37, and FIG. 4B shows a D-flip flop 39 after design change. The conventional D-flip flop 37 holds the logic level of the input signal IN1 input to the data terminal D at the rising edge of the input signal IN2 input to the clock terminal CK. ) From the output terminal Q as an output signal OUT. The D-flip flop 39 after the design change is obtained by connecting a selector 38 to the output terminal Q of the conventional D-flip flop 37. The selector 38 receives the output of the D-flip flop 37, the switching data signal 102, and the switching control signal 101. The selector 38 outputs the switching data signal as the output signal OUT in response to the assertion of the switching control signal 101, and the output (D of the D flip-flop 37 in response to the negation of the switching control signal 101. The internal logic state of the flip-flop 37 is output as the output signal OUT.

  In FIG. 2B, the length of the wiring W1 connecting the AND gate 30 and the selector 31 is preferably as short as possible. Similarly, the length of the wiring W2 between the selectors 34 and 35 in FIG. 3B and the length of the wiring W3 connecting the D-flip flop 37 and the selector 38 in FIG. 4B are preferably as short as possible. . When the wiring length between the selector and the circuit element is long, the capacity of the wiring increases, and as a result, the power consumption of the signal flowing through the wiring and the absolute amount of the bias also increase. In order to reduce the bias of power consumption as much as possible, it is desirable to arrange the selector and the circuit element close to each other to suppress the wiring length and to reduce the absolute amount of power consumption as much as possible.

  2 to 4 show only the conversion of the AND gate, the selector, and the flip-flop, the same applies to other circuit elements, and the selector may be connected in series with the output node of the circuit element to be converted.

  Alternatively, a function equivalent to the circuit element after conversion (that is, a function combining a logic gate or flip-flop and a selector) may be realized by a single cell. In this case, the converted circuit element includes one or more first input nodes, a second input node to which the switching data signal 102 is input, and a third input node to which the switching control signal 101 is input. , And output nodes. In response to the deactivation of the switching control signal 101, the circuit element after the conversion is converted into a logical operation result of a signal input from one or more first input nodes, or data stored therein. Based signal is output. The converted circuit element outputs a signal corresponding to the switching data signal 102 in response to the switching control signal 101 being activated.

  2 to 4 show a case where the switching data signal 102 is output as it is from the circuit elements 32, 36, and 39 after the design change in response to the assertion of the switching control signal 101. There is no need to output. A signal obtained by modifying the switching data signal 102 may be output, for example, by inverting the logic level of the switching data signal 102.

  FIG. 5 is a diagram for explaining a place where circuit elements are converted in the arithmetic device 1.

  The conversion described with reference to FIGS. 2 to 4 need not be performed for all the logic gates and storage elements included in the ALU 1 and the register group 2 shown in FIG. However, as shown in FIG. 5, circuit portions 11_1 and 11_2 that output at least data signals 1 and 2 (109, 110), circuit portions 12_0 to 12_M that receive data signals 1 and 2 (109, 110), and arithmetic operations For the circuit portion 13 that outputs the result 111 and the register in which the operation result 111 is written, it is desirable to perform the conversion described with reference to FIGS. Among the above, the conversion of the circuit portions 11_1 and 11_2 will be described with reference to FIG. 6, the conversion of the circuit portions 12_0 to 12_M will be described with reference to FIG. 7, and the conversion of the circuit portion 13 will be described with reference to FIG. For the registers 2_0 to 2_N, the conversion shown in FIG. 4 is performed for each flip-flop.

  Furthermore, if conversion is also performed for the nonlinear logic gate in the ALU 1, the bias of the power consumption in the nonlinear logic gate can be reduced, and the resistance to the power analysis attack is further improved. Here, the linear logic gate is a logic gate in which the number of “1” and “0” output when random data is input is equal, such as an XOR (exclusive OR) element. A non-linear logic gate is a logic gate having a bias in the number of “1” and “0” output when random data is input, such as an AND element and an OR element.

  FIG. 6 is a circuit diagram showing an example of the configuration of the circuit portion 11_1 that outputs the data signal 1 (109) shown in FIG. 6A shows an example of a conventional circuit configuration, and FIG. 6B shows an example of a circuit configuration after conversion. Since the circuit portion 11_2 that outputs the data signal 2 (110) has the same configuration, an example of the configuration of the data signal 1 (109) circuit portion 11_1 is shown as a representative.

  As shown in FIG. 6A, AND gates 40_0 to 40_N into which output data DR_0 to DR_N of registers 0 to N (2_0 to 2_N) are input to the circuit portion 11_1 that outputs the data signal 1 (109), respectively. And an OR gate 41 to which the output of each AND gate 40 is input. A corresponding data source selection signal 104 (any one of 104 — 0 to 104 — N) is input to the other input node of each AND gate 40.

  As shown in FIG. 6B, the selector 42 is further connected to the output node of the OR gate 41 in the converted circuit portion 11_1. Here, the selector 42 receives the output of the OR gate 41, the switching control signal 101, and the switching data signal 102, and in response to the switching control signal 101 being asserted, the selector 42 converts the switching data signal 102 into the data signal 1 ( 109), and in response to the negation of the switching control signal 101, the output of the OR gate 41 is output as the data signal 1 (109).

  FIG. 7 is a circuit diagram illustrating an example of the configuration of the circuit portions 12_0 to 12_M to which the data signals 1 and 2 (109, 110) illustrated in FIG. 5 are input. 7A shows an example of a conventional circuit configuration, and FIG. 7B shows an example of a circuit configuration after conversion. The circuit portions 12_0 to 12_M are provided corresponding to the logic blocks 1_0 to 1_M, respectively. In FIG. 7, as an example, the logical block 1_0 is a logical product block, and the logical block 1_1 is a logical sum block.

  As shown in FIG. 7A, the circuit portion 12_0 includes an AND gate 43_0 that receives the data signal 1 (109) and an AND gate 44_0 that receives the data signal 2 (110). Further, a selection signal 100_0 representing a logical product among the operation type selection signals 100 is input to the AND gates 43_0 and 44_0. Each output node of the AND gates 43_0 and 44_0 is connected to the corresponding AND block 1_0. Similarly, the circuit portion 12_1 includes an AND gate 43_1 that receives the data signal 1 (109) and an AND gate 44_1 that receives the data signal 2 (110). The AND gates 43_1 and 44_1 are further supplied with a selection signal 100_1 representing a logical sum among the operation type selection signals 100. Each output node of the AND gates 43_1 and 44_1 is connected to the corresponding OR block 1_1. Although not shown in FIG. 7, the same applies to the circuit portions 12_2 to 12_M.

  As shown in FIG. 7B, the converted circuit portion 12_i (i is an integer of 0 to M) includes a selector 45_i inserted between the AND gate 43_i and the corresponding logic block 1_i, and an AND gate. It further includes a selector 46_i inserted between 44_i and the corresponding logical block 1_i. The selector 45_i receives data 1 (109), the corresponding bit signal among the switching data signal 102, and the switching control signal 101. The selector 46 — i receives the data 2 (110), the corresponding bit signal of the switching data signal 102, and the switching control signal 101. The selector 45_i outputs a corresponding bit signal of the switching data signal 102 to the corresponding logic block 1_i in response to the switching control signal 101 being asserted, and responds to the switching control signal 101 being negated. The output of the corresponding AND gate 43_i is output to the corresponding logic block 1_i. The selector 46_i outputs a corresponding bit signal of the switching data signal 102 to the corresponding logic block 1_i in response to the assertion of the switching control signal 101, and responds to the negation of the switching control signal 101. The output of the corresponding AND gate 44_i is output to the corresponding logic block 1_i.

  FIG. 8 is a circuit diagram showing an example of the configuration of the circuit portion 13 that outputs the calculation result 111 shown in FIG. 8A shows an example of a conventional circuit configuration, and FIG. 8B shows an example of a circuit configuration after conversion. In FIG. 8, as an example, the logical block 1_0 in FIG. 5 is an AND operation block, the logical block 1_1 is an OR operation block, and the logical block 1_M is an addition block.

  As shown in FIG. 8A, the circuit portion that outputs the operation result 111 includes AND gates 50_0 to 50_M corresponding to the logical blocks 1_0 to 1_M of the ALU1 and OR gates that receive the outputs of the AND gates 50_0 to 50_M, respectively. 51 is provided. The AND gates 50_0 to 50_M are further supplied with corresponding calculation type selection signals among the calculation type selection signals 100, respectively.

  As shown in FIG. 8B, a selector 52 is further connected to the output node of the OR gate 51 in the converted circuit portion 13. The selector 52 receives the output of the OR gate 51, the switching control signal 101, and the switching data signal 102. The selector 52 outputs the switching data signal 102 as the calculation result 111 in response to the switching control signal 101 being asserted, and outputs the output of the OR gate 51 in response to the switching control signal 101 being negated. 111 is output. However, the selector 52 delays the timing of outputting the switching data signal 102 by a time (delay time Td) corresponding to the calculation time of the calculation block from the timing when the switching control signal 101 is asserted. The selector 52 further delays the timing at which the output signal of the OR gate 51 is output by the delay time Td above the timing at which the switching control signal 101 is negated.

[Operation and Effect of Arithmetic Unit 3]
FIG. 9 is a timing chart showing an example of the operation of the arithmetic device 3 of FIG. In FIG. 9, in order from the top, the clock signal 112, operation type selection signal 100, data source selection signal 1 (104), data source selection signal 2 (105), write register selection signal 106, write enable signal 107, switching Data signal 102, switching control signal 101, data signal 1 (109), data signal 2 (110), calculation result 111, and data stored in register 4 (2_4) are shown. Hereinafter, referring to FIGS. 5 and 9, the addition result “c” (= a + b) of the data “a” stored in the register 4 (2_4) and the data “b” stored in the register 5 (2_5) is obtained. An operation when data is written to the register 4 (2_4) will be described.

  As shown in FIG. 9, the arithmetic unit 3 operates in response to the rising edge (time t1, t2, t3, t4) of the clock signal 112. Since the switching control signal 101 is asserted before the time t2, the invalid data “X0” is output as the data signal 1 (109) from the register group 2, and the invalid data “10” is output as the data signal 2 (110). X1 "is output. Invalid data “X2” is output from ALU1.

  At the next time t2, the switching control signal 101 is negated, and the switching data signal 102 is switched from “X0, X1, X2,...” To “Y0, Y1, Y2,. Note that the switching timing of the switching data signal 102 may be any timing while the switching control signal 101 is negated, that is, between time t2 and time t3.

  Further, at time t2, a signal representing an addition operation (ADD) is input to ALU1 as operation type selection signal 100. Register group 2 receives a signal representing register 4 (2_4) as data source selection signal 1 (104), and a signal representing register 5 (2_5) as data source selection signal 2 (105) for writing. A signal representing register 4 (2_4) is input as register selection signal 106. Further, the write enable signal 107 input to the register group 2 is asserted. As a result, data “a” is output as data signal 1 (109) from register group 2, and data “b” is output as data signal 2 (110). The signal 111 output from the ALU1 is switched from the invalid data “X2” to the addition result “c” (where c = a + b) after a delay time Td from the time t2. The addition result “c” is written into the register 4 at time t3 in response to the rise of the next clock signal.

  At the next time t3, the write enable signal 107 is negated and the switching control signal 101 is asserted. As a result, invalid data “Y0” is output as the data signal 1 (109) from the circuit portion 11_1 of the register group 2, and invalid data “Y1” is output as the data signal 2 (110) from the circuit portion 11_2. The signal 111 output from the circuit portion 13 of the ALU1 is switched to invalid data “Y2” with a delay time Td from the time t3.

  As described above, the switching control signal 101 is first asserted prior to the execution of the calculation. During the period when the switching control signal 101 is asserted, the output signal values (that is, circuit states) of the flip-flops and logic gates constituting the arithmetic device 3 are values determined by the switching data signal 102. Next, the actual calculation is executed by negating the switching control signal 101. The calculation type selection signal 100 and the data source selection signals 104 and 105 are supplied to the calculation device 3 in a state in which the switching control signal 101 is negated or the previous switching control signal (101) is asserted. After the calculation is completed, the switching control signal 101 is asserted again, and output signal values (that is, circuit states) such as flip-flops and logic gates constituting the calculation device 3 become values unrelated to the executed calculation. At the timing when the switching control signal 101 is negated, the operation result is written in the register designated by the write register selection signal 106 in the register group 2.

  The value of the internal signal of the arithmetic unit 3 before the execution of the operation and after the execution of the operation, that is, the circuit state, in particular, the input / output data signals 109, 110, and 111 of the ALU 1 are not predetermined values such as “0” but the switching data The value is determined by the signal 102. Therefore, the hamming weight of the input / output data of ALU1 is independent of the hamming distance of the input / output data of ALU1. Therefore, resistance to power analysis attacks using the Hamming weight of the input / output data of ALU1 as a selection function is improved.

  Even when the same register as the calculation source register is designated as the register for storing the calculation result, the data input to the ALU 1 is not the updated register contents at the timing when the data stored in the register is updated. The value is determined by the switching data signal 102. As a result, resistance against power analysis attacks using the Hamming distance before and after the update of the register value as a selection function is improved.

  Hereinafter, a case where the data width of the operation data is 4 bits will be specifically described with reference to FIGS. 6 (A) and 6 (B). In the circuit before conversion shown in FIG. 6A, when any register is not selected as a data source (for example, when an instruction that does not require an operation is executed), data 1 (109) output from the register group 2 The data in which all 4 bits are “0” (denoted as “0000”) appears. When register j (2_j) (j is an integer not smaller than 0 and not larger than N) is selected for execution of operation, data 1 (109) changes to the contents of register j (2_j). At this time, if the stored content of the register j (2_j) is “0101”, the power corresponding to the 2-bit change of the data 1 (109) is consumed in the arithmetic unit, and the content of the register j (2_j) is “ If “1111”, power corresponding to a 4-bit change of data 1 (109) is consumed. The same applies when data 1 (109) returns to “0000” upon completion of the above calculation. This result does not change no matter how many times the same operation is performed with the same data. For this reason, secret information may be leaked by power analysis using the Hamming weight of the value of the register j (2_j) as a selection function.

  On the other hand, in the circuit after conversion shown in FIG. 6B, since the switching control signal 101 is asserted in the state before the execution of the operation and the state after the execution of the operation, the value of the data 1 (109) becomes the switching data signal 102. Is set to the value of Specifically, it is assumed that the switching data signal 102 is set to “1010” before the calculation and “0101” after the calculation. In this case, if the stored content of the register j (2_j) is “0101”, the change of the data 1 (109) is 4 bits at the start of the calculation, and the change of the data 1 (109) is 0 bit when the calculation is completed. Therefore, there is no correlation between the Hamming weight of the value of the register j (2_j) and the data 1 (109). No matter how many times the same operation is performed with the same data, the power consumption changes depending on the contents of the switching data signal 102 at that time. As a result, resistance against power analysis attacks using the Hamming weight of the value of the register j (2_j) as a selection function is improved.

  In the case of the circuit elements that generate the input signals to the arithmetic blocks 1_0 to 1_M described with reference to FIG. 7, in the circuit illustrated in FIG. 7A before conversion, in the period when the arithmetic blocks 1_0 to 1_M are not used, A certain value (for example, data of all “0”) is input to these operation blocks. On the other hand, in the circuit shown in FIG. 7B after the change, the value set by the switching data signal 102 is input to these arithmetic blocks 1_0 to 1_M during a period when the arithmetic blocks 1_0 to 1_M are not used. The As a result, the resistance to a power analysis attack using the Hamming weight of the value of the selected register j (2_j) (j is an integer not less than 0 and not more than N) as a selection function is improved.

  The case where the conversion as shown in FIG. 8B is performed on the circuit element that outputs the calculation result 111 is similar to the above, and the resistance to power analysis using the Hamming weight of the calculation result 111 as a selection function is improved. Further, by performing the conversion as shown in FIG. 4 on each register in the register group 2, resistance to a power analysis attack using the Hamming distance of the register value before and after updating the register contents as a selection function is improved.

  As described above, according to the arithmetic device 3 of the first embodiment, the switching control signal 101 is activated for at least some of the circuit elements such as logic gates and flip-flops included in the arithmetic device 3. In response to this, the design is changed so as to output the switching data signal 102 irrelevant to the source data used in the calculation and the calculation result. As a result, it is possible to take detailed measures against power analysis attacks in units of circuit elements of the arithmetic device 3.

<Embodiment 2>
FIG. 10 is a block diagram showing a configuration of CPU 10 according to the second embodiment of the present invention. FIG. 10 also shows the main storage device 20 (instruction memory 21 and data memory 22) and the flow of signals. Of the signals input to the arithmetic unit 3 described with reference to FIG. 1, the clock signal 112 and the reset signal 113 are not shown. The clock signal 112 and the reset signal 113 are usually given from the outside of the CPU 10. The configuration of the CPU described in the second embodiment and each subsequent embodiment is shown as an example, and the arithmetic device 3 shown in the first embodiment is applicable to any known CPU. it can.

  In FIG. 10, the CPU 10 includes the arithmetic device 3 described in the first embodiment, an instruction register 4, an instruction decoder 5, a program counter 6, and a switching data signal generation unit 7. The instruction register 4 reads an instruction from the instruction memory 21 according to the value of the program counter 6. The instruction decoder 5 decodes the instruction read by the instruction register 4 and outputs a control signal corresponding to the type of instruction to the arithmetic unit 3 or the data memory 22. For example, when an arithmetic logic operation instruction is read, the instruction decoder 5 outputs an operation type selection signal 100 corresponding to the instruction content to the ALU 1, and a data source selection signal 1 (104), data source corresponding to the instruction content The selection signal 2 (105) and the write register selection signal 106 are output to the register group 2, and the write enable signal 107 is asserted. As a result, the operation is executed in ALU1, and the operation result is written to the designated register. When the memory operation instruction is read, the instruction decoder 5 outputs a write register selection signal 106 to the register group 2 according to the instruction content, outputs a memory control signal to the data memory 22, and a write enable signal 107. Is asserted. As a result, the data stored at the memory address instructed by the memory operation instruction is written as the write data 108 to the designated register of the register group 2.

  In the case of the second embodiment, the type of instruction further includes a switching instruction that is a dedicated instruction for asserting the switching control signal 101. The instruction decoder 5 normally outputs the negated switching control signal 101 to the ALU 1 and the register group 2. The instruction decoder 5 asserts the switching control signal 101 in the cycle in which the switching instruction is executed, and negates the switching control signal 101 when the execution of the switching instruction is completed. The switching command has no side effects other than changing the switching control signal 101. In the software that operates the CPU 10, the switching instruction is inserted before and after the arithmetic instruction that may cause the secret information to leak due to the power analysis attack. Since the switching instruction and the calculation instruction that may leak the secret information need to be executed continuously, they must be executed in the interrupt disabled state. This can be realized by using an interrupt mask function generally provided in the CPU. However, since the encryption processing program is normally executed with interrupts disabled, no additional interrupt mask is required to execute the switching instruction. Note that the above switching instruction is not added as a new instruction, and other instructions having no side effects (for example, a NOP instruction that performs nothing) may have the function of the above switching instruction. .

  In FIG. 10, the switching data signal generation unit 7 generates a switching data signal 102. As the switching data signal generator 7, for example, a random number generation source or a pseudo random number generator can be used. In addition, the switching data signal 102 may be generated using a system clock or a timer value at the time of execution of calculation.

  As described above, the CPU 10 according to the second embodiment can flexibly control the timing at which the switching control signal 101 is asserted or negated using software by adding a command for asserting the switching control signal 101. .

<Embodiment 3>
FIG. 11 is a block diagram showing a configuration of CPU 10A according to the third embodiment of the present invention. The CPU 10A in FIG. 11 includes a dedicated register 14 in which an arbitrary value can be written by software instead of the switching data signal generation unit 7 in FIG. 10, and uses the stored contents of the register 14 as the switching data signal 102. This is different from the CPU 10 of FIG. In the CPU 10A of FIG. 11, the dedicated register 14 is provided inside the register group 2A, but may be provided outside the register group 2A. The bit length of the register 14 is provided as much as necessary for generating the switching data signal (102). The switching data signal 102 may be generated by a plurality of dedicated registers.

  The CPU 10A may be provided with a dedicated instruction for writing an arbitrary value to the dedicated register 14, or an address is assigned to the dedicated register 14 and an arbitrary value is written to the dedicated register 14 by a normal store instruction. Good. The stored contents of the dedicated register 14 can be updated to arbitrary data by software at an arbitrary timing (for example, every time a predetermined time elapses or every time a predetermined number of operations are executed). In this case, it is preferable that the data to be written to the dedicated register 14 includes “0” and “1” bits at an approximately equal ratio and has a small deviation.

  Other points in FIG. 11 are the same as those in FIG. 10, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Embodiment 4>
FIG. 12 is a block diagram showing a configuration of CPU 10B according to the fourth embodiment of the present invention. The CPU 10B of FIG. 12 includes a shift register 15 having a bit length necessary for use as the switching data signal 102 instead of the dedicated register 14 of FIG. 11, and uses the stored contents of the shift register 15 as the switching data signal 102. This is different from the CPU 10A of FIG. Instead of the single shift register 15 shown in FIG. 12, the switching data signal 102 may be generated by a plurality of shift registers. In the CPU 10B, the value of the switching data signal 102 changes as the shift register 15 shifts.
The data stored in the shift register 15 is an arbitrary bit pattern in which 0 and 1 appear in each bit in a substantially equal ratio in accordance with the shift operation, and the bias between adjacent bits is small. As an example, when a 32-bit shift register is used to cyclically shift one bit at a time, for example, “01010011101011001010110001010011” may be set as an initial value.

  Examples of the shift method of the shift register 15 include the following examples, and are not particularly limited.

  (1) A cyclic shift is performed by an arbitrary number of bits (for example, one bit) every predetermined clock cycle.

  (2) Each time the switching control signal 101 is asserted a predetermined number of times, a cyclic shift is performed by an arbitrary number of bits (for example, by 1 bit).

  (3) Repeat “1-bit right cyclic shift, 3-bit left cyclic shift every clock cycle”.

  (4) The shift operation of “2-bit left cyclic shift is performed 50 times and 1-bit right cyclic shift is performed 100 times” is repeated.

  (5) The shift operation of “cyclic shift continuously for 100 clock cycles and no cyclic shift for 50 clock cycles” is repeated.

Furthermore, the following method is also conceivable as a shift method other than the cyclic shift.
(6) The inverted value of the shifted out bit is added as a new bit.

  (7) Instead of the shifted out bit, the Xth bit of the shift register is added as a new bit.

  Further, similarly to the dedicated register 14 described in the third embodiment, any value may be written to the shift register 15 by software, or the shift method may be changed by software.

<Embodiment 5>
FIG. 13 is a block diagram showing a configuration of CPU 10C according to the fifth embodiment of the present invention. The CPU 10C of FIG. 13 has a mode setting register 16, a clock buffer 17, and an AND gate 18 (switching) as a new configuration for generating the switching control signal 101 without the instruction decoder 5A generating the switching control signal 101. 12 is different from the CPU 10B of FIG.

  The CPU 10C has two operation modes, a secure mode and a non-secure mode. Which operation mode is selected depends on the value of the mode setting register 16. In the case of FIG. 13, the secure mode is set when the value of the mode setting register 16 is “1”, and the non-secure mode is set when “0”. In the secure mode, the control of the arithmetic device 3C by the switching control signal 101 and the switching data signal 102 is effective. In the non-secure mode, control by the switching control signal 101 and the switching data signal 102 is invalid. The value of the mode setting register 16 can be set by software. Typically, a specific bit of an existing control register is assigned as the mode setting register 16, but the CPU 10C may include a dedicated register for mode setting or a dedicated instruction for accessing the register. In FIG. 13, the mode setting register 16 is provided in the register group 2C, but the mode setting register 16 may be provided outside the register group 2C.

  The clock buffer 17 generates a new signal 114 synchronized with the clock signal 112 based on the clock signal 112 given from the outside of the CPU 10C. The clock buffer 17 is used when the clock signal 112 is not permitted as an input signal of the combinational circuit as a design rule.

  FIG. 14 is a diagram for explaining the configuration and operation of the clock buffer 17. Referring to FIG. 14A, clock buffer 17 includes D-flip flops 61 and 62, inverters 63 and 64, and an exclusive OR gate 65. The clock signal 112 is input to the clock terminal CK of the D flip-flops 61 and 62. The output terminal Q of the D flip-flop 61 is connected to the data terminal D of the D flip-flop 61 through the inverter 63. The output terminal Q of the D flip-flop 62 is connected to the data terminal D of the D flip-flop 62 through the inverter 64. The output terminals Q of the D flip-flops 61 and 62 are further connected to the input node of the exclusive OR gate 65. In the D-flip flop 61, the input value of the D terminal is held as the output of the Q terminal in response to the rising edge of the clock signal 112, and the D-flip flop 62 in response to the falling edge of the clock signal 112. The input value of the terminal is held as the output of the Q terminal.

  FIG. 14B shows voltage waveforms of the clock signal 112, the output signals S1 and S2 of the D-flip flops 61 and 62, and the output signal SOUT of the exclusive OR gate 65. The output signal S1 of the D-flip flop 61 is switched to a high (H) level or a low (L) level in response to the rising edge (time t1, t3, etc.) of the clock signal 112, and the output signal to the D-flip flop 62 is output. S2 switches to H level or L level in response to the falling edge of clock signal 112 (time t2, t4, etc.). As a result, the signal level of the output signal SOUT of the exclusive OR gate 65 changes in response to the clock signal 112.

  Referring again to FIG. 13, the AND gate 18 receives the output signal 114 of the clock buffer 17 and the mode setting signal 115 corresponding to the setting value of the mode setting register 16, and these logical products are used as the switching control signal 101. , ALU1 and register group 2C. Therefore, in the secure mode in which the value of the mode setting register 16 is “1”, the switching control signal 101 is asserted during the period in which the clock signal is “1” (H level) in one clock cycle, and the clock signal is “0”. ”(L level), the switching control signal 101 is negated. Therefore, in the secure mode, the period of the clock signal “0” is a time that can be used for the arithmetic processing by the arithmetic device 3C. On the other hand, in the non-secure mode where the value of the mode setting register 16 is “0”, the switching control signal 101 is negated regardless of the logic level of the output signal 114 of the clock buffer 17. Therefore, in the non-secure mode, all of one clock cycle is a time that can be used for arithmetic processing by the arithmetic device 3C.

  The other points in FIG. 13 are the same as those of CPU 10B described in FIG. 12, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 15 is a timing chart showing an example of the operation of the CPU 10C of FIG. In FIG. 15, in order from the top, the clock signal 112, the operation type selection signal 100, the data source selection signal 1 (104), the data source selection signal 2 (105), the write register selection signal 106, the write enable signal 107, switching The data signal 102, the switching control signal 101, the data signal 1 (109), the data signal 2 (110), the signal 111 indicating the calculation result, and the data stored in the register 4 (2_4) are shown. Hereinafter, referring to FIG. 13 and FIG. 15, the addition result “c” (= a + b) of the data “a” stored in the register 4 (2_4) and the data “b” stored in the register 5 (2_5) is obtained. An operation when data is written to the register 4 (2_4) will be described.

  As shown in FIG. 15, the CPU 10C operates in response to the rising edges (time t11, t13, t15, t17) of the clock signal 112 except for the switching control signal 101. The switching control signal 101 is asserted in response to the rising edge of the clock signal 112 and negated in response to the falling edge of the clock signal 112 (time t12, t14, t16, t18). Thus, data signals 1 and 2 (109, 110) output from ALU1 from register group 2C and signal 111 representing the operation result output from ALU1 are also responsive to both the rising edge and falling edge of clock signal 112. Change. However, the signal level of the signal 111 representing the calculation result output from the ALU 1 changes with a delay from the clock edge by a time corresponding to the calculation time in the ALU 1 (delay time Td).

  The value of the switching data signal 102 changes in response to the rising edge of the clock signal 112, for example, when the shift register 15 is cyclically shifted. In the case of FIG. 15, the switching data signal 102 is switched to “X0, X1, X2,...” At time t11, switched to “Y0, Y1, Y2,. , Z1, Z2,...

  At time t13, a signal representing an addition operation (ADD) is input to ALU1 as operation type selection signal 100. The register group 2C receives a signal representing the register 4 as the data source selection signal 1 (104), receives a signal representing the register 5 as the data source selection signal 2 (105), and registers as the write register selection signal 106. 4 is input. Further, the write enable signal 107 input to the register group 2C is asserted.

  Since the switching control signal 101 is asserted in the time zone between the time t13 and the next time t14, the data signals 1 and 2 (109, 110) input to the ALU1 are switched data signals “Y0”, “Y1” and the stored contents “a” and “b” of the registers 4 and 5 (2_4 and 2_5) are not input to the ALU1.

  When the switching control signal 101 is negated at time t14, “a” and “b” are input to the ALU 1 as the data signals 1 and 2 (109 and 110). As a result, the signal 111 output from the ALU 1 is switched from the switching data signal “Y2” to the addition result “c” (c = a + b) after a delay time Td from the time t14. The addition result “c” is written to the register 4 at time t15 in response to the rising edge of the next clock signal 112.

  At the next time t15, the write enable signal 107 is negated and the switching control signal 101 is asserted. As a result, the invalid data “Z0” is output to the ALU1 as the data signal 1 (109) from the register group 2C, and the invalid data “Z1” is output to the ALU1 as the data signal 2 (110). The signal 111 output from the ALU1 is switched to invalid data “Z2” with a delay time Td from the time t3.

  As described above, by asserting the switching control signal 101 in the first half of one clock cycle, the values of the signals 109, 110, and 111 inputted to and outputted from the ALU1 and the circuit state in the arithmetic unit 3C are changed over to the switching data. The value is determined by the signal 102. The actual calculation is executed by negating the switching control signal 101 in the second half of one clock cycle. After the calculation is completed, by asserting the switching control signal 101 again, the values of the signals 109, 110, and 111 input / output to / from the ALU1 become values determined by the switching data signal 102, and become values unrelated to the executed calculation. As a result, the Hamming weight of the input / output data of ALU1 becomes independent of the Hamming distance of the input / output data of ALU1. For this reason, the resistance against the power analysis attack using the Hamming weight of the input / output data of the ALU1 as the selection function is improved, and the resistance against the power analysis attack using the Hamming distance of the register value before and after the update is also improved. Furthermore, since the output of the switching data signal and the arithmetic processing are performed during one clock cycle, it is not necessary to provide an extra clock cycle for outputting the switching data signal.

  However, in the case of the fifth embodiment, the restriction on the clock frequency is stricter than in the case of FIG. That is, in the secure mode, the actual arithmetic processing starts only after the clock signal 112 becomes “0” (L level), but the arithmetic processing needs to be completed before the next rising of the clock signal 112. Therefore, the period T2 in which the clock signal 112 is “0” needs to be longer than the delay time Td corresponding to the calculation processing time (that is, Td <T2). On the other hand, in the non-secure mode, it is not necessary to satisfy Td <T2, and Td <T1 + T2 = Tc may be satisfied (however, a period in which the clock signal 112 is “1” is T1 and a clock cycle is Tc). As a result, in the non-secure mode, T2 can be made smaller than in the secure mode. Therefore, when executing a program with no possibility of leakage of secret information, the CPU clock frequency can be improved by setting the non-secure mode. The function of controlling the clock frequency by software control is a function provided in many existing CPUs.

  FIG. 16 is a block diagram showing a modification of the clock buffer 17 shown in FIG. A clock buffer 17 </ b> A illustrated in FIG. 16 includes a D-flip flop 61 and an inverter 63. A clock signal 120 having a frequency twice that of the clock signal used by the arithmetic unit 3C of FIG. 13 is supplied to the clock terminal CK of the D flip-flop 61. The output terminal Q of the D flip-flop 61 is connected to the data terminal D of the D flip-flop 61 through the inverter 63. A signal output from the data terminal D of the D flip-flop 61 is the switching control signal 101.

  FIG. 17 is a block diagram showing a configuration of a CPU 10D as a modification of the CPU 10C shown in FIG. The CPU 10D of FIG. 17 differs from the CU 10C of FIG. 13 in that the instruction decoder 5B outputs a mode setting signal 116 for designating an operation mode to the AND gate 18 instead of the mode setting register 16. The arithmetic device 3B of FIG. 17 is not provided with the mode setting register 16, and the configuration of the arithmetic device 3B is the same as that of FIG.

  In FIG. 17, when the instruction read from the instruction register 4 is an arithmetic instruction for performing an arithmetic operation using the arithmetic device 3B, the instruction decoder 5B designates the secure mode while executing the arithmetic instruction. The mode setting signal 116 (“1”: H level) is output to the AND gate 18. The instruction decoder 5B outputs a mode setting signal 116 (“0”: L level) designating the non-secure mode to the AND gate 18 after the execution of the operation instruction is completed.

  The other points of CPU 10D shown in FIG. 17 are the same as those of CPU 10C shown in FIG. 13. Therefore, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  Each embodiment disclosed this time should be considered as illustrative in all points and not restrictive. For example, in the above second to fifth embodiments, various generation methods of the switching control signal 101 and the switching data signal 102 have been described. The generation methods of these signals are the generation methods described in the second to fifth embodiments. It is not limited to. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 arithmetic logic unit (ALU), 2, 2A, 2B, 2C register group, 3, 3A, 3B, 3C arithmetic unit, 5, 5A, 5B instruction decoder, 7 switching data signal generator, 14 dedicated register, 15 shift Register, 16 mode setting register, 31, 35, 38, 42, 45, 46, 52 selector, 101 switching control signal, 102 switching data signal, 109, 110 input data, 111 operation result, 112 clock signal, 115, 116 Mode setting signal.

Claims (10)

A storage unit;
An arithmetic unit that performs an arithmetic operation or a logical operation using one or more source data received from the storage unit,
Each of the storage unit and the calculation unit receives a switching control signal that is in an active state or an inactive state, and a data signal that changes over time and is unrelated to the one or more source data,
The storage unit outputs the one or more source data to the arithmetic unit in response to the switching control signal being deactivated, and the storage unit is in response to the switching control signal being activated. Outputting one or more data based on an irrelevant data signal to the computing unit;
The operation unit outputs an operation result obtained by performing an arithmetic operation or a logical operation on the one or more source data in response to the switching control signal being deactivated, and the switching control signal is activated. A computing device that outputs data based on the irrelevant data signal in response to being converted. The unrelated data signal is a multi-bit signal,
Each of the storage unit and the calculation unit is
A plurality of circuit elements each having a logical operation function or a storage function;
A plurality of selection circuits respectively corresponding to at least a part of the plurality of circuit elements,
Each of the plurality of selection circuits receives an output signal of a corresponding circuit element, a signal of a corresponding bit among the irrelevant data signal, and the switching control signal,
Each of the plurality of selection circuits outputs an output signal of the corresponding circuit element in response to the switching control signal being deactivated, and in response to the switching control signal being activated. The arithmetic unit according to claim 1, wherein a signal of the corresponding bit is output. A plurality of circuit elements having a logical operation function or a storage function are provided,
Each of at least some of the plurality of circuit elements is
One or more first input nodes;
A second input node receiving a signal different from the one or more signals input from the one or more first input nodes;
An output node;
A third input node that receives a switching control signal for switching a signal output from the output node;
Each of the circuit elements performs a logical operation on one or more signals input from the one or more first input nodes in response to the switching control signal being deactivated. Or a signal corresponding to the data stored inside is output from the output node,
Each of the partial circuit elements outputs a signal corresponding to a signal input from the second input node from the output node in response to activation of the switching control signal. . The arithmetic device according to claim 1 or 2,
An instruction decoder that receives any of a plurality of preset instructions and outputs a signal corresponding to the received instruction to the arithmetic unit;
The plurality of instructions includes a central processing unit (CPU) including an operation instruction for causing the operation unit to perform an arithmetic operation or a logical operation. The central processing unit further includes a first register that is provided inside or outside the storage unit and stores data corresponding to the irrelevant data signal,
The central processing unit according to claim 4, wherein the data stored in the first register can be set by a program. The central processing unit further includes a shift register that is provided inside or outside the storage unit and stores data corresponding to the irrelevant data signal,
The central processing unit according to claim 4, wherein the irrelevant data signal changes as the shift register shifts. The plurality of instructions include a switching instruction for activating the switching control signal,
The central processing unit according to claim 4, wherein the instruction decoder outputs the switching control signal to the arithmetic unit and activates the switching control signal when the switching instruction is received. The central processing unit has first and second operation modes;
The central processing unit receives a clock signal and a mode setting signal for setting one of the first and second operation modes, and generates the switching control signal based on the clock signal and the mode setting signal A switching control signal generation unit
The storage unit stores a calculation result of the calculation unit in response to a first edge of the clock signal,
The switching control signal generation unit activates the switching control signal in response to the first edge of the clock signal and responds to the second edge of the clock signal in the first operation mode. Deactivating the switching control signal,
The central processing unit according to claim 4, wherein the switching control signal generation unit deactivates the switching control signal regardless of the clock signal in the second operation mode. The central processing unit further includes a second register that is provided inside or outside the storage unit and stores data corresponding to the mode setting signal,
9. The central processing unit according to claim 8, wherein the data stored in the second register can be set by a program.   The instruction decoder outputs the mode setting signal for designating the first operation mode to the switching control signal generation unit while the arithmetic device is executing an operation according to the arithmetic instruction, and the arithmetic device 9. The central processing according to claim 8, wherein after completing execution of the operations according to the plurality of the operation instructions, the mode setting signal designating the second operation mode is output to the switching control signal generation unit. apparatus.

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