JP2011234114A - Frame processor and frame processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reduction of a buffer resource generated when an abnormality occurs in a value read out from an address storage section which stores an empty address of the buffer.SOLUTION: A frame processor 1 comprises an address storage section 3 storing an empty address of a buffer 2, a frame writing section 4 writing a frame into the empty address read out from the address storage section 3 by designating a reading address by a cyclic address, a first storing section 10 storing a using state of each address of the buffer 2, a state changing section 11 changing the using state, which is stored into the first storing section 10, of the address into which the frame is written when writing the frame into the buffer 2, and an address detection section 20 detecting the address stored into the first storing section 10 as an unused address without being subjected to a writing process over a period of time of one cycle of the cyclic address.

Description

  Embodiments discussed herein relate to a frame processing apparatus and a frame processing method for storing frames in a buffer.

  A frame processing apparatus that processes a frame transmitted on a communication transmission path is provided with a buffer for storing the frame. The frame processing apparatus includes an address storage unit that stores empty addresses in the buffer. When storing the frame in the buffer, the empty address stored in the address storage unit is read, and the frame is written in the read empty address. When a frame is read from the buffer, the address that has been emptied is returned to the address storage unit again.

  It is a memory free management device that manages free addresses of memory for storing various information, and has the same number of addresses as the number of addresses in the memory, and stores whether the corresponding address is free or in use. One having a free address management table has been proposed. This free management device holds information indicating whether a certain address in the memory is free or in use in a free address management table area having the same address value as that address.

  In addition, there has been proposed an exchange apparatus provided with an address usage status table in the usage status storage unit that can register the usage status of all buffer addresses existing in the exchange apparatus. By providing the address usage status table, it is possible to grasp what buffer address actually exists in the shared buffer memory of the switching apparatus and which queue address currently exists.

  A buffer memory device comprising a buffer memory, an empty pointer management unit, a buffer memory management unit, a QoS scheduler, a QoS management content memory, a writing unit for writing data to the buffer memory, and a reading unit for reading data from the buffer memory Proposed.

  There has also been proposed a buffer memory circuit comprising an address memory for storing a write address, an empty address memory for storing an empty address of the buffer memory, and an error address detection circuit having information on the address in use of the buffer memory. The error detection circuit detects an overlap between the address in use of the buffer memory and the address read from the empty address memory, and sends an error signal to the control circuit when there is an overlap.

JP 2000-105723 A Japanese Patent Laid-Open No. 7-321795 JP 2004-240711 A JP-A-9-305493

  When an abnormality occurs in the value of the empty address read from the address storage unit, the frame is stored at an address different from the original storage destination. For this reason, there is no opportunity for the original storage destination address to be returned to the address storage unit, and no frame is stored at this address, so that available buffer resources are reduced.

  The apparatus and method according to the embodiment prevents a reduction in available buffer resources when an abnormality occurs in the value of the empty address of the buffer read from the address storage unit.

  A frame processing device according to another embodiment includes a buffer, an address storage unit that stores a free address of the buffer, and a free address that is read from the address storage unit by designating a read address by a cyclic address generated in a cyclic order The frame writing unit for writing the frame, the first storage unit for storing the use state of each address of the buffer, and the address at which the frame is written when the frame is written to the buffer is stored in the first storage unit. The state changing unit that changes the usage state from unused to in-use, and the writing process by the frame writing unit is not performed over the period in which the cyclic address makes a round and is stored in the first storage unit as unused. An address detecting unit for detecting an address to be detected.

  In a frame processing method according to another embodiment, a free address of a buffer is stored in an address storage unit, and a free address is read from the address storage unit by designating a read address by a cyclic address generated in a cyclic order. When a frame is written to an address, the use state of the free address stored in the first storage unit that stores the use state of each address in the buffer is changed from unused to used, and the cyclic address goes through a period. The address stored in the first storage unit is detected when the frame writing process is not performed and the frame is not used.

  According to the apparatus or method of the present disclosure, it is possible to prevent reduction of available buffer resources when an abnormality occurs in the value of the empty address of the buffer read from the address storage unit.

It is a figure which shows the 1st structural example of a frame processing apparatus. It is explanatory drawing of the frame writing process in the frame processing apparatus shown in FIG. It is a figure which shows the 2nd structural example of a frame processing apparatus. It is explanatory drawing of the frame writing process in the frame processing apparatus shown in FIG. It is a figure which shows the 3rd structural example of a frame processing apparatus. It is explanatory drawing of the frame read-out process in the frame processing apparatus shown in FIG. It is a figure which shows the 4th structural example of a frame processing apparatus. It is a figure which shows the 5th structural example of a frame processing apparatus. It is explanatory drawing of the frame writing process in the frame processing apparatus shown in FIG. It is explanatory drawing of the detection process of the address abnormality in the frame processing apparatus shown in FIG. It is explanatory drawing of the initial state of the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 1) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 2) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 3) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 4) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 5) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 6) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 7) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 8) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 9) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 10) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 11) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer. It is explanatory drawing (the 12) of the data memorize | stored in the address memory | storage part shown in FIG. 8, a 1st memory | storage part, a 2nd memory | storage part, and a buffer.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a first configuration example of the frame processing apparatus. For example, the frame processing device 1 may be a frame transmission device that transmits a frame transmitted on a communication transmission path. Examples of such a frame transmission device include a switch device and a router device. The frame processing device 1 includes a buffer 2, an address storage unit 3, a frame writing unit 4, a frame reading unit 5, a first storage unit 10, a state change unit 11, and an address detection unit 20.

  The buffer 2 stores an input frame. The buffer 2 of this embodiment has a storage capacity for storing N frames. Each storage location for storing N frames is specified by an N-value address. Each storage destination address may be, for example, “0” to “N−1”. In the following description, an address representing each storage destination of the buffer 2 may be referred to as a “buffer address”.

  The address storage unit 3 stores an empty address of the buffer 2. The address storage unit 3 has a storage capacity for storing N buffer addresses. Each storage location for storing N buffer addresses is specified by an N-value address. Each storage destination address may be, for example, “0” to “N−1”.

  The frame writing unit 4 reads the empty address of the buffer 2 from the address storage unit 3 and writes the frame to the acquired empty address. The read address used when the frame writing unit 4 reads the empty address of the buffer 2 from the address storage unit 3 is a cyclic address generated in a cyclic order. In the following description, a read address used when reading an empty address from the address storage unit 3 may be referred to as a “first read address”.

  The first read address, which is a cyclic address, sequentially changes to a value selected from N addresses one by one in a predetermined order. When all N addresses are used, the first read address returns to the first selected address again. For example, the first read address may be an address that increases one by one from “0”. After the first read address becomes “15”, the first read address returns to “0” again.

  When a frame is written into the buffer 2, the frame reading unit 5 receives a write address at which the frame is written. The frame reading unit 5 reads a frame from the buffer 2 using the received address as a reading address. In the following description, a read address used when the frame reading unit 5 reads a frame from the buffer 2 may be referred to as a “second read address”. The frame reading unit 5 returns the second reading address to the address storage unit 3. The second read address is stored in the address that has the earliest read order in the unused area of the address storage unit 3.

  The first storage unit 10 stores the usage state of each buffer address. The first storage unit 10 has a storage capacity for storing a use state for each of the N buffer addresses. For example, the first storage unit 10 may have an N-bit storage capacity. The storage destination for storing the usage status of each of the N buffer addresses is designated by an N-value address. Each storage destination address may be, for example, “0” to “N−1”.

  In each embodiment described below, the usage states of the buffer addresses “0” to “N−1” are stored in the addresses “0” to “N−1” of the first storage unit 10, respectively. However, the first storage unit 10 only needs to be able to store the usage state of each buffer address. As the first storage unit 10, various configurations that can store the use state of each buffer address can be employed.

  Various values may be used as a value indicating whether the buffer address is in use or unused. For example, in this embodiment, “1” is stored in the first storage unit 10 as a value indicating the use state when the buffer address is in use, and “0” is set as a value indicating the use state when the buffer address is not used. Is memorized.

  When a frame is written in the buffer 2, the state change unit 11 changes the use state stored in the first storage unit 10 for the buffer address to which the frame is written from unused (0) to in use (1).

  The address detection unit 20 does not perform the writing process by the frame writing unit 4 over a period in which the first read address that is the cyclic address makes a round, and stores the address in the first storage unit 10 when it is unused. Is detected.

  FIG. 2 is an explanatory diagram of the frame writing process in the frame processing apparatus 1 shown in FIG. In other embodiments, the following operations AA to AI may be steps.

  In operation AA, the frame writing unit 4 attempts to receive a frame. When the frame is received (operation AA: Y), the processing proceeds to operation AB. When no frame is received (operation AA: N), operation AA is repeated.

  In operation AB, the frame writing unit 4 generates the first read address in a cyclic order. The first read address may not be generated by the frame writing unit 4. The first read address may be generated by another component (not shown). In operation AC, the frame writing unit 4 reads an empty address of the buffer 2 from the address storage unit 3 using the generated first read address as a read address.

  In operation AD, the state change unit 11 changes the use state stored in the first storage unit 10 for the read empty address from the value “0” indicating unused to the value “1” indicating in use. . At this time, for example, the read address of the first storage unit 10 may be specified by an empty address read from the address storage unit 3. The state changing unit 11 may check whether or not the usage state read from the first storage unit 10 represents “unused (0)”. When the use state indicates “unused (0)”, the state change unit 11 sends “used” to the first storage unit 10 in which the write address is designated by the free address read from the address storage unit 3. A value “1” may be input.

  In operation AE, the frame writing unit 4 stores the frame at the empty address read from the address storage unit 3. In operation AF, the frame reading unit 5 stores the empty address read from the address storage unit 3. The operations AD to AF may be executed in any order.

  In operation AG, the address detection unit 20 reads the usage state from the first storage unit 10 designated with the first read address as the read address. That is, the address detection unit 20 reads the use state of the buffer address having the same value as the first read address. The address detection unit 20 determines whether or not a buffer address having the same value as the first read address is unused.

  When the buffer address having the same value as the first read address is not unused (operation AG: N), the process ends. When the buffer address having the same value as the first read address is unused (operation AG: Y), the process proceeds to operation AH.

  In operation AH, the address detection unit 20 performs the writing process by the frame writing unit 4 over a period in which the first read address makes a round for the buffer address having the same value as the current first read address. It is determined whether or not there is a problem.

  For example, the address detection unit 20 may store that each buffer address has been written when a frame is written to the buffer address. The address detection unit 20 then starts the same operation as the current first read address within the period until the first read address starts from the same address as the current address value and then returns to the current address value once again. It may be determined whether a write process has been performed on the value buffer address.

  If the writing process has never been performed (operation AH: Y), the process proceeds to operation AI. If the writing process has been performed (operation AH: N), the process ends.

  In operation AI, the address detection unit 20 detects the current first read address as an abnormal address.

  If a buffer address is not used, this buffer address is stored in the address storage unit 3 if the buffer address is not lost due to an abnormality. Therefore, the buffer address is read at least once by the frame writing unit 4 and the frame is written to the buffer address while the first read address makes a round. Therefore, it can be considered that an unused buffer address is a buffer address that has disappeared from the storage of the address storage unit 3 while the frame writing process is not performed over a period of one cycle of the first read address.

  According to this embodiment, it is possible to detect a buffer address that has disappeared from the storage of the address storage unit 3. For this reason, even if an address disappears from the storage of the address storage unit 3 due to an abnormality in the value of the buffer address read from the address storage unit 3, this address can be specified.

  In the above-described embodiment, the value of the buffer address determined in operation AG is specified by the first read address. Instead, the value of the buffer address may be specified by another cyclic address that is generated in a cyclic order so as to change in synchronization with the first read address and can specify each address of the address storage unit 3. Good. Examples of such other cyclic addresses are an address advanced by a predetermined number of addresses from the first read address or an address delayed by a predetermined number of addresses from the first read address.

  At this time, in operation AH, the address detection unit 20 performs the writing process by the frame writing unit 4 over a period in which the other cyclic address completes a cycle with respect to the buffer address having the same value as the other cyclic address. It is determined whether or not it has been broken.

  FIG. 3 is a diagram illustrating a second configuration example of the frame processing device. The frame processing apparatus 1 includes a first determination unit 12 in addition to the configuration shown in FIG. The first determination unit 12 determines whether or not the empty address read from the address storage unit 3 is stored in the first storage unit 10 as unused. When the empty address read from the address storage unit 3 is not unused, the first determination unit 12 outputs a first abnormality detection signal notifying the abnormality of the empty address read from the address storage unit 3 to the frame writing unit 4. When the first abnormality detection signal is received, the frame writing unit 4 discards the empty address read from the address storage unit 3 and redoes the empty address reading process.

  FIG. 4 is an explanatory diagram of the frame writing process in the frame processing apparatus 1 shown in FIG. In other embodiments, the following operations BA to BG may be steps.

  The processing of operations BA to BC is the same as that of operations AA to AC shown in FIG. In operation BD, the first determination unit 12 determines whether or not the empty address read from the address storage unit 3 is stored in the first storage unit 10 as unused. At this time, for example, the read address of the first storage unit 10 may be specified by an empty address read from the address storage unit 3. The first determination unit 12 may check whether or not the usage state read from the first storage unit 10 represents “unused (0)”.

  When the read empty address is unused (operation BD: Y), the process proceeds to operation BE. If the read empty address is not unused (operation BD: N), the processing returns to operation BB. As a result, the frame writing unit 4 discards the acquired empty address and redoes the process of reading the empty address from the address storage unit 3.

  The processing of operations BE to BG is the same as the processing of operations AD to AF shown in FIG. Further, the address detection unit 20 executes the operations AG to AI shown in FIG. 2 both when the empty address is discarded and when it is not discarded in the operation BD.

  According to this embodiment, when a free address read from the address storage unit 3 is already in use, the frame writing unit 4 is prevented from overwriting the frame with this address. Therefore, even if an abnormality occurs in the value of the buffer address read from the address storage unit 3, it is possible to eliminate the inconvenience that another frame is overwritten on the frame already stored in the buffer 2. In any of the embodiments described below, the first determination unit 12 may be provided.

  FIG. 5 is a diagram illustrating a third configuration example of the frame processing apparatus. The frame reading unit 5 includes a reading unit 30 and a reading control unit 31. Components that are the same as those shown in FIG.

  The read unit 30 receives the second read address from the read control unit 31. The reading unit 30 reads a frame from the buffer 2 using the received second read address as a read address. The read control unit 31 includes a read address determination unit 32 and a second determination unit 33.

  When the frame is written into the buffer 2, the read address determination unit 32 receives a write address at which the frame is written from the frame writing unit 4. The read address determination unit 32 stores the received address. The read address determination unit 32 selects a second read address from the stored addresses and outputs the second read address to the second determination unit 33.

  For example, the read address determination unit 32 may include a priority-specific address storage unit that stores addresses according to the priority of each frame stored in the buffer 2. At this time, the frame writing unit 4 may extract priority information from the frame and give it to the read address determination unit 32. The priority information may be, for example, quality of service (QoS).

  The read address determination unit 32 may store the frame in the priority-specific address storage unit according to the priority information. The read address determination unit 32 may determine the output order of addresses according to the priority assigned to the priority-specific address storage unit.

  The second determination unit 33 determines whether the second read address output from the read address determination unit 32 is stored in the first storage unit 10 when it is unused. For example, the second determination unit 33 reads the usage state from the first storage unit in which the read address is designated by the second read address. The second determination unit 33 determines whether or not the read usage state indicates “unused (0)”. When the read usage state indicates “unused (0)”, the second determination unit 33 discards the second read address.

  FIG. 6 is an explanatory diagram of the frame reading process in the frame processing apparatus 1 shown in FIG. In other embodiments, the operations CA to CE described below may be steps.

  In operation CA, the read address determination unit 32 determines the second read address. In operation CB, the second determination unit 33 determines whether or not the second read address is stored in the first storage unit 10 when it is unused. When the second read address is unused and stored in the first storage unit 10 (operation CB: Y), the process ends. For this reason, the second read address is not used. That is, the second read address is discarded. If the second read address is unused and not stored in the first storage unit 10 (operation CB: N), the process proceeds to operation CC.

  In operation CC, the frame reading unit 5 changes the value representing the use state stored in the first storage unit 10 for the second read address to the value “0” representing “unused”. In operation CD, the frame reading unit 5 stores the second reading address in the address storage unit 3. In operation CE, the reading unit 30 reads a frame from the buffer 2. The operations CC to CE may be executed in any order.

  According to this embodiment, it is possible to determine whether or not a valid frame is stored in the second read address used for reading a frame from the buffer 2. For this reason, even if an abnormality occurs in the second read address, the inconvenience that the already read frames are read redundantly is solved. Note that the frame reading unit 5 shown in FIG. 5 may be provided in another embodiment described in this specification.

  FIG. 7 is a diagram illustrating a fourth configuration example of the frame processing apparatus. The frame processing apparatus 1 includes an address input unit 21 in addition to the configuration shown in FIG. The address input unit 21 stores the address detected by the address detection unit 20 in the address storage unit 3.

  The address detection unit 20 detects a buffer address that has disappeared from the storage in the address storage unit 3. Therefore, the address stored in the address storage unit 3 by the address input unit 21 is a buffer address lost from the storage in the address storage unit 3. According to the present embodiment, even if the address disappears from the storage of the address storage unit 3 due to an abnormality in the value of the buffer address read from the address storage unit 3, the lost address is restored to prevent the resource of the buffer 2 from being reduced. It becomes possible.

  FIG. 8 is a diagram illustrating a fifth configuration example of the frame processing device. The address detection unit 20 includes a second storage unit 40, a first input unit 41, a second input unit 42, and a detection unit 43. The same components as those shown in FIG. 7 are denoted by the same reference numerals.

  The second storage unit 40 stores a variable for each buffer address. The second storage unit 40 has a storage capacity for storing variables for each of the N buffer addresses. For example, the second storage unit 40 may have a storage capacity of N bits. The storage destination for storing the variable for each of the N buffer addresses is specified by an N-value address. Each storage destination address may be, for example, “0” to “N−1”. In the following description, a variable stored in the second storage unit 40 for the buffer address may be referred to as “a variable related to the buffer address”.

  The variable stored for each buffer address can have at least a first predetermined value and a second predetermined value. For example, the first predetermined value may be “1” and the second predetermined value may be “0”.

  In each of the following embodiments, the variables related to the buffer addresses “0” to “N−1” are stored in the addresses “0” to “N−1” of the second storage unit 40, respectively. However, it is sufficient for the second storage unit 40 to be able to store variables for each buffer address. As the second storage unit 40, various configurations that can store variables for each buffer address can be employed.

  When it is determined that the usage state stored in the first storage unit 10 for a certain buffer address is “unused”, the first input unit 41 inputs a first predetermined value “1” to a variable related to the buffer address. To do. When a frame is written to a certain buffer address, the second input unit 42 inputs a second predetermined value “0” to a variable related to this buffer address.

  The detection unit 43 detects a buffer address in which the variable continues to have the first predetermined value over a period in which the first read address makes a round.

  The value of the variable relating to a certain buffer address being the first predetermined value “1” means that a frame has not yet been written to this buffer address since it was previously determined that this buffer address was not used. means. The fact that the value of the variable relating to a certain buffer address is the second predetermined value “0” means that a frame has been written to this buffer address after it was previously determined that this buffer address was not used. Means.

  For example, the first input unit 41 may determine whether or not the use state stored in the first storage unit 10 for the buffer address having the same value as the current first read address is “unused (0)”. . When the use state stored in the first storage unit 10 for this buffer address is “unused (0)”, the first input unit 41 uses the second predetermined value “0” as the value of the variable related to this buffer address. It is determined whether or not there is. When the value of the variable related to the buffer address is the second predetermined value “0”, the first input unit 41 inputs the first predetermined value “1” as the value of this variable.

  On the other hand, when the use state stored for the buffer address having the same value as the current first read address is “unused (0)”, the detection unit 43 determines that the value of the variable related to this buffer address is the first predetermined value. It is determined whether or not “1”. The fact that the value of the variable relating to the buffer address remains at the first predetermined value “1” means that the first read address goes around once after the first predetermined value “1” is input to the variable. Also means that the second predetermined value “0” has not been input to the variable. This means that a frame has never been written to this buffer address over the course of the first read address.

  In this way, the detection unit 43 detects a buffer address in which the variable continues to have the first predetermined value over a period of one cycle of the first read address, and detects a buffer address that has disappeared from the storage in the address storage unit 3. . As in the first configuration example described with reference to FIGS. 1 and 2, the addresses are generated in a cyclic order so as to change in synchronization with the first read address, and each address of the address storage unit 3 is designated. Other possible cyclic addresses may be used instead of the first read address.

  FIG. 9 is an explanatory diagram of the frame writing process in the frame processing apparatus 1 shown in FIG. In other embodiments, the following operations DA to DH may be steps. The processing of operations DA to DE is the same as that of operations BA to BE shown in FIG.

  In operation DF, the second input unit 42 inputs the second predetermined value “0” to the variable related to the read empty address. The processing of operations DG and DH is the same as operations BF and BG shown in FIG. 4, respectively. Note that operations DE to DH may be executed in any order.

  FIG. 10 is an explanatory diagram of address abnormality detection processing in the frame processing apparatus 1 shown in FIG. In other embodiments, the following operations DI to DM may be steps. In operation DI, the first input unit 41 and the detection unit 43 read the usage state from the first storage unit 10 designated with the first read address as the read address, and the buffer address having the same value as the first read address is not yet read. It is determined whether or not it is in use. When the buffer address having the same value as the first read address is not unused (operation DI: N), the process ends. When the buffer address having the same value as the first read address is unused (operation DI: Y), the process proceeds to operation DJ.

  In operation DJ, the first input unit 41 and the detection unit 43 read a variable from the second storage unit 40 designated with the first read address as the read address. That is, the first input unit 41 and the detection unit 43 read a variable related to the buffer address having the same value as the first read address. In operation DK, the first input unit 41 and the detection unit 43 determine whether or not the value of the read variable is the second predetermined value “0”.

  When the value of the variable is the second predetermined value “0” (operation DK: Y), the processing proceeds to operation DL. When the value of the variable is not the second predetermined value “0” (operation DK: N), the process proceeds to operation DM.

  In operation DL, the first input unit 41 inputs a first predetermined value “1” to a variable relating to a buffer address having the same value as the first read address. In operation DM, the detection unit 43 detects a buffer address having the same value as the first read address as an abnormal address lost from the storage in the address storage unit 3.

  Next, the frame writing process in the frame processing apparatus 1 shown in FIG. 8 will be described by referring to the temporal changes of the address storage unit 3, the first storage unit 10, the second storage unit 40, and the buffer 2. FIG. 11 is an explanatory diagram of an initial state of the address storage unit 3, the first storage unit 10, the second storage unit 40, and the buffer 2 shown in FIG. In the following description, it is assumed that the buffer 2 can store 16 frames.

  In the initial state, all addresses in the buffer 2 are empty addresses. Therefore, all the addresses of the buffer 2 are stored in the address storage unit 3. In this example, buffer address values “0” to “15” are stored in the addresses “0” to “15” of the address storage unit 3, respectively. The usage states stored in the first storage unit 10 are all “unused (0)”. Further, the values of the variables stored in the second storage unit 40 are all the second predetermined value (0).

  FIG. 12 shows a state in which the sixth frame is stored in the buffer after the state shown in FIG. The position of the first read address which is the read address of the address storage unit 3 has advanced to “5”. Since the buffer address stored in the address “5” of the address storage unit 3 is “5”, the frame is written in the buffer address “5”.

  The operation state stored in the first storage unit 10 for the buffer address “5” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. The buffer address “5” where the frame is written has the same value as the first read address “5”. Therefore, in the determination of the operation DI shown in FIG. 10, the use state stored in the first storage unit 10 for the buffer address having the same value as the first read address is “in use (1)”. For this reason, the change of the variable of the 2nd memory | storage part 40 does not arise.

  FIG. 13 shows a state in which the eleventh frame is stored in the buffer after the state shown in FIG. The position of the first read address advances to “11”. Since the buffer address stored in the address “11” of the address storage unit 3 is “11”, the frame is written in the buffer address “11”. The operation state stored in the first storage unit 10 for the buffer address “11” is changed to “in use (1)” by the operation DE illustrated in FIG. 9.

  In the state shown in FIG. 13, the frame reading unit 5 reads the frame stored at the buffer address “3”. The frame reading unit 5 stores the buffer address “3” in the address storage unit 3. The buffer address “3” is stored in the address “0” having the earliest read order among the currently unused areas “0” to “10” of the address storage unit 3. Similarly to the operation CC shown in FIG. 6, the use state stored in the first storage unit 10 for the buffer address “3” is changed to “unused (0)”.

  Next, the frame writing process of the frame processing apparatus 1 in the normal state after a certain amount of time has elapsed from the initial state will be described. FIG. 14 shows a state where a certain amount of time has elapsed from the initial state. The addresses “0” to “15” of the address storage unit 3 include buffer address values “3”, “14”, “1”, “8”, “5”, “7”, “15”, “9”. , “13”, “11”, “2”, “6”, “12”, “4”, “10”, and “0” are stored, respectively. The position of the first read address is currently “0”.

  Since the buffer address stored in the address “0” of the address storage unit 3 is “3”, the frame is written in the buffer address “3”. The operation state stored in the first storage unit 10 for the buffer address “3” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. Further, the second predetermined value “0” is input to the variable relating to the buffer address “3” by the operation DF shown in FIG.

  In the determination of the operation DI illustrated in FIG. 10, the use state stored in the first storage unit 10 for the buffer address “0” having the same value as the first read address is “unused (0)”. In the determination of the operation DK shown in FIG. 10, the value of the variable relating to the buffer address “0” is the second predetermined value (0).

  That the value of the variable relating to the buffer address “0” is the second predetermined value (0) means that the first read address is cycled after the first predetermined value (1) is input to this variable. This means that write processing has been executed for the buffer address “0”. Therefore, it is determined that the buffer address “0” is not an abnormal address lost from the storage in the address storage unit 3. In the operation DL shown in FIG. 10, the first predetermined value (1) is input to the variable relating to the buffer address “0” in order to detect the execution of the writing process during the next round of the first read address.

  FIG. 15 shows a state where the position of the first read address has advanced to “7” after the state shown in FIG. Since the buffer address stored in the address “7” of the address storage unit 3 is “9”, the frame is written in the buffer address “9”. The operation state stored in the first storage unit 10 for the buffer address “9” is changed to “in use (1)” by the operation DE shown in FIG.

  The use state stored in the first storage unit 10 for the buffer address “7” having the same value as the first read address is “in use (1)”. For this reason, the variable regarding the buffer address “7” does not change.

  The frame reading unit 5 reads the frame stored at the buffer address “14”. The frame reading unit 5 stores the buffer address “14” in the address storage unit 3. The buffer address “14” is stored in the address “0” having the earliest read order among the currently unused areas “0” to “6” of the address storage unit 3. Similarly to the operation CC shown in FIG. 6, the usage state stored in the first storage unit 10 for the buffer address “14” is changed to “unused (0)”.

  FIG. 16 shows a state where the position of the first read address has advanced to “10” after the state shown in FIG. Since the buffer address stored in the address “10” of the address storage unit 3 is “2”, the frame is written in the buffer address “2”. The operation state stored in the first storage unit 10 for the buffer address “2” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. Further, by the operation DF shown in FIG. 9, the second predetermined value “0” is input to the variable relating to the buffer address “2”.

  In the determination of the operation DI illustrated in FIG. 10, the use state stored in the first storage unit 10 for the buffer address “10” having the same value as the first read address is “unused (0)”. Further, in the determination of the operation DK shown in FIG. 10, the value of the variable relating to the buffer address “10” is the second predetermined value (0). Therefore, it is determined that the buffer address “10” is not an abnormal address lost from the storage in the address storage unit 3. In the operation DL shown in FIG. 10, the first predetermined value (1) is input to the variable relating to the buffer address “10” in order to detect the execution of the writing process during the next round of the first read address.

  FIG. 17 shows a state where the position of the first read address has advanced to “14” after the state shown in FIG. Since the buffer address stored in the address “14” of the address storage unit 3 is “10”, the frame is written in the buffer address “10”. The operation state stored in the first storage unit 10 for the buffer address “10” is changed to “in use (1)” by the operation DE shown in FIG.

  In the state shown in FIG. 16, the first predetermined value “1” is input to the variable relating to the buffer address “10”. In the state shown in FIG. 17, the value of this variable is reset to the second predetermined value “0” by operation DF shown in FIG. In this way, the variable relating to the buffer address “10” reflects the fact that the writing process occurred while the first read address makes a round after the state of FIG.

  Further, in the state shown in FIG. 15, since the buffer address “14” is returned to the address storage unit 3, the use state stored in the first storage unit 10 for the buffer address “14” is changed to “unused (0)”. changed. In the state shown in FIG. 17, in order to detect the execution of the writing process during the next round of the first read address, the first predetermined value (1) is set to the variable related to the buffer address “14” by the operation DL shown in FIG. ) Is entered.

  FIG. 18 shows a state where the position of the first read address has advanced to “15” after the state shown in FIG. Since the buffer address stored in the address “15” of the address storage unit 3 is “0”, the frame is written in the buffer address “0”. The operation state stored in the first storage unit 10 for the buffer address “0” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. Further, the value of the variable relating to the buffer address “0” is reset to the second predetermined value “0” by the operation DF shown in FIG.

  The frame reading unit 5 reads the frame stored in the buffer addresses “9”, “7”, and “11”. The frame reading unit 5 stores the buffer addresses “9”, “7”, and “11” in the address storage unit 3. Similarly to the operation CC shown in FIG. 6, the usage state stored in the first storage unit 10 for the buffer addresses “9”, “7”, and “11” is changed to “unused (0)”.

  FIG. 19 shows a state where the position of the first read address has returned to “0” after the state shown in FIG. Since the buffer address stored in the address “0” of the address storage unit 3 is “14”, the frame is written in the buffer address “14”. The operation state stored in the first storage unit 10 for the buffer address “14” is changed to “in use (1)” by the operation DE illustrated in FIG. 9.

  In the state shown in FIG. 17, the first predetermined value “1” is input to the variable relating to the buffer address “14”. In the state shown in FIG. 19, the value of this variable is reset to the second predetermined value “0” by the operation DF shown in FIG. 9, and the writing process occurs while the first read address makes a round after the state of FIG. 17. This fact is reflected in the variable relating to the buffer address “14”.

  In this way, in a normal state where no buffer address disappears, the abnormal address detection process in operation DM shown in FIG. 10 is not executed. That is, the state that “the buffer address having the same value as the first read address is unused and the value of the variable related to this address is the first predetermined value (1)” is not detected.

  Next, the frame writing process of the frame processing apparatus 1 in an abnormal state after a certain amount of time has elapsed from the initial state will be described. FIG. 20 shows a state in which a certain amount of time has elapsed from the initial state. The addresses “0” to “15” of the address storage unit 3 include buffer address values “3”, “14”, “3”, “8”, “5”, “7”, “15”, “9”. , “13”, “11”, “2”, “6”, “12”, “4”, “10”, and “0” are stored, respectively.

  The buffer address “1” originally intended to be stored in the address “2” of the address storage unit 3 has changed to “3” due to an abnormality. The position of the first read address is currently “0”.

  Since the buffer address stored in the address “0” of the address storage unit 3 is “3”, the frame is written in the buffer address “3”. The operation state stored in the first storage unit 10 for the buffer address “3” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. Further, the second predetermined value “0” is input to the variable relating to the buffer address “3” by the operation DF shown in FIG.

  In the determination of the operation DI illustrated in FIG. 10, the use state stored in the first storage unit 10 for the buffer address “0” having the same value as the first read address is “unused (0)”. In the determination of the operation DK shown in FIG. 10, the value of the variable relating to the buffer address “0” is the second predetermined value (0). The first predetermined value (1) is input to the variable relating to the buffer address “0” by the operation DL shown in FIG.

  FIG. 21 shows a state in which the position of the first read address has advanced to “2” after the state shown in FIG. The buffer address stored in the address “2” of the address storage unit 3 is “3”. In the determination of the operation DD shown in FIG. 9, the use state stored in the first storage unit 10 for the buffer address “3” is “in use (1)”. Therefore, the frame writing unit 4 detects an abnormality in the buffer address read from the address “2” in the address storage unit 3 and discards the buffer address.

  In the determination of the operation DI illustrated in FIG. 10, the use state stored in the first storage unit 10 for the buffer address “2” having the same value as the first read address is “unused (0)”. In the determination of the operation DK shown in FIG. 10, the value of the variable relating to the buffer address “2” is the second predetermined value (0). The first predetermined value (1) is input to the variable relating to the buffer address “2” by the operation DL shown in FIG.

  FIG. 22 shows a state where the position of the first read address has advanced to “15” after the state shown in FIG. Since the buffer address stored in the address “15” of the address storage unit 3 is “0”, the frame is written in the buffer address “0”. The operation state stored in the first storage unit 10 for the buffer address “0” is changed to “in use (1)” by the operation DE illustrated in FIG. 9. Further, the value of the variable relating to the buffer address “0” is reset to the second predetermined value “0”.

  The use state stored in the first storage unit 10 for the buffer address “15” having the same value as the first read address is “in use (1)”. For this reason, the variable relating to the buffer address “15” does not change.

  The frame reading unit 5 reads the frame stored in the buffer addresses “14”, “9”, “7”, and “11”. The frame reading unit 5 stores the buffer addresses “14”, “9”, “7”, and “11” in the address storage unit 3. Similarly to the operation CC shown in FIG. 6, the use state stored in the first storage unit 10 for the buffer addresses “14”, “9”, “7”, and “11” is set to “unused (0)”. Be changed.

  FIG. 23 shows a state in which the position of the first read address has returned to “0” and the position of the first read address has advanced to “1” after the state shown in FIG. Since the buffer address stored in the address “1” of the address storage unit 3 is “9”, the frame is written in the buffer address “9”. The operation state stored in the first storage unit 10 for the buffer address “9” is changed to “in use (1)” by the operation DE shown in FIG.

  In the determination of the operation DI illustrated in FIG. 10, the use state stored in the first storage unit 10 for the buffer address “1” having the same value as the first read address is “unused (0)”. Further, in the determination of the operation DK shown in FIG. 10, the value of the variable relating to the buffer address “1” is the first predetermined value (1). As a result, in operation DM shown in FIG. 10, it is detected that an abnormality has occurred in buffer address “1”. The address input unit 21 stores the buffer address “1” in the address storage unit 3.

  According to the present embodiment, it is possible to realize a frame processing device that can detect a lost buffer address from the storage of the address storage unit 3 and restore the lost address. Further, according to the present embodiment, it is possible to realize a frame processing apparatus that prevents overwriting of a stored frame with another frame even if an abnormality occurs in the value of the buffer address read from the address storage unit 3.

DESCRIPTION OF SYMBOLS 1 Frame processing apparatus 2 Buffer 3 Address memory | storage part 4 Frame writing part 10 1st memory | storage part 11 State change part 20 Address detection part

Claims (4)

A buffer,
An address storage unit for storing an empty address of the buffer;
A frame writing unit for writing a frame to the empty address read from the address storage unit by designating a read address by a cyclic address generated in a cyclic order;
A first storage unit for storing a use state of each address of the buffer;
A state changing unit that changes a use state stored in the first storage unit from an unused state to an in-use state for an address at which a frame is written when a frame is written to the buffer;
A frame processing apparatus comprising an address detection unit that detects an address stored in the first storage unit when the frame writing unit does not perform a writing process over a period of one cycle of the cyclic address and is unused. .   The frame processing apparatus according to claim 1, further comprising an address input unit that inputs an address detected by the address detection unit to the address storage unit. The address detecting unit is
A second storage unit for storing a variable for each address of the buffer;
A first input unit that puts a first predetermined value in the variable for the address stored in the first storage unit as unused;
A second input unit that, when a frame is written to the buffer, puts a second predetermined value in the variable for the address to which the frame is written;
A detecting unit for detecting an address in which the variable has the first predetermined value over a period of a round of the cyclic address;
The frame processing device according to claim 1 or 2. Store the free address of the buffer in the address storage unit,
By reading the empty address from the address storage unit by designating a read address by a cyclic address generated in a cyclic order,
When a frame is written to the free address, the use state of the free address stored in the first storage unit that stores the use state of each address of the buffer is changed from unused to used,
A frame processing method for detecting an address stored in the first storage unit when the frame writing process is not performed over a period of one cycle of the cyclic address and is unused.

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