JP2011234080A - Video display control apparatus and video monitoring apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a video display control apparatus capable of realizing a function of adjusting a video signal synchronized with a synchronization signal, at low cost.SOLUTION: A horizontal position detector 35 receives a digital video signal 31a and a horizontal synchronization pulse 31b, and outputs a video delay control signal 35a and a horizontal synchronization delay control signal 35b corresponding to a shift amount between a timing of the digital video signal 31a synchronized with the horizontal synchronization pulse 31b and a timing of the digital video signal 31a that is actually inputted. A delay selection circuit 46 for a video signal and a delay selection circuit 47 for a synchronization signal select any one output of flip-flop circuits 36-40 and flip-flop circuits 41-45, respectively, based on the delay control signal 35a, and output the selected output as a horizontal position adjusted digital video signal 32a and a horizontal position adjusted horizontal synchronization pulse 32b, respectively.

Description

  The present invention mainly relates to a video monitoring apparatus that digitally converts an NTSC video output (analog output) of a surveillance camera into a format that can be recorded by a digital recorder, and more particularly to an image display apparatus connected to the digital recorder. The present invention relates to a video display control apparatus and a video monitoring apparatus having means for automatically correcting the horizontal direction of an image when displaying a video.

  In recent years, video surveillance apparatuses composed of a camera unit and a recorder unit are widely installed in buildings and apartment houses. In such a video monitoring device, for example, an analog output camera (image size 640 pixels × 480 lines) that outputs an NTSC composite video signal in an elevator cabin, other entrances, hallways, etc. have an image size of 1280 pixels × 960 lines. Use a digital output camera that can handle. This is because the digital camera output is transmitted using an Ethernet (registered trademark; hereinafter omitted) cable, so it is impossible to transmit more than 100 m due to the characteristics of the Ethernet cable, and from the camera installed in the elevator car. This is because it is not suitable for the transmission distance (average 200 m).

  Therefore, conventionally, the video of the analog output camera has to be recorded by a digital recorder having an NTSC composite video signal interface, and the video of the digital output camera has to be recorded by a digital recorder having an Ethernet interface.

  On the other hand, if an A / D converter that converts an NTSC composite video signal to an Ethernet interface is used, the digital recorder can be supported only by the Ethernet interface. However, when conversion is performed using such an A / D converter, the video image may be displayed with a shift. For example, the video that is originally displayed on the image display device as shown in FIG. 6 (a) is displayed horizontally as shown in FIGS. 6 (b) and 6 (c) (the screen shown in FIG. 6 (b) is the screen). 6 (c) is shifted to the right, and the portion surrounded by the broken line in FIG. 6 (a) is not displayed, and the portion surrounded by the one-dot broken line in FIGS. 6 (b) and 6 (c). May appear black.

  FIG. 7 shows an NTSC composite video signal input to the A / D converter. In FIG. 7, the horizontal axis represents time, and the vertical axis represents signal amplitude (voltage). FIG. 7 (a) shows a normal case. However, as shown in FIG. 7 (b), when it is earlier in time than the normal video signal area, or when it is normal as shown in FIG. 7 (c). In some cases, the time is slower than the video signal area. The image display example shown in FIG. 6B occurs in the case of the state shown in FIG.

  As a device for coping with the case where the video signal area is shifted with respect to the horizontal synchronization signal and cannot be displayed correctly on the display device as described above, there has conventionally been a device disclosed in, for example, Patent Document 1. When storing video data in the line memory, this apparatus performs horizontal correction of video display by generating and storing a write start pulse at a timing adjusted for a phase shift in the horizontal direction. Further, even in the multi-screen display processing apparatus having the conventional image adjustment means described in Patent Document 2, the write control to the memory is performed as a result of adjusting the phase shift in the horizontal direction as in the apparatus described in Patent Document 1. The video display was corrected.

Japanese Patent No. 3067067 JP-A-10-112828

  In a video surveillance apparatus using an analog output camera having an NTSC composite video signal output, a phase difference occurs between the video horizontal sync signal and the video signal area due to the accuracy of the output circuit, and the phase difference varies. When a phase difference from the horizontal synchronizing signal is generated, the image that should originally be viewed is cut out on the image display device as shown in FIG. The function may not be satisfied.

In order to prevent such a problem, the conventional image display device has the image horizontal direction adjusting means in the display device. However, since the image display device is provided in the display device, the image display device can be used for image display after the horizontal correction. Therefore, it is necessary to store in an image memory such as a frame memory. Therefore, the circuit scale such as a memory write control circuit and a memory is not small, and there is a problem that the product price increases correspondingly.
In particular, when a plurality of cameras are connected, the display of the image display device may be divided. In such a case, a horizontal adjustment circuit is required according to the number of divisions, and there is a problem that the product price increases accordingly. It was.

  The present invention has been made to solve the above-described problems, and provides a video display control device and a video monitoring device capable of realizing a function of adjusting a video signal synchronized with a synchronization signal at low cost. With the goal.

  The video display control device according to the present invention is a video display control device that inputs a video signal and a synchronization signal, and outputs the video signal in synchronization with the synchronization signal, and the video signal based on the synchronization signal is predetermined. Position detection means for detecting the difference between the timing and the timing of the actual video signal, and when the position detection means detects the deviation, either the video signal or the synchronization signal is delayed as a video signal at a predetermined timing. Signal adjusting means for outputting.

  The video display control device according to the present invention delays either the video signal or the synchronization signal and detects the difference between the predetermined timing of the video signal based on the synchronization signal and the timing of the actual video signal. Since the video signal is output at the specified timing, the function of adjusting the video signal synchronized with the synchronization signal can be realized at low cost.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the image | video monitoring apparatus by Embodiment 1 of this invention. It is a block diagram which shows the A / D converter of the video monitoring apparatus by Embodiment 1 of this invention. It is a block diagram which shows the horizontal position detection part of the image | video monitoring apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the delay control table of the video monitoring apparatus by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the video monitoring apparatus horizontal position detection part by Embodiment 1 of this invention. It is explanatory drawing which shows the example of a display of the monitoring image of the video monitoring apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the relationship between the horizontal synchronizing signal and video signal of the video monitoring apparatus by Embodiment 1 of this invention. It is explanatory drawing of the operation | movement which correct | amends the phase shift of the horizontal synchronizing signal and video signal of the video monitoring apparatus by Embodiment 1 of this invention. It is a block diagram which shows the A / D converter of the video monitoring apparatus by Embodiment 2 of this invention.

Embodiment 1 FIG.
1 is a block diagram showing an image monitoring apparatus according to Embodiment 1 of the present invention.
The video monitoring apparatus shown in FIG. 1 includes an analog output camera 1, a digital output camera 2, an A / D converter 3, a digital recorder 4, and an image display device 5. The analog output camera 1 is a camera provided in, for example, an elevator car and outputs an NTSC composite video signal 1a. The digital output camera 2 is a camera installed at other entrances, corridors, and the like, and has an Ethernet signal 2a in a digital recorder format as an output. The A / D converter 3 is an A / D converter that converts the composite video signal 1a into an Ethernet signal 3a for the Ethernet interface. The details of the A / D converter 3 will be described later with reference to FIG. The digital recorder 4 is a recorder for recording video signals of the analog output camera 1 and the digital output camera 2. The image display device 5 is a display device that is connected to the digital recorder 4 via a video cable 4 a and is composed of a liquid crystal display device or a CRT for displaying video stored in the digital recorder 4.

FIG. 2 is a configuration diagram showing details of the A / D converter 3.
The illustrated A / D converter 3 includes an A / D converter 31, a video display control device 32, a format converter 33, and an Ethernet interface converter 34. The A / D converter 31 digitally converts the NTSC composite video signal 1a input from the analog output camera 1 with a video clock (not shown) synchronized with the video signal, and outputs it as a digital video signal 31a. A horizontal synchronization pulse 31b generated from a horizontal synchronization signal superimposed on the video signal is output. The video display control device 32 receives the digital video signal 31a output from the A / D converter 31 and the horizontal synchronization pulse 31b, and outputs the horizontal position adjusted digital video signal 32a and the horizontal position adjusted horizontal synchronization pulse 32b. Output. The format conversion unit 33 inputs the horizontal position adjusted digital video signal 32 a and the horizontal position adjusted horizontal synchronization pulse 32 b output from the video display control device 32, performs format conversion that can be recorded in the digital recorder 4, and outputs them. To do. The Ethernet interface conversion unit 34 outputs the format-converted video signal 33a output from the format conversion unit 33 as an Ethernet signal 3a that matches the Ethernet interface.

  The video display control device 32 includes a horizontal position detection unit (position detection means) 35, flip-flop circuits (Flip Flop) 36 to 45, a video signal delay selection circuit 46, and a synchronization signal delay selection circuit 47. The horizontal position detector 35 receives the digital video signal 31a and the horizontal synchronizing pulse 31b and detects the start of the video signal area, which will be described later with reference to FIG. The flip-flop circuits 36 to 40 are video signal delay circuits, and each output is input to the video signal delay selection circuit 46. The flip-flop circuits 41 to 45 are synchronization signal delay circuits, and each output is input to the synchronization signal delay selection circuit 47. The video signal delay selection circuit 46 selects one of the outputs of the flip-flop circuits 36 to 40 or the digital video signal 31a based on the video delay control signal 35a output from the horizontal position detector 35, and the horizontal position has been adjusted. It is a circuit that outputs as a digital video signal 32a. Further, the synchronization signal delay selection circuit 47 selects one of the outputs of the flip-flop circuits 41 to 45 or the horizontal synchronization pulse 31b based on the horizontal synchronization delay control signal 35b output from the horizontal position detector 35, and performs horizontal operation. It is a circuit that outputs as a position-adjusted horizontal synchronizing pulse 32b. The flip-flop circuits 36 to 45, the video signal delay selection circuit 46, and the synchronization signal delay selection circuit 47 constitute a signal adjustment means.

Although not shown in FIG. 2, the A / D conversion unit 31, the horizontal position detection unit 35, the flip-flop circuits 36 to 45, the video signal delay selection circuit 46, the synchronization signal delay selection circuit 47, and the format conversion unit. A video clock having the same cycle as that of the digital video signal data is supplied to 33 in synchronization with the video signal, and a clock synchronized with Ethernet transmission is supplied to the format conversion unit 33 and the Ethernet interface conversion unit 34.
In FIG. 2, five flip-flop circuits 36 to 45 for delaying are provided for the digital video signal (36 to 40) and five for the horizontal synchronizing pulse signal (41 to 45). Is an example and the number provided is not limited to five. Further, although a flip-flop circuit is used as the delay circuit, other structures may be used as long as they have the same function.

FIG. 3 is a block diagram of the horizontal position detector 35 shown in FIG.
As shown in FIG. 3, the horizontal position detection unit 35 includes a separation circuit 351, an amplitude comparator 352, a counter 353, a latch circuit 354, a difference unit 355, and a delay control signal generation unit 356. The separation circuit 351 is a circuit that receives the digital video signal 31a and separates the luminance signal (Y) and the color difference signals (Cb, Cr), and outputs the luminance signal (Y) 351a. The amplitude comparator 352 receives the luminance signal (Y) 351a output from the separation circuit 351, compares the amplitude value with a preset threshold A357, and the luminance signal (Y) 351a exceeds the threshold A357. Outputs a significant signal 352a. The counter 353 is, for example, a 10-bit counter, receives the video clock 358, counts the video clock 358, and outputs the count value 353a. Further, the horizontal synchronization pulse 31b is input, and the count value 353a is cleared based on the horizontal synchronization pulse 31b.

  The latch circuit 354 is a circuit that latches the count value 353a output from the counter 353 and outputs the latched value 354a when the significant signal 352a output from the amplitude comparator 352 is input. The differentiator 355 calculates a difference between the value 354a output from the latch circuit 354 and a threshold value B359 provided in advance, and outputs the calculated difference value 355a. The delay control signal generation unit 356 has a delay control table 360 as shown in FIG. 4, and the video delay control signal 35a corresponding to the difference value 355a output from the differentiator 355 with reference to the delay control table 360. The horizontal synchronization delay control signal 35b is output. The delay control table 360 shown in FIG. 4 shows the video delay and the horizontal synchronization delay with respect to the difference value, and the video delay (Video_delay0 to Video_delay5) and the horizontal synchronization delay corresponding to each difference value (−5 to +5). Values of (Hsync_delay5 to Hsync_delay0) are registered.

Next, the operation of the video monitoring apparatus according to the first embodiment will be described.
First, the composite video signal 1 a is output from the analog output camera 1 and input to the A / D converter 3. In the A / D converter 3, the A / D converter 31 separates the digital video signal 31a and the horizontal synchronizing pulse 31b from the composite video signal 1a and outputs them. The digital video signal 31a and the horizontal synchronization pulse 31b are input to the video display control device 32 and input to the horizontal position detector 35, the digital video signal 31a is input to the flip-flop circuit 36, and the horizontal synchronization pulse 31b is input to the flip-flop. Input to the circuit 41.

The horizontal position detector 35 detects a horizontal shift based on the input digital video signal 31a and the horizontal synchronization pulse 31b.
FIG. 5 is a flowchart showing the operation of the horizontal position detector 35.
First, the separation circuit 351 separates the luminance signal (Y) from the digital video signal 31a and outputs it as the luminance signal (Y) 351a (step ST1). Further, when the horizontal synchronization pulse 31b is input (the horizontal synchronization pulse 31b becomes significant) (step ST2), it is cleared (count value = 0) (step ST3). On the other hand, when there is no input of the horizontal synchronization pulse 31b in step ST2, the counter 353 counts up according to the input video clock 358 (step ST4).

  The amplitude comparator 352 compares the input luminance signal (Y) 351a with the threshold value A357, and if the luminance signal (Y) 351a> the threshold value A357, the signal that becomes a significant signal 352a (for example, an amplitude level “H”). ) Is output (step ST5). The latch circuit 354 holds the count value 353a output from the counter 353 at the rising edge of the significant signal 352a output from the amplitude comparator 352, and uses this as a value 354a (a value corresponding to the video signal region start position). It outputs to the differentiator 355. The differencer 355 calculates the difference between the value 354a and the threshold value B359 (step ST6), and outputs the difference value 355a to the delay control signal generation unit 356. The delay control signal generation unit 356 refers to the delay control table 360 to determine the video delay control signal 35a and the horizontal synchronization delay control signal 35b (steps ST7 and ST8). That is, if the difference value 355a is a positive value, the control signal is output so that the video signal side is delayed, and if the difference value 355a is a negative value, the horizontal synchronization signal side is delayed. For example, when the difference value 355a is −5, the video delay control signal 35a indicates 0, and the horizontal synchronization delay control signal 35b indicates 5.

  Here, in the amplitude comparator 352, when the significant signal output when the luminance signal (Y) 351a exceeds the threshold A357 is the amplitude level “L”, the latch circuit 354 causes the significant signal to rise. Needless to say, hold at the falling edge.

Next, the operation of the video display control device 32 will be described.
The digital video signal 31a is input to the flip-flop circuit 36, and is input to the video signal delay selection circuit 46 and the subsequent flip-flop circuit 37 after being delayed by one cycle of the video clock synchronized with the video signal. The same operation is performed for the flip-flop circuit 37 to the flip-flop circuit 40, and the digital video signal 40a (Video_delay5) output from the flip-flop circuit 40 is in response to the digital video signal 31a (Video_delay0) input to the flip-flop circuit 36. The video clock is delayed by 5 cycles. Note that Video_delay0 to Video_delay5 (digital video signal 40a) in FIG. 2 correspond to the video delay field values (Video_delay0 to Video_delay5) in the delay control table 360 shown in FIG.

  On the other hand, the horizontal sync pulse 31b input to the video display control device 32 is input to the flip-flop circuit 41, and is delayed by one cycle of the video clock synchronized with the video signal to be delayed by the sync signal delay selection circuit 47 and the subsequent flip-flop. Is input to the circuit 42. The same operation is performed for the flip-flop circuit 42 to the flip-flop circuit 45, and the horizontal synchronization pulse 45a (Hsync_delay5) output from the flip-flop circuit 45 is in response to the horizontal synchronization pulse 31b (Hsync_delay0) input to the flip-flop circuit 41. The video clock is delayed by 5 cycles. Note that Hsync_delay0 to Hsync_delay5 (horizontal synchronization pulse 45a) in FIG. 2 correspond to the horizontal synchronization delay field values (Hsync_delay0 to Hsync_delay5) of the delay control table 360 shown in FIG.

  Each output of the flip-flop circuits 36 to 40 provided for the digital video signal 31a is input to the video signal delay selection circuit 46, and the flip-flop circuit corresponding to the video delay control signal 35a output from the horizontal position detector 35. The output is selected and output to the format conversion unit 33 as the digital video signal 32a whose horizontal position has been adjusted. For example, when the video delay control signal 35a indicates 1, the operation of the video signal delay selection circuit 46 is determined in advance so that the output of the flip-flop circuit 36 is selected.

  On the other hand, the outputs of the flip-flop circuits 41 to 45 provided for the horizontal synchronization pulse 31b are input to the synchronization signal delay selection circuit 47 and correspond to the horizontal synchronization delay control signal 35b output from the horizontal position detector 35. The flip-flop circuit output is selected and output to the format conversion unit 33 as the horizontal position adjusted horizontal synchronization pulse 32b. For example, when the horizontal synchronization delay control signal 35b indicates 2, the operation of the synchronization signal delay selection circuit 47 is determined in advance so that the output of the flip-flop circuit 42 is selected.

  The format conversion unit 33 to which the horizontal position adjusted digital video signal 32a and the horizontal position adjusted horizontal synchronization pulse 32b are input performs conversion into a predetermined format. Further, after being converted into an Ethernet signal by the Ethernet interface conversion unit 34, the Ethernet signal 3 a is transmitted to the digital recorder 28, and the image whose horizontal direction is adjusted is displayed on the image display device 5 connected to the digital recorder 4.

  FIG. 6 is an explanatory diagram showing an image in a normal state and an image in which a shift has occurred, in which (a) is normal, (b) is shifted in the horizontal direction (right) with respect to the normal state, (c) Shows a state shifted in the horizontal direction (left) with respect to the normal state. FIG. 7 is an explanatory diagram showing the relationship between the horizontal synchronization signal and the video signal region. With respect to the phase relationship between the normal horizontal synchronization signal 70 and the video signal region 71 shown in FIG. Indicates that the video signal area 73 is displayed earlier than the horizontal synchronization signal 72 by the time of the shift amount 74, and (c) is displayed later than the horizontal synchronization signal 75 by the time of the shift 77. It is shown that. FIG. 8 is a diagram for explaining the correction of the shifted horizontal position using the digital video signal 31a output from the A / D converter 31 and the horizontal synchronization pulse 31b.

For example, as shown in FIG. 7B, the operation when the video signal area is earlier in time than the normal state shown in FIG. 7A will be described for the digital video signal 31a obtained from the composite video signal 1a. . At this time, the image displayed on the image display device 5 is in the state shown in FIG.
The output of the A / D converter 31 corresponding to FIG. 7B is shown in FIG. In the example of FIG. 8 (1b), the video image is output two cycles earlier than the normal state of the digital video signal shown in FIG. 8 (1a). This is set as a deviation amount 74 = + 2. Since this deviation amount 74 can be expressed by the time from the horizontal synchronization pulse, in order to correct the deviation amount 74, if the output of the flip-flop circuit 37 is selected, a normal state is obtained.

Next, for example, when the digital video signal 31a obtained from the composite video signal 1a is later in time than the normal state shown in FIG. 7A, as shown in FIG. Will be described. At this time, the image displayed on the image display device 5 is in the state shown in FIG.
The output of the A / D converter 31 corresponding to FIG. 7C is shown in FIG. In the example of FIG. 8 (2b), the digital video signal shown in FIG. 8 (2a) is output late by two cycles of the video clock with respect to the normal state. This amount of shift is 77 = −2. Since this deviation amount 77 can be expressed by the time from the horizontal synchronization pulse, to correct the deviation amount 77, if the output of the flip-flop circuit 42 is selected, a normal state is obtained. That is, as shown in FIG. 8C, by delaying the horizontal synchronization pulse 31b by an amount corresponding to the shift amount 77, the phase relationship between the horizontal synchronization pulse 31b and the digital video signal 31a becomes a normal relationship.

  As described above, according to the video display control apparatus of the first embodiment, a video display control apparatus that inputs a video signal and a synchronization signal and outputs the video signal in synchronization with the synchronization signal. A position detection unit that detects a deviation between a predetermined timing of the video signal based on the video signal and a timing of the actual video signal, and when the deviation is detected by the position detection unit, either the video signal or the synchronization signal is delayed, Since the signal adjustment means for outputting the video signal at the determined timing is provided, the function of adjusting the video signal synchronized with the synchronization signal can be realized at low cost.

  In addition, according to the video display control apparatus of the first embodiment, the signal adjustment means includes a plurality of serially connected video signal delay circuits for inputting video signals and a plurality of serially connected synchronization signals for inputting synchronization signals. A signal delay circuit, a video signal selection circuit for selecting one of the outputs of the plurality of video signal delay circuits, and a synchronization signal selection circuit for selecting one of the outputs of the plurality of synchronization signal delay circuits. If the actual video signal timing is earlier than the predetermined timing of the video signal based on the synchronization signal, the video signal selection circuit corresponds to the shift amount. When the output of the signal delay circuit is selected and the timing of the actual video signal is later than the predetermined timing of the video signal based on the synchronization signal, the synchronization signal selection circuit adjusts the deviation amount. Since the output of the synchronization signal delay circuit is selected, the memory is not used to correct the position of the shift, and the delay circuit and the delay circuit output selection circuit are used. It is possible to realize a video signal adjustment function at low cost.

  Further, according to the video display control apparatus of the first embodiment, the position detection unit includes a difference unit that calculates a difference value between a predetermined timing of the video signal based on the synchronization signal and a timing of the actual video signal. A delay amount control that has a difference control table that indicates the relationship between the difference value and the delay amount in advance and outputs a delay control signal that indicates the delay amount corresponding to the difference value obtained by the difference means with reference to the difference control table Therefore, a highly accurate delay control signal can be obtained with a simple configuration, and therefore the video signal can be adjusted with high accuracy.

  Further, according to the video monitoring apparatus of the first embodiment, the video display control apparatus is used, the video display control apparatus acquires the video signal and the synchronization signal separately from the output signal of the analog output camera, and the video Since the image display device that displays the video based on the video signal from the display control device is provided, even when there is a shift between the video signal and the synchronization signal as the output of the analog output camera, the shift can be easily corrected.

  In addition, according to the video monitoring apparatus of the first embodiment, the A / D converter that extracts the digital video signal and the synchronization pulse from the output of the analog output camera is provided, and each of the digital video signal and the synchronization pulse is a video display control apparatus. Since the position detection means calculates the shift amount using the digital video signal as the video signal and the synchronization pulse as the synchronization signal, the digital video signal is input to the video signal delay circuit and the synchronization signal delay circuit. Even if a deviation occurs between the sync pulse and the sync pulse, the deviation can be easily corrected.

Embodiment 2. FIG.
FIG. 9 is a block diagram showing a video monitoring apparatus according to Embodiment 2 of the present invention.
The video display control device and the video monitoring device according to the second embodiment are configured to input a horizontal position correction instruction signal 90 from the outside to the horizontal position detection unit 350 in the video display control device 320 of the A / D converter 30. Only when the horizontal position correction instruction signal 90 is valid, delay selection by the horizontal position detection unit 350 is performed. When the horizontal position correction instruction signal 90 from the outside is invalid, the current video delay control signal 35a and horizontal synchronization delay The control signal 35b is held. As a specific method for realizing the horizontal position detection unit 350, for example, the delay control signal generation unit 356 shown in FIG. 3 performs the control signal update process only when the horizontal position correction instruction signal 90 is valid. When the horizontal position correction instruction signal 90 is not valid, the generated video delay control signal 35a and horizontal synchronization delay control signal 35b are held as they are. The other configuration in the A / D converter 30 is the same as the configuration in the A / D converter 3 in the first embodiment shown in FIG. The description is omitted.

  In the video monitoring apparatus according to the second embodiment configured as described above, for example, an operation device (not shown) is added on the A / D converter 30 and the user can arbitrarily operate the operation device. It is possible to make the horizontal position adjustment by making the horizontal position correction instruction signal 90 valid at the timing. For this reason, it is possible to prevent malfunction of the video display control device 320 that performs horizontal position correction due to noise superimposed on the NTSC composite video signal 1a output from the analog output camera 1 (see FIG. 1), or the horizontal position. Since the horizontal position adjustment can be performed only when an image suitable for the adjustment (the luminance level is large) is captured, the horizontal position adjustment can be performed efficiently and accurately.

  As described above, according to the video display control apparatus of the second embodiment, the position detection unit includes a unit that receives a position correction instruction from the outside, and calculates a deviation amount when the position correction instruction is received. When the correction instruction has not been received, the state of the delay control signal generated before that time is retained, so that malfunction due to noise superimposed on the input signal can be prevented, and position adjustment can be performed efficiently and It can be performed with high accuracy.

  In the first and second embodiments, the case where a shift occurs in the horizontal direction has been described. However, in the case where an image is displayed in synchronization with the vertical synchronization signal, the same applies to the shift in the vertical direction.

  DESCRIPTION OF SYMBOLS 1 Analog output camera, 1a Composite video signal, 2 Digital output camera, 3,30 A / D converter, 3a Ethernet signal, 4 Digital recorder, 5 Image display apparatus, 31 A / D conversion part, 31a Digital video signal, 31b Horizontal synchronization pulse, 32, 320 Video display control device, 32a Horizontal position adjusted digital video signal, 32b Horizontal position adjusted horizontal synchronization pulse, 33 Format conversion unit, 34 Ethernet interface conversion unit, 35, 350 Horizontal position detection unit, 35a Video delay control signal, 35b horizontal synchronization delay control signal, 36-45 flip-flop circuit, 46 video signal delay selection circuit, 47 synchronization signal delay selection circuit, 90 horizontal position correction instruction signal, 351 separation circuit, 351a luminance signal, 352 Amplitude comparator, 3 2a significant signal, 353 counter, 353a count value, 354 latch circuit, 354a value, 355 differencer, 355a difference value, 356 delay control signal generator, 357 threshold A, 358 video clock, 359 threshold B, 360 delay control table .

Claims (6)

A video display control device that inputs a video signal and a synchronization signal and outputs the video signal in synchronization with the synchronization signal,
Position detecting means for detecting a difference between a predetermined timing of the video signal based on the synchronization signal and a timing of the actual video signal;
A video display control device comprising: a signal adjusting unit that delays either the video signal or the synchronization signal and outputs the delayed video signal as the video signal at the predetermined timing when a shift is detected by the position detecting unit. The signal adjustment means includes a plurality of serially connected video signal delay circuits for inputting video signals, a plurality of serially connected synchronization signal delay circuits for inputting synchronization signals, and the plurality of video signal delay circuits. A selection circuit for a video signal for selecting one of the outputs, and a selection circuit for a synchronization signal for selecting one of the outputs of the plurality of delay circuits for the synchronization signal,
If the actual video signal timing is earlier than the predetermined timing of the video signal based on the synchronization signal, the degree of deviation detected by the position detecting means corresponds to the amount of deviation. If the output of the video signal delay circuit is selected and the timing of the actual video signal is later than the predetermined timing of the video signal based on the synchronization signal, the synchronization signal selection circuit sets the shift amount to the amount of deviation. 2. The video display control apparatus according to claim 1, wherein an output of a corresponding synchronizing signal delay circuit is selected.   The position detection means includes a difference means for calculating a difference value between a predetermined timing of the video signal based on the synchronization signal and a timing of the actual video signal, and a difference control table indicating a relationship between the difference value and the delay amount in advance. And a delay amount control means for outputting a delay control signal indicating a delay amount corresponding to the difference value obtained by the difference means with reference to the difference control table. Or the video display control apparatus of Claim 2.   The position detection means includes means for receiving a position correction instruction from the outside. When the position correction instruction is received, the amount of deviation is calculated. When the position correction instruction is not received, the delay control generated before that is calculated. 4. The video display control device according to claim 3, wherein the state of the signal is maintained.   The video display control device according to any one of claims 1 to 4, wherein the video display control device acquires the video signal and the synchronization signal separately from the output signal of the analog output camera, and A video monitoring device comprising an image display device for displaying a video based on a video signal from the video display control device. An A / D converter that extracts the digital video signal and sync pulse from the output of the analog output camera is provided.
The digital video signal and the sync pulse are respectively input to the video signal delay circuit and the sync signal delay circuit of the video display control device, and the position detection means uses the digital video signal as the video signal and the sync pulse as the sync pulse. 6. The video monitoring apparatus according to claim 5, wherein a shift amount is calculated as a synchronization signal.

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