JP2011232787A - Designing device, designing method and program for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a designing device for a semiconductor integrated circuit capable of eliminating the possibility that an operational failure might occur due to the difference between operational results of the semiconductor integrated circuit before and after a insertion FF is inserted when a clock-gated insertion FF for compensating a hold error is connected between a clock-gated front stage FF and a clock-gated subsequent stage FF.SOLUTION: A designing method for a semiconductor integrated circuit according to the present invention comprises the steps of: newly connecting a clock-gated insertion FF between a clock-gated front stage FF and a clock-gated subsequent stage FF; and determining a clock gating cell to be inputted into the insertion FF depending on types of the clock-gating cells corresponding to the front stage FF and the subsequent stage FF.

Description

  The present invention relates to a semiconductor integrated circuit design apparatus, design method, and program.

  In LSI design, data is transferred by synchronizing the functional blocks with flip-flops. On the other hand, after the LSI layout is generated, a delay test is performed by simulation or the like to check whether the hold time is defined between flip-flops. The location where a hold error has occurred in this inspection is dealt with by providing a circuit for generating a delay or inserting a flip-flop operating with a reverse phase clock. Such a technique is disclosed in Patent Document 1, Patent Document 2, and the like.

  For example, FIG. 24 and FIG. 27 show a semiconductor integrated circuit having two flip-flops clock-gated and inserting a new clock-gated flip-flop between the flip-flops to avoid a hold error. A design example is shown.

  First, FIG. 24 shows a configuration of the semiconductor integrated circuit 1 before the flip-flop is inserted. As shown in FIG. 24, the semiconductor integrated circuit 1 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2.

  The flip-flop FF1 inputs data from the previous circuit to the data input terminal D. Then, the data input to the data input terminal D is latched according to the gating clock signal GCLK1 input to the clock input terminal, and is output as the data A to the data output terminal Q.

  The data A is input to the data input terminal D of the flip-flop FF2 as data B through the logic circuit 10 that performs a predetermined logic operation. Then, the flip-flop FF2 latches the data B in accordance with the gating clock signal GCLK2 input to the clock input terminal and outputs it to the data output terminal Q.

  Here, each of the clock gating cells CGC1 and CGC2 includes a flip-flop FF11 and an AND circuit AND11. FIG. 25 shows a single unit configuration of the clock gating cell CGC1 and a timing chart for explaining the operation thereof.

  The flip-flop FF11 inputs the enable signal EN1 to the data input terminal D. In addition, a clock signal having a phase opposite to that of the reference clock CLK (half cycle shifted) is input to the clock input terminal. The flip-flop FF11 latches the enable signal EN1 according to the clock signal input to the clock input terminal, and outputs it from the data output terminal Q.

  The AND circuit AND11 inputs a reference clock to one input terminal, and inputs data from the data output terminal Q of the flip-flop FF11 to the other input terminal. The product is calculated and output from the output terminal.

  As shown in FIG. 25, before time t1, the enable signal EN1 is at a high level, and the output data of the flip-flop FF11 is also at a high level. Therefore, a gating clock signal GCLK1 having the same phase as the reference clock input to the other input terminal is output from the output terminal of the AND circuit AND11.

  At time t1, the enable signal EN1 falls to the low level. Thereafter, corresponding to the rising edge of the clock signal having a reverse phase (shifted by a half cycle) of the reference clock CLK, the output data of the flip-flop FF11 also becomes low level at time t2. For this reason, the output of the AND circuit AND11 is fixed at the low level.

  At time t3, the enable signal EN1 rises again to the high level. After that, the output data of the flip-flop FF11 also becomes high level at time t4 corresponding to the rising edge of the clock signal having the opposite phase (half cycle shifted) of the reference clock CLK. Thereafter, as in the case before time t1, the output of the AND circuit AND11 is the gating clock signal GCLK1 having the same phase as the reference clock.

  The same applies to the clock gating cell CGC2 except that the enable signal EN1 is replaced with EN2 and the gating clock signal GCLK2 is replaced with GCLK1 in the above description. Hereinafter, a clock gating cell having the same configuration as the clock gating cells CGC1 and CGC2 is referred to as an “AND type clock gating cell”.

  FIG. 26 is a timing chart for explaining the operation of the semiconductor integrated circuit 1 of FIG. However, in this operation timing chart, it is assumed that no hold error occurs and the semiconductor integrated circuit 1 performs an ideal operation. Below, it demonstrates on the assumption.

  As shown in FIG. 26, the flip-flop FF1 latches the data input to the data input terminal D in response to the rise of the gating clock signal GCLK1 at time t1, and outputs the data as data A1 from the data output terminal. The data A1 is input as data B1 to the flip-flop FF2 via the logic circuit 10.

  At time t2, the enable signal EN1 falls to the low level. For this reason, the gating clock signal GCLK1 is fixed at the low level, and the output data from the flip-flop FF1 is also fixed at the data A1. Similarly, data input from the logic circuit 10 to the flip-flop FF2 is also fixed to the data B1.

  On the other hand, the enable signal EN2 is at a high level before time t5. Therefore, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 at times t1, t3, and t4. Therefore, the flip-flop FF2 latches and outputs the data B1 in response to the rising of the gating clock signal GCLK2 at times t3 and t4.

  At time t5, the enable signal EN2 falls to the low level. For this reason, the gating clock signal GCLK2 is fixed to the low level. Therefore, the output of the flip-flop FF2 is fixed at the data B1 latched at time t4.

  At time t6, the enable signal EN1 rises to a high level. For this reason, the gating clock signal GCLK1 in phase with the reference clock is output from the clock gating cell CGC1 again. In response to the rising edge of the gating clock signal GCLK1, data A6, A7, A8, A9... Are output from the flip-flop FF1 at times t7, t9, t10, t11. The data A6, A7, A8, A9,... Are input as data B6, B7, B8, B9,.

  On the other hand, the enable signal EN2 rises to a high level at time t8. For this reason, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 again. Then, at times t9, t10, t11,..., The flip-flop FF2 latches the data B6, B7, B8,... From the logic circuit 10 in response to the rising edge of the gating clock signal GCLK2. ,Output.

  However, when the semiconductor integrated circuit 1 of FIG. 24 does not have the ideal operation as described above and a hold error occurs, a clock having a phase opposite to the reference clock CLK (shifted by a half cycle) is provided between the flip-flops FF1 and FF2. A flip-flop synchronized with the signal is connected to perform hold error compensation.

  FIG. 27 shows the configuration of the semiconductor integrated circuit 1 after the flip-flop is inserted. As shown in FIG. 27, the semiconductor integrated circuit 1 includes flip-flops FF1, FF2, and FF3, and clock gating cells CGC1 and CGC2. The semiconductor integrated circuit 1 in FIG. 27 differs from that in FIG. 24 in that a flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2. In order to avoid a hold error, the flip-flop FF3 inputs a clock signal having a phase opposite to that of the gating clock signal GCLK2 output from the clock gating cell CGC2 (shifted by a half cycle) to the clock input terminal.

  FIG. 28 is a timing chart for explaining the operation of the semiconductor integrated circuit 1 of FIG. As shown in FIG. 27, at time t1, the flip-flop FF1 latches the data input to the data input terminal D according to the rise of the gating clock signal GCLK1, and outputs the data as data A1 from the data output terminal. This data A1 is input as data B1 to the flip-flop FF3 via the logic circuit 10.

  At time t2, the enable signal EN1 falls to the low level. For this reason, the gating clock signal GCLK1 is fixed at the low level, and the output data from the flip-flop FF1 is also fixed at the data A1. Similarly, data input to the flip-flop FF3 is also fixed to data B1.

  On the other hand, the enable signal EN2 is at a high level before time t7. Therefore, the gating clock signal GCLK2 having the rising edge at the times t1, t4, and t6 and having the same phase as the reference clock is output.

  Here, as described above, the flip-flop FF3 inputs the clock signal GCLK2B having a phase opposite to that of the gating clock signal GCLK2 (shifted by a half cycle) to the clock input terminal. Therefore, the flip-flop FF3 latches and outputs the data B1 from the logic circuit 10 in response to the rise of the gating clock signal GCLK2B at times t3, t5, and t8.

  Further, the flip-flop FF2 latches and outputs the data B1 from the flip-flop FF3 in response to the rising of the gating clock signal GCLK2 at times t4 and t6.

  At time t7, the enable signal EN2 falls to the low level. For this reason, the gating clock signal GCLK2 is fixed to the low level and the gating clock signal GCLK2B is fixed to the high level. Therefore, the output of the flip-flop FF3 is fixed at the data B1 latched at time t8. The output of the flip-flop FF2 is fixed at the data B1 latched at time t6.

  At time t9, the enable signal EN1 rises to a high level. For this reason, the gating clock signal GCLK1 in phase with the reference clock is output from the clock gating cell CGC1 again. In response to the rising edge of the gating clock signal GCLK1, data A6, A7, A8, A9... Are output from the flip-flop FF1 at times t10, t12, t14, t16. The data A6, A7, A8, A9,... Are inputted as data B5, B6, B7, B8, B9,.

  On the other hand, the enable signal EN2 rises to a high level at time t11. For this reason, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 again. Then, in response to the rising edge of the gating clock signal GCLK2B, the flip-flop FF3 latches the data B7, B8, B9... From the logic circuit 10 at times t13, t15, t17. Output.

  Further, at times t14, t16,..., The flip-flop FF2 latches and outputs the data B7, B8,... Output from the above-described flip-flop FF3 in response to the rising edge of the gating clock signal GCLK2. To do.

Japanese Patent Laid-Open No. 9-8143 JP 2004-186515 A

  However, when a flip-flop FF3 gate-clocked as shown in FIG. 27 is inserted to avoid a hold error, the following problem occurs. First, as shown in FIG. 26, in the semiconductor integrated circuit 1 of FIG. 24 that performs an ideal operation, the flip-flop FF2 latches the data B6 at the seventh reference clock rising edge from time t1 (time t9). Is output.

  On the other hand, as shown in FIG. 28, in the semiconductor integrated circuit 1 of FIG. 27 in which the flip-flop FF3 is inserted, the flip-flop FF2 latches the data B1 at the rising edge of the seventh reference clock from time t1 (time t12). Is output.

  This occurs because the flip-flop FF3 in the previous stage of the flip-flop FF2 latches and outputs data according to the rising edge of the gating clock signal GCLK2B having a phase opposite to that of the gating clock signal GCLK2.

  As shown in FIG. 28, the data input by the flip-flop FF3 can be latched and output at time t13. Therefore, the flip-flop FF3 cannot latch the data B6 from the logic circuit 10 at the seventh reference clock rising edge (time t12) from time t1, and discards it. Therefore, in the semiconductor integrated circuit 1 (FIG. 27) in which the flip-flop FF3 is inserted, the data output at the seventh reference clock rising edge from the time t1 of the flip-flop FF2 performs the ideal operation. The result is different from the data of 24). Therefore, the semiconductor integrated circuit 1 in which the flip-flop FF3 is inserted (FIG. 27) outputs an operation result different from that of the semiconductor integrated circuit 1 in which the flip-flop FF3 is not inserted (FIG. 24).

  Further, as a configuration that does not cause such operation irregularity, as shown in FIG. 29, a configuration of the semiconductor integrated circuit 1 that does not gate the input clock signal of the inserted flip-flop FF3 is conceivable.

  In this case, as shown in the operation timing chart of FIG. 30, the reverse-phase clock signal CLKB of the reference clock is input to the flip-flop FF3 regardless of the fall of the enable signal EN2 at time t2. In response to the rising edge of the clock signal CLKB, the flip-flop FF3 latches and outputs the input data.

  Therefore, after time t2, the flip-flop FF3 latches data B1, B1, B1, B6, B7, B8 at time t3, t4, t5, t6, t8, t10. Output to FF2. Then, after the enable signal EN2 rises to a high level, the flip-flop FF2 receives data B6, B7, B8,... At times t7, t9, t11... According to the rising edge of the gating clock signal GCLK2, respectively.・ Latch and output.

  As can be seen from FIG. 30, in this case, the data output by the flip-flop FF2 between the semiconductor integrated circuit 1 (FIG. 29) after the insertion of the flip-flop FF3 and the semiconductor integrated circuit 1 (FIG. 24) before the insertion is It becomes the same, and operation fraud does not occur.

  However, since the flip-flop FF3 is not clock-gated, it always operates regardless of the enable signal. For this reason, even if the power consumption of the folding flip-flops FF1 and FF2 is reduced by performing clock gating, the total power consumption reduction effect of the semiconductor integrated circuit 1 is reduced due to the increase in the power consumption of the flip-flop FF3. Problem occurs. Therefore, the inserted flip-flop FF3 is expected to be inserted into an existing circuit on the premise of clock gating.

  As described above, in order to eliminate a hold error, when a clock-gated flip-flop is inserted between the front-stage flip-flop and the rear-stage flip-flop, the operation shown in FIG. 28 is performed depending on how the flip-flop is inserted. Fraud may occur. Therefore, there is a need for a semiconductor integrated device design apparatus and design method that does not cause the above-described operation fraud when a clock-gated flip-flop is inserted for hold error compensation.

  The technique of Patent Document 1 is also a technique for compensating for a hold error. In this prior art, a low latch circuit is inserted between the front-stage flip-flop and the rear-stage flip-flop. This low latch operates as a delay element and avoids a hold error. However, when a hold error occurs in the row latch circuit, the row latch circuit does not operate as a delay element, and the signal latched by the previous stage flip-flop may be input to the subsequent stage flip-flop without delay. . For this reason, processing for avoiding a hold error of the low latch circuit itself is required.

  The technique of Patent Document 2 is also a technique for compensating for a hold error. In this prior art, a half-cycle delay of the clock signal is provided at the subsequent stage of the flip-flop in order to compensate the hold of the circuit. As a mechanism for providing this half-cycle delay, a low latch circuit and a reverse-phase flip-flop are described. However, when a low latch circuit is used, a process for avoiding a hold error of the low latch circuit itself is required, as in the above-mentioned Patent Document 1. Further, when a reverse phase flip-flop is used, there is no description about clock gating, and the problem described with reference to FIG. 28 may occur.

One embodiment of the present invention includes first and second flip-flops that latch and output input data in accordance with a clock signal input to a clock input terminal. The second flip-flop In a semiconductor integrated circuit to which an output signal of the first flip-flop via a logic circuit is input, the first or second flip-flop is newly provided between the first flip-flop and the second flip-flop. A method of designing a semiconductor integrated circuit that connects a third flip-flop that latches and outputs input data according to a clock signal that is shifted by a half cycle of a clock signal input to the flip-flop, the semiconductor integrated circuit comprising: At least the first enable signal that is input outputs a signal that is synchronized with the reference clock when activated, and the signal that is output when deactivated is the first signal. The first clock gating circuit having the value of " and the second enable signal input outputs a signal synchronized with the reference clock when activated, and the signal output when deactivated is the second value. The second clock gating circuit, and the clock signal input to the first flip-flop is a signal from the first clock gating circuit, The third flip-flop is connected between the first flip-flop and the logic circuit, and an input clock signal is used as a signal from the first clock gating circuit, or the second flip-flop Is a signal from the second clock gating circuit, the third flip-flop is connected to the logic circuit and the logic circuit. Connected between the second flip-flop, a method for designing a semiconductor integrated circuit of the input clock signal signal from the second clock gating circuit.

  Another aspect of the present invention includes first and second flip-flops that latch and output input data in accordance with a clock signal input to a clock input terminal, and the second flip-flop has a predetermined value. In the semiconductor integrated circuit to which the output signal of the first flip-flop via the logic circuit is input, the first or second flip-flop is newly provided between the first flip-flop and the second flip-flop. A semiconductor integrated circuit design apparatus for connecting a third flip-flop that latches and outputs input data in response to a clock signal shifted by a half cycle of the clock signal input to the flip-flop, wherein the semiconductor integrated circuit includes: A signal that is synchronized with the reference clock is output when at least the first enable signal that is input is activated, and a signal that is output when the first enable signal is inactivated. The first clock gating circuit having a value of 1 and the input second enable signal output a signal synchronized with the reference clock when activated, and the signal output when deactivated is the second A clock signal input to the first flip-flop is a signal from the first clock gating circuit. The third flip-flop is connected between the first flip-flop and the logic circuit, and the input clock signal is a signal from the first clock gating circuit, or the second flip-flop When the clock signal input to the clock is a signal from the second clock gating circuit, the third flip-flop is connected to the logic circuit. Connected between the second flip-flop, a design device of a semiconductor integrated circuit according to the signal of the input clock signal from said second clock gating circuit.

  Still another aspect of the present invention includes first and second flip-flops that latch and output input data in accordance with a clock signal input to a clock input terminal, and the second flip-flop includes: In a semiconductor integrated circuit to which an output signal of the first flip-flop that has passed through a predetermined logic circuit is input, the first or second flip-flop is newly provided between the first flip-flop and the second flip-flop. A semiconductor integrated circuit design program for connecting a third flip-flop that latches and outputs input data in response to a clock signal shifted by a half cycle of a clock signal input to two flip-flops, the semiconductor integrated circuit Output a signal synchronized with the reference clock when at least the first enable signal input is activated, and output when deactivated A signal that outputs a first clock gating circuit whose signal has a first value and a second enable signal that is input are synchronized with the reference clock when activated, and that is output when deactivated Is a second clock gating circuit having a second value, and the clock signal input to the first flip-flop is a signal from the first clock gating circuit. The third flip-flop is connected between the first flip-flop and the logic circuit, and the input clock signal is a signal from the first clock gating circuit, or When the clock signal input to the second flip-flop is a signal from the second clock gating circuit, the third flip-flop is And a circuit, connected between said second flip-flop, a design program of the semiconductor integrated circuit of the signal of the input clock signal from said second clock gating circuit.

  In the present invention, the third flip-flop is connected so that the semiconductor integrated circuit has a predetermined configuration according to the type of the clock gating circuit corresponding to the first flip-flop at the front stage and the second flip-flop at the rear stage. In addition, the clock gating circuit corresponding to the third flip-flop can be selected.

  The present invention prevents a configuration of a semiconductor integrated circuit after a flip-flop from being illegally operated when a clock-gated flip-flop is inserted between the front and rear flip-flops for hold error compensation. Is possible.

1 is a block configuration diagram of a semiconductor integrated circuit design apparatus according to a first exemplary embodiment; FIG. 3 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 1 is a configuration diagram of a semiconductor integrated circuit after an insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; FIG. 3 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 5 is an operation timing chart for explaining the configuration and operation of a single OR type clock gating cell. 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; FIG. 3 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; FIG. 3 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is a flowchart for explaining the operation of the flip-flop insertion unit according to the first exemplary embodiment; 3 is a flowchart for explaining the operation of the flip-flop insertion unit according to the first exemplary embodiment; FIG. 3 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 3 is an operation timing chart of the semiconductor integrated circuit after the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the first exemplary embodiment; 6 is a table summarizing combinations when the flip-flop insertion unit according to the first exemplary embodiment inserts an insertion flip-flop. FIG. 6 is a configuration diagram of a semiconductor integrated circuit before the insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the second embodiment; FIG. 6 is a configuration diagram of a semiconductor integrated circuit after an insertion flip-flop is inserted by the semiconductor integrated circuit design apparatus according to the second exemplary embodiment; 10 is a flowchart for explaining an operation of the flip-flop insertion unit according to the second exemplary embodiment; 10 is a flowchart for explaining an operation of the flip-flop insertion unit according to the second exemplary embodiment; 10 is a table summarizing combinations when the flip-flop insertion unit according to the second exemplary embodiment inserts an insertion flip-flop. It is a block diagram which shows the structure of the design apparatus of the semiconductor integrated circuit concerning other embodiment. It is a block diagram of a semiconductor integrated circuit before a conventional semiconductor integrated circuit design apparatus inserts an insertion flip-flop. 6 is an operation timing chart for explaining the operation of an AND type clock gating cell. It is a block diagram of a semiconductor integrated circuit before a conventional semiconductor integrated circuit design apparatus inserts an insertion flip-flop. It is a block diagram of a semiconductor integrated circuit after a conventional semiconductor integrated circuit design apparatus has inserted an insertion flip-flop. 5 is an operation timing chart of a semiconductor integrated circuit after a conventional semiconductor integrated circuit design apparatus has inserted an insertion flip-flop. It is a block diagram of a semiconductor integrated circuit when a clock signal that is not clock-gated is input to an insertion flip-flop. It is an operation | movement timing chart at the time of inputting the clock signal which is not clock-gating with respect to an insertion flip-flop.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a semiconductor integrated circuit design apparatus and design method.

  FIG. 1 shows an example of a block configuration of a semiconductor integrated circuit design apparatus 100 according to the first exemplary embodiment. As illustrated in FIG. 1, the semiconductor integrated circuit design apparatus 100 includes a circuit design database 101, a timing analysis unit 102, and a flip-flop insertion unit 104. Here, the flip-flop insertion unit 104 constitutes a characteristic part of the present invention.

  The circuit design database 101 includes various pieces of information necessary for designing a semiconductor integrated circuit having a predetermined function. This information includes, for example, information about logic elements (AND circuit, OR circuit, XOR circuit, etc.) and flip-flops provided in the semiconductor integrated circuit, delay information of the logic elements, etc., timing information of flip-flops, and unit There is delay information per wiring length.

  The timing analysis unit 102 analyzes occurrence of a hold error, error timing, and the like for the designed semiconductor integrated circuit. Then, as an analysis result, hold error information 103 having information on where and in what timing a hold error has occurred is output in the semiconductor integrated circuit.

  The flip-flop insertion unit 104 inserts a flip-flop for hold error compensation (hereinafter referred to as an insertion flip-flop) at a necessary location of the semiconductor integrated circuit in accordance with the hold error information 103+. When inserting the insertion flip-flop, the flip-flop insertion unit 104 inserts the insertion flip-flop at an optimal location according to the type of the clock gating cell corresponding to the preceding and succeeding flip-flops. At the same time, the gating clock of the inserted flip-flop is selected from the gating clocks output from the clock gating cell corresponding to the preceding or succeeding flip-flop. Then, the circuit configuration and connection information of the semiconductor integrated circuit in which the insertion flip-flop is inserted and the hold error is eliminated is output as circuit connection information 105. The insertion flip-flop operates with a clock signal having a phase opposite to that of the input gating clock (shifted by a half cycle).

  The flip-flop insertion unit 104 changes the type of the clock gating cell corresponding to the front-stage and rear-stage flip-flops when the types of clock gating cells corresponding to the front-stage and rear-stage flip-flops are a predetermined combination. After the change, the insertion flip-flop is inserted by the above-described operation.

  Hereinafter, the operation of the flip-flop insertion unit 104 constituting the characteristic part of the present invention will be described with reference to the drawings.

  FIG. 2 shows a block configuration diagram of the semiconductor integrated circuit 2 in which no insertion flip-flop is inserted in the flip-flop insertion unit 104. As shown in FIG. 2, the semiconductor integrated circuit 2 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2.

  The flip-flop FF1 inputs data from the previous circuit to the data input terminal D. Then, the data input to the data input terminal D is latched according to the gating clock signal GCLK1 input to the clock input terminal, and is output as the data A to the data output terminal Q.

  The data A is input to the data input terminal D of the flip-flop FF2 as data B through the logic circuit 10 that performs a predetermined logic operation. Then, the flip-flop FF2 latches the data B in accordance with the gating clock signal GCLK2 input to the clock input terminal and outputs it to the data output terminal Q.

  Here, each of the clock gating cells CGC1 and CGC2 includes a flip-flop FF11 and an AND circuit AND11. That is, the clock gating cells CGC1 and CGC2 are both the AND type clock gating cells described above.

  The flip-flop FF11 inputs the enable signal EN1 to the data input terminal D. In addition, a clock signal having a phase opposite to that of the reference clock CLK (half cycle shifted) is input to the clock input terminal. The flip-flop FF11 latches the enable signal EN1 according to the clock signal input to the clock input terminal, and outputs it from the data output terminal Q.

  The AND circuit AND11 inputs a reference clock to one input terminal, and inputs data from the data output terminal Q of the flip-flop FF11 to the other input terminal. The product is calculated and output from the output terminal.

  As can be seen from FIG. 2, the semiconductor integrated circuit 2 has the same configuration as the semiconductor integrated circuit 1 of FIG. Therefore, an operation timing chart of the semiconductor integrated circuit 2 in the case of performing an ideal operation in which a hold error does not occur is the same as that in FIG. 26, and description thereof is omitted here.

  Next, the timing analysis unit 102 determines that a hold error occurs in the semiconductor integrated circuit 2, and based on the hold error information 103, the flip-flop insertion unit 104 inserts the insertion flip-flop FF3 between the flip-flops FF1 and FF2. Consider the case. FIG. 3 shows a block configuration of the semiconductor integrated circuit 2 when the flip-flop FF3 is inserted.

  As shown in FIG. 3, the flip-flop insertion unit 104 connects the insertion flip-flop FF3 between the flip-flop FF1 and the logic circuit 10. The flip-flop inserting unit 104 is connected so that the gating clock signal of the inserting flip-flop FF3 is supplied from the clock gating cell CGC1.

  FIG. 4 is a timing chart for explaining the operation of the semiconductor integrated circuit 2 of FIG. As shown in FIG. 4, the flip-flop FF1 latches the data input to the data input terminal D and outputs it as data A1 in response to the rise of the gating clock signal GCLK1 at time t1. At time t2, the enable signal EN1 falls to the low level. For this reason, the gating clock signal GCLK1 is fixed at the low level, and the output data from the flip-flop FF1 is also fixed at the data A1.

  Here, the flip-flop FF3 inputs a clock signal GCLK1B having a phase opposite to that of the gating clock signal GCLK1 (shifted by a half cycle) to the clock input terminal. Therefore, the flip-flop FF3 latches and outputs the output data A1 from the flip-flop FF1 in accordance with the rising edge of the clock signal GCLK1B at time t3. However, since the gating clock signal GCLK1 is fixed at the low level after time t2 as described above, the output data of the flip-flop FF3 after time t3 is also fixed with the data A1. The data A1 is input as data B1 to the flip-flop FF2 via the logic circuit 10.

  On the other hand, the enable signal EN2 is at a high level before time t6. Therefore, the gating clock signal GCLK2 having the rising edge at the times t1, t4, and t5 and having the same phase as the reference clock is output. Therefore, the flip-flop FF2 latches and outputs the data B1 from the logic circuit 10 in response to the rising of the gating clock signal GCLK2 at times t4 and t5.

  At time t6, the enable signal EN2 falls to the low level. For this reason, the gating clock signal GCLK2 is fixed to the low level. Therefore, the output of the flip-flop FF2 is also fixed at the data B1 latched at time t5.

  Next, the enable signal EN1 rises to a high level at time t7. For this reason, the gating clock signal GCLK1 in phase with the reference clock is output from the clock gating cell CGC1 again. In response to the rising edge of the gating clock signal GCLK1, data A6, A7, A8, A9... Are output from the flip-flop FF1 at times t8, t11, t13, t15.

  Then, in response to the rising edge of the clock signal GCLK1B, the flip-flop FF2 latches the output data A6, A7, A8, A9... At the time t10, t12, t14, t16. Output to the logic circuit 10. The data A6, A7, A8, A9,... Are input as data B6, B7, B8, B9,.

  On the other hand, the enable signal EN2 rises to a high level at time t9. For this reason, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 again. Then, at times t11, t13, t15..., The flip-flop FF2 latches the data B6, B7, B8... From the logic circuit 10 in response to the rising edge of the gating clock signal GCLK2, respectively. Output.

  As described above, the semiconductor integrated circuit 2 in FIG. 3 after inserting the insertion flip-flop FF3 latches and outputs the data B6 at the seventh reference clock rising edge from time t1 (time t11). is doing. This is the same operation result as the ideal operation of the semiconductor integrated circuit 2 of FIG. 2 in which the insertion flip-flop FF3 is not inserted.

  Next, FIG. 5 shows a block configuration diagram of the semiconductor integrated circuit 3 having a configuration different from that of the semiconductor integrated circuit 2 in the configuration of the clock gating cell corresponding to the subsequent flip-flop. FIG. 7 shows a configuration in which the flip-flop insertion unit 104 inserts the insertion flip-flop FF3 into the semiconductor integrated circuit 3.

  First, as shown in FIG. 5, the semiconductor integrated circuit 3 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2. The semiconductor integrated circuit 3 of FIG. 5 differs from the semiconductor integrated circuit 2 of FIG. 2 in the configuration of the clock gating cell CGC2. Therefore, only the clock gating cell CGC2 will be described here unless otherwise specified.

  The clock gating cell CGC2 includes a flip-flop FF21 and an OR circuit OR21. FIG. 6 shows a configuration of a single clock gating cell CGC2 and a timing chart for explaining its operation. As shown in FIG. 6, before time t1, the enable signal EN2 is at a high level, and the inverted signal EN2B of the enable signal EN2 is at a low level. Therefore, the output data of the flip-flop FF21 is also at a low level. For this reason, the gating clock signal GCLK2 having the same phase as the reference clock input to the other input terminal is output from the output terminal of the OR circuit OR21.

  At time t1, the enable signal EN2 falls to the low level, and the inverted signal EN2B rises to the high level. Thereafter, the output data of the flip-flop FF21 also becomes a high level at time t2 in response to the rising edge of the clock signal having a reverse phase (shifted by a half cycle) of the reference clock CLK. For this reason, the output of the OR circuit OR21 is fixed at a high level.

  At time t3, the enable signal EN2 rises again to the high level, and the inverted signal EN2B falls to the low level. After that, corresponding to the rising edge of the clock signal having a phase opposite to that of the reference clock CLK (shifted by a half cycle), the output data of the flip-flop FF21 also becomes low level at time t4. Thereafter, as in the time before time t1, the output of the OR circuit OR21 is the gating clock signal GCLK2 having the same phase as the reference clock.

  Hereinafter, the clock gating cell having the same configuration as the clock gating cell CGC2 of FIG. 5 is referred to as an “OR type clock gating cell”.

  The operation timing chart of the semiconductor integrated circuit 3 in the case of performing an ideal operation in which no hold error occurs basically shows that the gating clock signal GCLK2 is fixed to the high level when the enable signal EN2 is at the low level. This is the same as FIG. For this reason, explanation here is omitted.

  Next, the timing analysis unit 102 determines that a hold error occurs in the semiconductor integrated circuit 3, and based on the hold error information 103, the flip-flop insertion unit 104 inserts the insertion flip-flop FF3 between the flip-flops FF1 and FF2. Consider the case.

  As shown in FIG. 7, in the semiconductor integrated circuit 3 after the flip-flop FF3 is inserted by the flip-flop insertion unit 104, the flip-flop FF3 is connected between the flip-flop FF1 and the logic circuit 10, and the gating The clock is connected to be supplied from the clock gating cell CGC1.

  FIG. 8 shows an operation timing chart of the semiconductor integrated circuit 3 of FIG. However, the operation timing chart of the semiconductor integrated circuit 3 in FIG. 8 is basically the same as that in FIG. 4 except that when the enable signal EN2 is at low level, the gating clock signal GCLK2 is fixed at high level. For this reason, explanation here is omitted.

  As described above, the semiconductor integrated circuit 3 of FIG. 7 after inserting the insertion flip-flop FF3 latches and outputs the data B6 at the seventh reference clock rising edge from time t1 (time t11). is doing. This is the same operation result as the ideal operation of the semiconductor integrated circuit 3 of FIG. 5 in which the insertion flip-flop FF3 is not inserted.

  As described above, when the clock gating cell CGC1 corresponding to the flip-flop FF1 in the preceding stage of the insertion flip-flop FF3 is an AND type clock gating cell as shown in FIGS. The FF3 is connected between the previous flip-flop FF1 and the logic circuit 10. The flip-flop inserting unit 104 is connected so that the gating clock signal of the inserting flip-flop FF3 is supplied from the clock gating cell CGC1.

  By adopting such a connection configuration, it is possible to avoid the occurrence of incorrect operation in the semiconductor integrated circuits 2 and 3 after the insertion flip-flop FF3 is inserted. Then, circuit connection information 105 having the circuit configuration of the semiconductor integrated circuits 2 and 3 shown in FIGS. 3 and 7 is output from the flip-flop insertion unit 104.

  Further, FIG. 9 shows a block configuration diagram of the semiconductor integrated circuit 4 when the configuration of the clock gating cells corresponding to the flip-flops FF1 and FF2 is different from that of the semiconductor integrated circuits 2 and 3. FIG. 10 shows a configuration in which the flip-flop inserting unit 104 inserts the inserting flip-flop FF3 into the semiconductor integrated circuit 4.

  As shown in FIG. 9, the semiconductor integrated circuit 4 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2. The semiconductor integrated circuit 4 of FIG. 9 is different from the semiconductor integrated circuits 2 and 3 in that both clock gating cells CGC1 and CGC2 are OR type clock gating cells.

  In the operation timing chart of the semiconductor integrated circuit 4 when performing an ideal operation in which no hold error occurs, when the enable signals EN1 and EN2 are at low level, the gating clock signals GCLK1 and GCLK2 are fixed at high level, respectively. Other than this, it is basically the same as FIG. For this reason, explanation here is omitted.

  Next, the timing analysis unit 102 determines that a hold error occurs in the semiconductor integrated circuit 4. Based on the hold error information 103, the flip-flop insertion unit 104 inserts the insertion flip-flop FF 3 between the flip-flops FF 1 and FF 2. Consider the case.

  As shown in FIG. 10, in the semiconductor integrated circuit 4 after the flip-flop FF3 is inserted by the flip-flop insertion unit 104, the flip-flop FF3 is connected between the logic circuit 10 and the flip-flop FF2, and the gating is performed. The clock is connected to be supplied from the clock gating cell CGC2.

  FIG. 11 is a timing chart for explaining the operation of the semiconductor integrated circuit 4 of FIG. As shown in FIG. 11, the flip-flop FF1 latches the data input to the data input terminal D and outputs it as data A1 in response to the rising of the gating clock signal GCLK1 at time t1. At time t2, the enable signal EN1 falls to the low level. For this reason, the gating clock signal GCLK1 is fixed at a high level, and the output data from the flip-flop FF1 is also fixed at the data A1. The data A1 is input as data B1 to the flip-flop FF2 via the logic circuit 10.

  On the other hand, the enable signal EN2 is at a high level before time t7. Therefore, the gating clock signal GCLK2 having the rising edge at the times t1, t4, and t6 and having the same phase as the reference clock is output.

  Here, as described above, the flip-flop FF3 inputs the clock signal GCLK2B having a phase opposite to that of the gating clock signal GCLK2 (shifted by a half cycle) to the clock input terminal. Therefore, the flip-flop FF3 latches and outputs the output data B1 from the logic circuit 10 in accordance with the rising edge of the clock signal GCLK2B at times t3 and t5.

  Further, the flip-flop FF2 latches and outputs the data B1 from the flip-flop FF3 in response to the rising of the gating clock signal GCLK2 at times t4 and t6.

  At time t7, the enable signal EN2 falls to the low level. Therefore, the gating clock signal GCLK2 is fixed at the high level and the gating clock signal GCLK2B is fixed at the low level. Therefore, the output of the flip-flop FF3 is fixed at the data B1 latched at time t5. Similarly, the output of the flip-flop FF2 is also fixed at the data B1 latched at time t6.

  Next, the enable signal EN1 rises to a high level at time t8. For this reason, the gating clock signal GCLK1 in phase with the reference clock is output from the clock gating cell CGC1 again. Then, in response to the rising edge of the gating clock signal GCLK1, data A6, A7, A8, A9... Are output from the flip-flop FF1 to the logic circuit 10 at times t9, t12, t14, t16. . The data A6, A7, A8, A9,... Are input as data B6, B7, B8, B9,.

  On the other hand, the enable signal EN2 rises to a high level at time t10. For this reason, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 again. At time t11, t13, t15, t17,..., The flip-flop FF2 latches the data B6, B7, B8,... From the logic circuit 10 in response to the rising edge of the gating clock signal GCLK2B. And output.

  Further, the flip-flop FF2 latches and outputs the data BB6, B7, B8,... From the flip-flop FF3 in response to the rising of the gating clock signal GCLK2 at times t12, t14, t16.

  As described above, the semiconductor integrated circuit 4 of FIG. 10 after inserting the insertion flip-flop FF3 latches and outputs the data B6 at the seventh reference clock rising edge from time t1 (time t12). is doing. This is the same operation result as the ideal operation of the semiconductor integrated circuit 4 of FIG. 9 in which the insertion flip-flop FF3 is not inserted.

  Therefore, when both the clock gating cells corresponding to the preceding flip-flop FF1 and the subsequent flip-flop FF2 of the insertion flip-flop FF3 are OR-type clock gating cells, the flip-flop inserting unit 104 determines that the flip-flop FF3 The circuit 10 is connected between the post-stage flip-flop FF2 and connected to supply a gating clock from the clock gating cell CGC2. By adopting such a connection configuration, it is possible to avoid the occurrence of incorrect operation in the semiconductor integrated circuit 4 after the insertion flip-flop FF3 is inserted.

  Then, circuit connection information 105 having the circuit configuration of the semiconductor integrated circuit 4 shown in FIG.

  Next, FIG. 12 shows a block configuration diagram of the semiconductor integrated circuit 5 when the configuration of the clock gating cells corresponding to the flip-flops FF1 and FF2 is different from that of the semiconductor integrated circuits 2, 3, and 4.

  As shown in FIG. 12, the semiconductor integrated circuit 5 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2. In the semiconductor integrated circuit 5 of FIG. 12, the clock gating cells CGC 1 and CGC 2 are OR type and AND type clock gating cells, respectively, which are different from the semiconductor integrated circuits 2, 3, and 4.

  In the case of this semiconductor integrated circuit 5, even if the timing analysis unit 102 determines that a hold error occurs, the flip-flop insertion unit 104 determines that a new flip-flop FF3 is not inserted between the flip-flops FF1 and FF2. To do.

  Then, the clock gating cell CGC1 is changed to an AND type clock gating cell, that is, the same configuration as that of the semiconductor integrated circuit 2 of FIG. 2, and the flip-flop is connected by the same connection as that of the semiconductor integrated circuit 2 of FIG. Insert FF3. Alternatively, the clock gating cell CGC2 is changed to an OR type clock gating cell, that is, the same configuration as that of the semiconductor integrated circuit 4 of FIG. 9 is changed, and then the flip-flop is connected by the same connection as that of the semiconductor integrated circuit 4 of FIG. Insert FF3.

  For this reason, the semiconductor integrated circuit 5 is finally changed to the configuration of FIG. 3 or FIG. 10 by the operation of the flip-flop insertion unit 104 as described above. Therefore, even if the timing analysis unit 102 determines that a hold error has occurred in the semiconductor integrated circuit 5, the semiconductor integrated circuit 5 is consequently changed to the configuration of FIG. 3 or FIG. The semiconductor integrated circuit is configured to avoid the occurrence of fraud. Then, circuit connection information 105 having the configuration of the semiconductor integrated circuit is output from the flip-flop insertion unit 104.

  FIG. 13 is a flowchart for explaining the circuit design operation by the flip-flop insertion unit 104 as described above. As shown in FIG. 13, first, the flip-flop insertion unit 104 receives inputs of a front-stage flip-flop (hereinafter referred to as a flip-flop FF1) and a rear-stage flip-flop (hereinafter referred to as a flip-flop FF2) where a hold error has occurred. It is determined whether or not the clock signal is gated (S101).

  If the input clock signals of the flip-flop FF1 and the flip-flop FF2 are not gated (S101 YES), the input clock signal of the inserted flip-flop to be inserted (hereinafter referred to as flip-flop FF3) is also not gated ( S102).

  On the other hand, if it is determined in step S101 that the input clock signal is gated in at least one of the flip-flops FF1 and FF2 (NO in S101), a clock gating cell (hereinafter referred to as a clock) corresponding to the flip-flop FF1. It is determined whether or not the gating cell CGC1 is an AND type clock gating cell (S103).

  If it is determined that the clock gating cell CGC1 is an AND type clock gating cell (S103 YES), the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC1 (S104).

  On the other hand, if it is determined in step S103 that the clock gating cell CGC1 is not an AND type clock gating cell (NO in S103), a clock gating cell corresponding to the flip-flop FF2 (hereinafter referred to as clock gating cell CGC2) is present. It is determined whether or not it is an OR type clock gating cell (S105).

  When it is determined that the clock gating cell CGC2 is an OR type clock gating cell (S105 YES), the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC2 (S106).

  On the other hand, if it is determined in step S105 that the clock gating cell CGC2 is not an OR type clock gating cell (NO in S105), whether the input clock signal is gated in one of the flip-flops FF1 and FF2. Is determined (S107).

  If it is determined that the input clock signal is not gated in one of the flip-flops FF1 and FF2 (YES in S107), the flip-flop FF1 in which the input clock signal is not gated and the logic circuit 10 The flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2 to which the input clock signal is not gated. The input clock signal of the flip-flop FF3 is also not gated (S102).

  On the other hand, if it is determined in step S107 that the input clock signal is gated by one of the flip-flops FF1 and FF2 (S107 NO), the clock gating cell CGC1 is an OR type clock gating cell. It is determined whether or not (S108).

  If it is determined that the clock gating cell CGC1 is an OR type clock gating cell (YES in S108), the clock gating cell CGC1 is changed from the OR type to the AND type clock gating cell (S109). Then, the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC1 (S104).

  On the other hand, if it is determined in step S108 that the clock gating cell CGC1 is not an OR type clock gating cell (NO in S108), since the clock gating cell CGC2 is an AND type, this is changed from an AND type to an OR type clock gating cell. Change to a cell (S110). Then, the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC2 (S106).

  Further, the flip-flop insertion unit 104 may perform a design operation as shown in the flowchart of FIG. As shown in FIG. 14, first, the flip-flop inserting unit 104 determines whether or not the input clock signals of the flip-flops FF1 and FF2 at the place where the hold error has occurred are gated (S201).

  If both the input clock signals of the flip-flops FF1 and FF2 are not gated (YES in S201), the input clock signal of the flip-flop FF3 is also not gated (S202).

  On the other hand, if it is determined in step S201 that the input clock signal is gated in at least one of the flip-flops FF1 and FF2 (S201 NO), the clock gating cell CGC2 corresponding to the flip-flop FF2 is OR-type. It is determined whether or not it is a clock gating cell (S203).

  When it is determined that the clock gating cell CGC2 is an OR type clock gating cell (YES in S203), the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC2 (S204).

  On the other hand, if it is determined in step S203 that the clock gating cell CGC2 is not an OR type clock gating cell (NO in S203), whether or not the clock gating cell CGC1 corresponding to the flip-flop FF1 is an AND type clock gating cell. Is determined (S205).

  If it is determined that the clock gating cell CGC1 is an AND type clock gating cell (S205 YES), the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC1 (S206).

  On the other hand, if it is determined in step S205 that the clock gating cell CGC1 is not an AND type clock gating cell (NO in S205), whether or not the input clock signal is gated in one of the flip-flops FF1 and FF2. Is determined (S207).

  If it is determined that one of the flip-flops FF1 and FF2 does not gate the input clock signal (YES in S207), the flip-flop FF1 that does not gate the input clock signal and the logic circuit 10 The flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2 to which the input clock signal is not gated. Then, the input clock signal of the flip-flop FF3 is also not gated (S202).

  On the other hand, when it is determined in step S207 that the input clock signal is gated in one of the flip-flops FF1 and FF2 (S207 NO), the clock gating cell CGC2 is an AND type clock gating cell. It is determined whether or not (S208).

  If it is determined that the clock gating cell CGC2 is an AND type clock gating cell (S208 YES), the clock gating cell CGC2 is changed from an AND type to an OR type clock gating cell (S209). Then, the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC2 (S204).

  On the other hand, if it is determined in step S208 that the clock gating cell CGC2 is not an AND type clock gating cell (NO in S208), the clock gating cell CGC1 is an OR type, and this is changed from an OR type to an AND type clock gating. Change to a cell (S210). Then, the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC1 (S206).

  By step S204 in FIG. 14, the flip-flop inserting unit 104 can generate the semiconductor integrated circuit 6 having the configuration as shown in FIG. 15 from the semiconductor integrated circuit 3 in FIG. The semiconductor integrated circuit 6 has a configuration in which an insertion flip-flop FF3 for hold error compensation is inserted into the semiconductor integrated circuit 3.

  Here, the semiconductor integrated circuit 3 of FIG. 7 also has a configuration in which an insertion flip-flop FF3 for hold error compensation is inserted into the semiconductor integrated circuit 3 of FIG. However, as described above, the semiconductor integrated circuit 3 in FIG. 7 is connected between the flip-flop FF1 and the logic circuit 10 in step S104 based on the operation of the flowchart in FIG. The clock gating cell CGC1 is connected to be supplied. However, in the semiconductor integrated circuit 6 of FIG. 15, the insertion flip-flop FF3 is connected between the logic circuit 10 and the flip-flop FF2 and the gating clock is the OR type clock gating cell CGC2 in step S204 of FIG. It becomes the structure connected so that it might be supplied from.

  As shown in FIG. 15, in the semiconductor integrated circuit 6 after the flip-flop FF3 is inserted by the flip-flop insertion unit 104, the flip-flop FF3 is connected between the logic circuit 10 and the flip-flop FF2. The configuration is such that the clock is supplied from the OR type clock gating cell CGC2. FIG. 16 shows an operation timing chart of the semiconductor integrated circuit 6 of FIG.

  As shown in FIG. 16, the flip-flop FF1 latches the data input to the data input terminal D and outputs it as data A1 in response to the rise of the gating clock signal GCLK1 at time t1. At time t2, the enable signal EN1 falls to the low level. For this reason, the gating clock signal GCLK1 is fixed at the low level, and the output data from the flip-flop FF1 is also fixed at the data A1. This data A1 is input as data B1 to the flip-flop FF3 via the logic circuit 10.

  On the other hand, the enable signal EN2 is at a high level before time t7. Therefore, the gating clock signal GCLK2 having the rising edge at the times t1, t4, and t6 and having the same phase as the reference clock is output.

  Here, as described above, the flip-flop FF3 inputs the clock signal GCLK2B having a phase opposite to that of the gating clock signal GCLK2 (shifted by a half cycle) to the clock input terminal. Therefore, the flip-flop FF3 latches and outputs the output data B1 from the logic circuit 10 in accordance with the rising edge of the clock signal GCLK2B at times t3 and t5.

  Further, the flip-flop FF2 latches and outputs the data B1 from the flip-flop FF3 in response to the rising of the gating clock signal GCLK2 at times t4 and t6.

  At time t7, the enable signal EN2 falls to the low level. Therefore, the gating clock signal GCLK2 is fixed at the high level and the gating clock signal GCLK2B is fixed at the low level. Therefore, the output of the flip-flop FF3 is fixed at the data B1 latched at time t5. Similarly, the output of the flip-flop FF2 is also fixed at the data B1 latched at time t6.

  Next, the enable signal EN1 rises to a high level at time t8. For this reason, the gating clock signal GCLK1 in phase with the reference clock is output from the clock gating cell CGC1 again. Then, in response to the rising edge of the gating clock signal GCLK1, data A6, A7, A8, A9... Are output from the flip-flop FF1 to the logic circuit 10 at times t9, t12, t14, t16. . The data A6, A7, A8, A9,... Are input as data B6, B7, B8, B9,.

  On the other hand, the enable signal EN2 rises to a high level at time t10. For this reason, the gating clock signal GCLK2 in phase with the reference clock is output from the clock gating cell CGC2 again. Then, at times t11, t13, t15, t17..., The flip-flop FF2 receives the data B6, B7, B8, B9... From the logic circuit 10 according to the rising edge of the gating clock signal GCLK2B. Latch and output.

  Further, the flip-flop FF2 latches and outputs the data BB6, B7, B8,... From the flip-flop FF3 in response to the rising of the gating clock signal GCLK2 at times t12, t14, t16.

  As described above, the semiconductor integrated circuit 6 of FIG. 15 after inserting the insertion flip-flop FF3 latches and outputs the data B6 at the seventh reference clock rising edge from time t1 (time t12). is doing. This is the same operation result as the ideal operation of the semiconductor integrated circuit 4 of FIG. 7 in which the insertion flip-flop FF3 is not inserted.

  Therefore, the clock gating cell CGC1 corresponding to the preceding flip-flop FF1 of the insertion flip-flop FF3 is an AND type clock gating cell, and the clock gating cell CGC2 corresponding to the subsequent flip flop FF2 is an OR type clock gating cell. In this case, the flip-flop insertion unit 104 connects the flip-flop FF3 between the logic circuit 10 and the subsequent-stage flip-flop FF2 and connects the gating clock to be supplied from the clock gating cell CGC2 according to the flowchart of FIG. . By adopting such a connection configuration, it is possible to avoid the occurrence of unauthorized operation in the semiconductor integrated circuit 6 after the insertion flip-flop FF3 is inserted.

  As described above, the flip-flop insertion unit 104 according to the first exemplary embodiment determines the types of clock gating cells corresponding to the front-stage flip-flop FF1 and the rear-stage flip-flop FF2. Then, the insertion flip-flop FF3 is automatically inserted at a predetermined location according to the determination result, and the corresponding clock gating cell is selected.

  In FIG. 17, the flip-flop insertion unit 104 inserts the insertion flip-flop FF3, the type of the clock gating cell that supplies the input clock signal, and the clock gate corresponding to the front-stage flip-flop FF1 and the rear-stage flip-flop FF2. A table summarizing the types of ting cells is shown.

  As shown in FIG. 17, when both the clock gating cells CGC1 and CGC2 are AND type clock gating cells, the flip-flop inserting unit 104 inserts the inserting flip-flop FF3 between the preceding flip-flop FF1 and the logic circuit 10 ( The input clock signal is supplied from the clock gating cell CGC1.

  When both the clock gating cells CGC1 and CGC2 are OR type clock gating cells, the flip-flop inserting unit 104 places the insertion flip-flop FF3 between the logic circuit 10 and the rear-stage flip-flop FF2 (the rear-stage flip-flop FF2). And the input clock signal is supplied from the clock gating cell CGC2.

  When the clock gating cell CGC1 is an AND type clock gating cell and the clock gating cell CGC2 is an OR type clock gating cell, the flip-flop inserting unit 104 replaces the inserting flip-flop FF3 with the preceding flip-flop FF1. 10 (immediately after the previous flip-flop FF1) and the input clock signal is supplied from the clock gating cell CGC1.

  However, depending on the operation of the flip-flop insertion unit 104 (see FIG. 14), the insertion flip-flop FF3 is connected to the rear flip-flop FF2 (immediately before the rear flip-flop FF2), and the input clock signal is the clock gating cell CGC2. Configured to be supplied from.

  When the clock gating cell CGC1 is an OR type clock gating cell and the clock gating cell CGC2 is an AND type clock gating cell, the flip-flop inserting unit 104 does not insert the insertion flip-flop FF3 in this state, The clock gating cell CGC1 is changed to an AND type clock gating cell. After the change, the insertion flip-flop FF3 is connected between the previous flip-flop FF1 and the logic circuit 10 (immediately after the previous flip-flop FF1), and the input clock signal is supplied from the clock gating cell CGC1, as described above. Configure to

  However, depending on the operation of the flip-flop insertion unit 104 (see FIG. 14), the clock gating cell CGC2 is changed to an OR type clock gating cell. After the change, similarly to the above, the insertion flip-flop FF3 is connected between the logic circuit 10 and the rear-stage flip-flop FF2 (immediately before the rear-stage flip-flop FF2), and the input clock signal is supplied from the clock gating cell CGC2. Configure to

  Here, in the conventional technique, when the insertion flip-flop FF3 is inserted, the problem described with reference to FIG. 28 may occur depending on the gating clock signal input to the insertion flip-flop FF3. However, the flip-flop insertion unit 104 according to the first embodiment is configured such that the clock-gated insertion flip-flop FF3 is connected between the front-stage flip-flop FF1 and the rear-stage flip-flop FF2 according to the combinations summarized in the table of FIG. Can be connected to. With this connection method, the insertion flip-flop FF3 is inserted so that the operation result is the same between the semiconductor integrated circuit that performs an ideal operation before the insertion of the flip-flop FF3 and the semiconductor integrated circuit after the insertion flip-flop FF3 is inserted. It is possible.

  As described above, the semiconductor integrated circuit design apparatus 100 according to the first embodiment corrects an operation error when inserting the hold error compensating insertion flip-flop FF3 into the semiconductor integrated circuit in which the hold error has occurred. It is possible to reliably design a configuration of a semiconductor integrated circuit capable of obtaining a correct operation result that does not occur without error. In this case, the existing clock gating cell can be applied to the insertion flip-flop FF3, and it is not necessary to install a new clock gating cell for the insertion flip-flop FF3, thereby increasing the circuit area of the semiconductor integrated circuit. Can be suppressed. Further, since the insertion flip-flop FF3 is clock-gated, the increase in power consumption of the semiconductor integrated circuit can be reduced as compared with the case where the insertion flip-flop FF3 is not clock-gated.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to a semiconductor integrated circuit design method and design apparatus. The design apparatus according to the second embodiment is the same as that shown in FIG. 1 described in the first embodiment. The second embodiment is different from the first embodiment in the configuration of a semiconductor integrated circuit in which the flip-flop inserting unit 104 is to insert the insertion flip-flop FF3.

  For example, FIG. 18 shows a block configuration diagram of the semiconductor integrated circuit 7 before the insertion flip-flop FF3 is inserted as an example of the semiconductor integrated circuit.

  As shown in FIG. 18, the semiconductor integrated circuit 7 includes flip-flops FF1 and FF2, and clock gating cells CGC1 and CGC2. Unlike the first embodiment, the flip-flops FF1 and FF2 are input with input clocks having a phase opposite to that of the gating clock supplied by the clock gating cells CGC1 and CGC2, respectively (shifted by a half cycle).

  In the following description, a flip-flop that uses a signal having a phase opposite to that of the gating clock (shifted by a half cycle) as an input clock is referred to as a negative flip-flop. Hereinafter, a flip-flop that uses a signal in phase with the gating clock as an input clock is referred to as a positive flip-flop.

  As shown in FIG. 18, the flip-flop FF1 inputs data from the previous circuit to the data input terminal D. Then, the data input to the data input terminal D is latched and output as data A to the data output terminal Q in accordance with a signal having a reverse phase (shifted by a half cycle) of the gating clock signal GCLK1 input to the clock input terminal. .

  The data A is input to the data input terminal D of the flip-flop FF2 as data B through the logic circuit 10 that performs a predetermined logic operation. Then, the flip-flop FF2 latches the data B in accordance with a signal having a reverse phase (shifted by a half cycle) of the gating clock signal GCLK2 input to the clock input terminal, and outputs the data B to the data output terminal Q.

  Each of the clock gating cells CGC1 and CGC2 is an OR type clock gating cell.

  This is a configuration in which the positive flip-flop of the semiconductor integrated circuit 2 of FIG. 2 is changed to negative and the AND type clock gating cell is changed to an OR type clock gating cell.

  When a hold error occurs in the semiconductor integrated circuit 7, the flip-flop insertion unit 104 inserts the insertion flip-flop FF3. At this time, the insertion flip-flop FF3 is inserted as a positive flip-flop to eliminate a hold error.

  FIG. 19 shows a block configuration diagram of the semiconductor integrated circuit 7 after the insertion flip-flop FF3 is inserted. As shown in FIG. 19, the semiconductor integrated circuit 7 includes flip-flops FF1, FF2, and FF3, and clock gating cells CGC1 and CGC2.

  The insertion flip-flop FF3, which is a positive flip-flop, is connected between the previous-stage flip-flop FF1 and the logic circuit 10, and is connected so that a gating clock is supplied from the clock gating cell CGC1. This is a configuration in which the positive flip-flop of the semiconductor integrated circuit 2 of FIG. 3 is set to negative and the AND type clock gating cell is changed to an OR type clock gating cell.

  The operation result of the semiconductor integrated circuit 7 shown in FIG. 19 is the same as the ideal operation result of the semiconductor integrated circuit 7 shown in FIG.

  Here, as described above, the configuration of the semiconductor integrated circuit 7 before and after the insertion flip-flop FF3 is inserted is the same as the configuration of the semiconductor integrated circuit 2 before and after the insertion flip-flop FF3 is inserted. The AND type clock gating cell and the OR type clock gating cell are interchanged.

  Similarly, in the configuration of the semiconductor integrated circuits 3 to 6 illustrated in the first embodiment, the positive flip-flop, the negative flip-flop, the AND-type clock gating cell, and the OR-type clock gating cell are replaced. As a result, the incorrect operation before and after the insertion of the insertion flip-flop FF3 does not occur.

  Therefore, the flip-flop insertion unit 104 of the second embodiment also inserts the insertion flip-flop FF3 between the front-stage flip-flop FF1 and the rear-stage flip-flop FF2, as in the first embodiment. However, the configuration of the semiconductor integrated circuit before and after the insertion of the insertion flip-flop FF3 is the same as that of the semiconductor integrated circuits 2 to 6 exemplified in the first embodiment, in the positive flip-flop, the negative flip-flop, the AND type clock gating cell, and the OR. The type clock gating cell is replaced. Then, the flip-flop insertion unit 104 outputs the circuit connection information 105 of the semiconductor integrated circuit having the configuration after the insertion flip-flop FF3 is inserted.

  FIG. 20 shows a flowchart for explaining the circuit design operation by the flip-flop insertion unit 104 of the second embodiment as described above. As shown in FIG. 20, first, the flip-flop inserting unit 104 gates the input clock signals of the front-stage flip-flop FF1 (negative flip-flop) and the rear-stage flip-flop FF2 (negative flip-flop) at the location where the hold error has occurred. It is determined whether or not (S301).

  If both the input clock signals of the flip-flops FF1 and FF2 are not gated (S301 YES), the input clock signal of the insertion flip-flop FF3 (positive flip-flop) to be inserted is also not gated (S302).

  On the other hand, when it is determined in step S301 that the input clock signal is gated in at least one of the flip-flops FF1 and FF2 (S301 NO), the clock gating cell CGC1 corresponding to the flip-flop FF1 is the OR type. It is determined whether it is a clock gating cell (S303).

  When it is determined that the clock gating cell CGC1 is an OR type clock gating cell (YES in S303), the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC1 (S304).

  On the other hand, if it is determined in step S303 that the clock gating cell CGC1 is not an OR type clock gating cell (NO in S303), whether or not the clock gating cell CGC2 corresponding to the flip-flop FF2 is an AND type clock gating cell. Is determined (S305).

  If it is determined that the clock gating cell CGC2 is an AND type clock gating cell (S305 YES), the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC2 (S306).

  On the other hand, if it is determined in step S305 that the clock gating cell CGC2 is not an AND type clock gating cell (NO in S305), whether or not the input clock signal is gated in one of the flip-flops FF1 and FF2. Is determined (S307).

  If it is determined that the input clock signal is not gated by one of the flip-flops FF1 and FF2 (YES in S307), the flip-flop FF1 that is not gated for the input clock signal and the logic circuit 10 The flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2 to which the input clock signal is not gated. The input clock signal of the flip-flop FF3 is also not gated (S302).

  On the other hand, if it is determined in step S307 that the input clock signal is gated in one of the flip-flops FF1 and FF2 (S307 NO), the clock gating cell CGC1 is an AND type clock gating cell. It is determined whether or not (S308).

  When it is determined that the clock gating cell CGC1 is an AND type clock gating cell (S308 YES), the clock gating cell CGC1 is changed from the AND type to the OR type clock gating cell (S309). Then, the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC1 (S304).

  On the other hand, if it is determined in step S308 that the clock gating cell CGC1 is not an AND type clock gating cell (NO in S308), since the clock gating cell CGC2 is an OR type, this is changed from an OR type to an AND type clock gating. Change to a cell (S310). Then, the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC2 (S306).

  Further, the flip-flop insertion unit 104 may perform a design operation as shown in the flowchart of FIG. As shown in FIG. 21, first, the flip-flop inserting unit 104 determines whether or not the input clock signals of the flip-flops FF1 and FF2 at the place where the hold error has occurred are gated (S401).

  If the input clock signals of the flip-flop FF1 and the flip-flop FF2 are not gated (S401 YES), the input clock signal of the flip-flop FF3 is also not gated (S402).

  On the other hand, when it is determined in step S401 that the input clock signal is gated in at least one of the flip-flops FF1 and FF2 (NO in S401), the clock gating cell CGC2 corresponding to the flip-flop FF2 is an AND type. It is determined whether or not it is a clock gating cell (S403).

  If it is determined that the clock gating cell CGC2 is an AND type clock gating cell (YES in S403), the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC2 (S404).

  On the other hand, if it is determined in step S403 that the clock gating cell CGC2 is not an AND type clock gating cell (NO in S403), whether or not the clock gating cell CGC1 corresponding to the flip-flop FF1 is an OR type clock gating cell. Is determined (S405).

  If it is determined that the clock gating cell CGC1 is an OR type clock gating cell (YES in S405), the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is set. It is supplied from the clock gating cell CGC1 (S406).

  On the other hand, if it is determined in step S405 that the clock gating cell CGC1 is not an OR type clock gating cell (NO in S405), whether or not the input clock signal is gated in any one of the flip-flops FF1 and FF2. Is determined (S407).

  If it is determined that the input clock signal is not gated in one of the flip-flops FF1 and FF2 (YES in S407), the flip-flop FF1 in which the input clock signal is not gated and the logic circuit 10 The flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2 to which the input clock signal is not gated. The input clock signal of the flip-flop FF3 is also not gated (S402).

  On the other hand, if it is determined in step S407 that the input clock signal is gated in one of the flip-flops FF1 and FF2 (S407 NO), the clock gating cell CGC2 is an OR type clock gating cell. It is determined whether or not (S408).

  When it is determined that the clock gating cell CGC2 is an OR type clock gating cell (YES in S408), the clock gating cell CGC2 is changed from the OR type to the AND type clock gating cell (S409). Then, the flip-flop FF3 is inserted between the logic circuit 10 and the flip-flop FF2, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC2 (S404).

  On the other hand, if it is determined in step S408 that the clock gating cell CGC2 is not an OR type clock gating cell (NO in S408), since the clock gating cell CGC1 is an AND type, this is changed from an AND type to an OR type clock gating. Change to a cell (S410). Then, the flip-flop FF3 is inserted between the flip-flop FF1 and the logic circuit 10, and the input clock of the flip-flop FF3 is supplied from the clock gating cell CGC1 (S406).

  As described above, the flip-flop insertion unit 104 according to the second exemplary embodiment determines the types of clock gating cells corresponding to the front-stage flip-flop FF1 and the rear-stage flip-flop FF2 that are negative flip-flops. Then, the insertion flip-flop FF3, which is a positive flip-flop, is automatically inserted at a predetermined location according to the determination result, and the corresponding clock gating cell is selected.

  In FIG. 22, the flip-flop insertion unit 104 inserts the insertion flip-flop FF3, the type of the clock gating cell that supplies the input clock signal, and the clock gate corresponding to the front-stage flip-flop FF1 and the rear-stage flip-flop FF2. A table summarizing the types of ting cells is shown.

  As shown in FIG. 22, when both of the clock gating cells CGC1 and CGC2 are OR type clock gating cells, the flip-flop inserting unit 104 places the inserting flip-flop FF3 between the preceding flip-flop FF1 and the logic circuit 10 ( The input clock signal is supplied from the clock gating cell CGC1.

  When the clock gating cells CGC1 and CGC2 are both AND type clock gating cells, the flip-flop inserting unit 104 places the insertion flip-flop FF3 between the logic circuit 10 and the rear-stage flip-flop FF2 (the rear-stage flip-flop FF2). And the input clock signal is supplied from the clock gating cell CGC2.

  When the clock gating cell CGC1 is an OR type clock gating cell and the clock gating cell CGC2 is an AND type clock gating cell, the flip-flop inserting unit 104 replaces the inserting flip-flop FF3 with the preceding flip-flop FF1. 10 (immediately after the previous flip-flop FF1) and the input clock signal is supplied from the clock gating cell CGC1.

  However, depending on the operation of the flip-flop insertion unit 104, the insertion flip-flop FF3 is connected to the rear-stage flip-flop FF2 (immediately before the rear-stage flip-flop FF2), and the input clock signal is supplied from the clock gating cell CGC2. Constitute.

  When the clock gating cell CGC1 is an AND type clock gating cell and the clock gating cell CGC2 is an OR type clock gating cell, the flip-flop insertion unit 104 does not insert the insertion flip-flop FF3 in this state, The clock gating cell CGC2 is changed to an OR type clock gating cell. After the change, the insertion flip-flop FF3 is connected between the previous flip-flop FF1 and the logic circuit 10 (immediately after the previous flip-flop FF1), and the input clock signal is supplied from the clock gating cell CGC1, as described above. Configure to

  However, depending on the operation of the flip-flop insertion unit 104, the clock gating cell CGC1 is changed to an AND type clock gating cell. After the change, similarly to the above, the insertion flip-flop FF3 is connected between the logic circuit 10 and the rear-stage flip-flop FF2 (immediately before the rear-stage flip-flop FF2), and the input clock signal is supplied from the clock gating cell CGC2. Configure to

  The flip-flop insertion unit 104 according to the second embodiment replaces the clock-gated insertion flip-flop FF3, which is a positive flip-flop, with the preceding flip-flop FF1, which is a negative flip-flop, according to the combinations summarized in the table of FIG. And a subsequent flip-flop FF2 which is a negative flip-flop. By this connection method, as in the first embodiment, the operation result is the same between the semiconductor integrated circuit that performs an ideal operation before the insertion of the flip-flop FF3 and the semiconductor integrated circuit after the insertion flip-flop FF3 is inserted. It is possible to insert the insertion flip-flop FF3.

  As described above, the semiconductor integrated circuit design apparatus 100 according to the second embodiment causes an operation error when the clock-gated hold error compensation insertion flip-flop is inserted into the semiconductor integrated circuit in which the hold error has occurred. It is possible to reliably design a semiconductor integrated circuit configuration capable of obtaining a correct operation result without any mistake. Also in this case, as in the first embodiment, the existing clock gating cell can be applied to the insertion flip-flop FF3, and there is no need to install a new clock gating cell for the insertion flip-flop FF3. An increase in the circuit area of the semiconductor integrated circuit can be suppressed. Further, since the insertion flip-flop FF3 is clock-gated, the increase in power consumption of the semiconductor integrated circuit can be reduced as compared with the case where the insertion flip-flop FF3 is not clock-gated.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, the above-described semiconductor integrated circuit design apparatus according to the first and second embodiments may be realized by a computer 200 such as a PC as shown in FIG. Hereinafter, an example in which such a computer 200 constitutes a semiconductor integrated circuit design apparatus will be briefly described. As illustrated in FIG. 23, the computer 200 includes a CPU 201, a main memory 202, an HDD 203, a ROM 204, an input / output device 205, and a bus 206. A bus 206 is connected to the CPU 201, the main memory 202, the HDD 203, the ROM 204, and the input / output device 205, and transmits various types of information.

  The circuit design database described above is stored in the HDD 203 of the computer 200, the database 207 in the network, or the like. Then, the CPU 201 calls a program (hereinafter referred to as a processing program) for realizing the design of the semiconductor integrated circuit of the present invention stored in the HDD 203 or the ROM 204 and develops it in the main memory 202.

  The timing analysis unit 102 and the flip-flop insertion unit 104 described above are modularized in this processing program. Note that an operating system that controls the computer 200 may control each module program.

  For example, a program that operates as the timing analysis unit 102 reads circuit connection information, delay information, and the like from the circuit design database 101 included in the HDD 203 and the like, and generates hold error information 103.

  Then, the program operating as the flip-flop inserting unit 104 generates the circuit connection information 105 by the operation described in the first and second embodiments.

  Note that the timing analysis unit 102 and the flip-flop insertion unit 104 may be realized by dedicated hardware instead of a program.

DESCRIPTION OF SYMBOLS 100, 200 Semiconductor integrated circuit design apparatus 101 Circuit design database 102 Timing analysis part 103 Hold error information 104 Flip-flop insertion part 105 Circuit connection information FF1 Front-stage flip-flop FF2 Rear-stage flip-flop FF3 Insertion flip-flop 10 Logic circuits CGC1, CGC2 Flip flop FF21 provided in the AND type clock gating cell Flip flop AND11 AND circuit OR21 OR circuit provided in the OR type clock gating cell

Claims (8)

The first and second flip-flops that latch and output input data according to a clock signal input to the clock input terminal, and the second flip-flop passes through a predetermined logic circuit. In a semiconductor integrated circuit to which an output signal of one flip-flop is input,
Input data is newly latched between the first flip-flop and the second flip-flop in accordance with a clock signal shifted by a half cycle of the clock signal input to the first or second flip-flop. A method for designing a semiconductor integrated circuit to which a third flip-flop for output is connected,
The semiconductor integrated circuit outputs a signal that is synchronized with a reference clock when at least a first enable signal that is input is activated, and a signal that has a first value when the signal is deactivated A gating circuit;
A second clock gating circuit that outputs a signal synchronized with a reference clock when the second enable signal that is input is activated and a signal that is output when the second enable signal is deactivated; Have either one,
When the clock signal input to the first flip-flop is a signal from the first clock gating circuit, the third flip-flop is connected between the first flip-flop and the logic circuit. Connected between the input clock signal and the signal from the first clock gating circuit,
Alternatively, when the clock signal input to the second flip-flop is a signal from the second clock gating circuit, the third flip-flop is connected to the logic circuit and the second flip-flop. And a method for designing a semiconductor integrated circuit in which the input clock signal is a signal from the second clock gating circuit. The clock signal input to the first flip-flop is a signal from the second clock gating circuit, and the clock signal input to the second flip-flop is the first clock gate. When the signal is from a gating circuit, the second clock gating circuit is changed to the first clock gating circuit, or the first clock gating circuit is changed to the second clock gating circuit. The method of designing a semiconductor integrated circuit according to claim 1 to be changed. The first clock gating circuit includes:
A fourth flip-flop that latches and outputs the first enable signal in response to a clock signal shifted by a half cycle of the reference clock;
2. An AND circuit that inputs the reference clock and a signal output from the fourth flip-flop and uses a product operation result as an output signal of the first clock gating circuit. 3. A method of designing a semiconductor integrated circuit according to 2. The second clock gating circuit includes:
A fifth flip-flop that latches and outputs an inverted signal of the second enable signal in response to a clock signal shifted by a half cycle of the reference clock;
2. An OR circuit that inputs the reference clock and a signal output from the fifth flip-flop and uses a sum operation result as an output signal of the second clock gating circuit. 3. A method of designing a semiconductor integrated circuit according to 2. The first and second flip-flops that latch and output input data according to a clock signal input to the clock input terminal, and the second flip-flop passes through a predetermined logic circuit. In a semiconductor integrated circuit to which an output signal of one flip-flop is input,
Input data is newly latched between the first flip-flop and the second flip-flop in accordance with a clock signal shifted by a half cycle of the clock signal input to the first or second flip-flop. A device for designing a semiconductor integrated circuit to which a third flip-flop for output is connected,
The semiconductor integrated circuit outputs a signal that is synchronized with a reference clock when at least a first enable signal that is input is activated, and a signal that has a first value when the signal is deactivated A gating circuit;
A second clock gating circuit that outputs a signal synchronized with a reference clock when the second enable signal that is input is activated and a signal that is output when the second enable signal is deactivated; Have either one,
When the clock signal input to the first flip-flop is a signal from the first clock gating circuit, the third flip-flop is connected between the first flip-flop and the logic circuit. Connected between the input clock signal and the signal from the first clock gating circuit,
Alternatively, when the clock signal input to the second flip-flop is a signal from the second clock gating circuit, the third flip-flop is connected to the logic circuit and the second flip-flop. And an input clock signal as a signal from the second clock gating circuit. The clock signal input to the first flip-flop is a signal from the second clock gating circuit, and the clock signal input to the second flip-flop is the first clock gate. When the signal is from a gating circuit, the second clock gating circuit is changed to the first clock gating circuit, or the first clock gating circuit is changed to the second clock gating circuit. The semiconductor integrated circuit design apparatus according to claim 5 to be changed. The first and second flip-flops that latch and output input data according to a clock signal input to the clock input terminal, and the second flip-flop passes through a predetermined logic circuit. In a semiconductor integrated circuit to which an output signal of one flip-flop is input,
Input data is newly latched between the first flip-flop and the second flip-flop in accordance with a clock signal shifted by a half cycle of the clock signal input to the first or second flip-flop. A semiconductor integrated circuit design program for connecting the third flip-flop to be output,
The semiconductor integrated circuit outputs a signal that is synchronized with a reference clock when at least a first enable signal that is input is activated, and a signal that has a first value when the signal is deactivated A gating circuit;
A second clock gating circuit that outputs a signal synchronized with a reference clock when the second enable signal that is input is activated and a signal that is output when the second enable signal is deactivated; Have either one,
When the clock signal input to the first flip-flop is a signal from the first clock gating circuit, the third flip-flop is connected between the first flip-flop and the logic circuit. Connected between the input clock signal and the signal from the first clock gating circuit,
Alternatively, when the clock signal input to the second flip-flop is a signal from the second clock gating circuit, the third flip-flop is connected to the logic circuit and the second flip-flop. A program for designing a semiconductor integrated circuit that is connected between the first clock gating circuit and the input clock signal as a signal from the second clock gating circuit. The clock signal input to the first flip-flop is a signal from the second clock gating circuit, and the clock signal input to the second flip-flop is the first clock gate. When the signal is from a gating circuit, the second clock gating circuit is changed to the first clock gating circuit, or the first clock gating circuit is changed to the second clock gating circuit. The semiconductor integrated circuit design program according to claim 7 to be changed.

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