JP2011227908A - Data processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide faster and more efficient emulation in an emulation system which uses a multi-processor architecture.SOLUTION: By dividing the emulation of an emulated processing unit into two (or more) emulating processing units, message traffic necessary for providing communication between the emulation of those emulated processing units is recognized to be able to been reduced. Similarly, by grouping the emulation of multiple processing units which are normally high-traffic between one another (on a single emulating processing unit), the message traffic necessary for providing communication between the emulation of those emulated processing units can be greatly reduced as well.

Description

  The present invention relates to data processing.

  As an example of data processing, an electronic game is well known, and such an electronic game can be supplied by various distribution media such as a magnetic disk, an optical disk, or a magneto-optical disk. These games can be played using a normal computer or a dedicated game machine.

  It may be necessary to emulate the operation of one processor on another. In other words, the emulation side processor executes native program code, but the configuration of the native program code is such that the native instruction or group of native instructions has the same effect as the data processing instruction for the emulated system. It is comprised so that it may have.

  A situation where such a need arises is that a data processor has been upgraded by a manufacturer to a new “generation” (eg, to a new hardware architecture or instruction protocol), but the manufacturer is still an older generation device. It may be desired that the software involved can be used (so-called backward compatibility). In many cases, the only way to accomplish this is for the new generation of devices to run emulation software and the emulation software to operate in response to instructions for the old generation of devices. In this case, of course, it is allowed to use more processor than usual to perform emulation compared to running native software, but the overall trend of progress by generation of data processing hardware performance As a result, an increase in processing overhead can be handled normally.

The present invention is a data processor having a plurality of interconnected actual processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected processed processing units. And
At least one emulated processing unit is emulated by the contribution of two or more actual processing units,
At least one actual processing unit contributes to the emulation of two or more emulated processing units;
A data processor is provided.

  The present invention addresses the problems associated with emulation systems that use multiprocessor architectures, and in particular (but not limited to), communication between processors (in an emulation-side system) It deals with the case where it is slower than the general operation speed. The present invention divides the emulation of a given emulation processing unit into two (or more) emulation processing units, thereby providing a message necessary for providing communication between the emulations of the emulation processing units. Recognizing that traffic can be reduced. Similarly, it is usually necessary to group the emulations of multiple processing units that are busy with each other (on a single emulation-side processing unit) to provide communication between the emulations of the emulation-side processing units. Message traffic can still be significantly reduced. By adopting these means together, faster and more efficient emulation can be provided.

  Various other aspects and features of the present invention are set forth in the appended claims.

  Embodiments of the present invention are described below with reference to the accompanying drawings, which are for illustration only.

FIG. 1 schematically illustrates the overall system architecture of the PlayStation 2. FIG. 2 is a diagram schematically showing an architecture of an emotion engine. FIG. 3 is a diagram schematically showing the configuration of the graphics synthesizer. FIG. 4 is a diagram schematically showing the structure of an emulation-side processor, particularly a Sony (registered trademark) PlayStation 3 (registered trademark) device. FIG. 5 is a diagram schematically showing the cell processor. FIG. 6 is a diagram schematically showing the graphics unit. FIG. 7 is a diagram schematically showing a logical interaction in the emulation processor.

  Referring to the figure, FIG. 1 schematically illustrates the overall system architecture of a PlayStation 2 computer game machine. A system unit 10 is provided, and various peripheral devices can be connected to the system unit.

  The system unit 10 includes an emotion engine 100, a graphics synthesizer 200, a sound processor unit 300 having a dynamic random access memory (DRAM), a read only memory (ROM) 400, and a compact disc (CD) / DVD disc (DVD). ) Read device 450, Rambus DRAM (RDRAM) unit 500, and input / output processor (IOP) 700 with dedicated RAM 750. As an option, an external hard disk drive (HDD) 390 can be connected.

  The input / output processor 700 has two universal serial bus (USB) ports 715 and an iLink or IEEE1394 port (not shown) (iLink is an IEEE 1394 standard implemented by Sony). The IOP 700 handles all USB, iLink and game controller data traffic. For example, when the user is playing a game, the IOP 700 receives data from the game controller and transmits the received data to the emotion engine 100, which updates the current state of the game accordingly. The IOP 700 has a direct memory access (DMA) architecture to achieve high data transfer rates. DMA involves transferring data from main memory to the device without passing it through the CPU. The USB interface conforms to the open host controller interface (OHCI) and can process data transfer rates of 1.5 Mbps to 12 Mbps. By providing these interfaces, the PlayStation 2 may be compatible with peripheral devices such as digital video cassette recorders (VCRs) such as camcorders, digital cameras, microphones, printers, keyboards, input devices such as mice and joysticks. is doing.

  In general, in order to successfully realize data communication with a peripheral device connected to the USB port 715, it is necessary to provide appropriate software such as a device driver. Device driver technology is well known and will not be described in detail here, but those skilled in the art know that device drivers and similar software may be required in the embodiments described herein. Yes.

  In this embodiment, a USB microphone 730 is connected to the USB port. It will be appreciated that the USB microphone 730 may be a handheld microphone or may be part of a headset worn by the operator. The advantage of wearing a headset is that the operator's hand is free to perform other actions. Since the microphone includes an analog-to-digital converter (ADC) and a basic hardware-based real-time data compression encoder, the microphone 730 allows the audio data to be in a format suitable for decoding by the PlayStation 2 system unit 10. For example, the data is transmitted to the USB port 715 in a streaming compressed audio format.

  Aside from the USB port, the other two ports 705 and 710 are sockets of a unique specification, and a proprietary nonvolatile RAM memory card 720 for storing game-related information, a handheld game controller 725, or Devices (not shown) such as dance mats that mimic handheld controllers can be connected.

  The system unit 10 can be connected to a network adapter 805 that provides an interface to a network (eg, Ethernet interface). This network can be, for example, a LAN, a WAN, or the Internet. The network may be a general network or a network dedicated to game-related communication. The network adapter 805 can transmit data to other system units 10 connected to the same network, and can receive data from other system units 10 (other system units 10 also have corresponding network adapters 805. ).

  Emotion engine 100 is a 128-bit central processing unit (CPU) specially designed for efficient simulation of three-dimensional (3D) graphics for gaming applications. The Emotion Engine components include a data bus, a cache memory (part of the CPU core), and registers, all of which are 128-bit types. This facilitates high-speed processing of a large amount of multimedia data. As a comparison, a conventional PC has a 64-bit basic data structure. The performance of the floating point calculation of PlayStation 2 is 6.2 gigaflops (GFLOPS). The Emotion Engine also has an MPEG2 decoder circuit, which allows simultaneous processing of 3D graphics data and DVD data. The Emotion Engine performs geometric calculations including mathematical transformations and translations, and performs calculations related to the physics of the simulated object, eg, the friction between two objects. The emotion engine generates a sequence of image rendering commands that are later utilized by the graphics synthesizer 200. The image rendering command is output in the form of a display list. The display list is a sequence of drawing commands that specifies to the graphics synthesizer which basic graphics objects (eg, points, lines, triangles, sprites) should be drawn at which coordinate positions on the screen. Therefore, a typical display list has a command for drawing a vertex, a command for shading a polygon (polygon) surface, and the like. The emotion engine 100 can generate a plurality of display lists asynchronously.

  The graphics synthesizer 200 is a video accelerator that performs rendering of a display list generated by the emotion engine 100. Graphics synthesizer 200 includes a graphics interface unit (GIF), which processes, tracks and manages a plurality of display lists. The rendering function of the graphics synthesizer 200 can generate image data compatible with several alternative standard output image formats (ie, NTSC / PAL, high definition television and VESA). In general, the rendering performance of a graphics system is defined by the memory bandwidth between the pixel engine and video memory (both located within the graphics processor). Conventional graphics systems use external video random access memory (VRAM), which is connected to the pixel logic by an off-chip bus, so the available bandwidth tends to be limited. However, since the graphics synthesizer 200 of the PlayStation 2 has pixel logic and video memory on a single high performance chip, a relatively large memory access bandwidth of 38.4 gigabytes per second is possible. The graphics synthesizer can theoretically achieve peak drawing performance of 75 million polygons per second. Even when a set of effects such as texture, lighting and transparency is used, it is possible to continuously draw at a speed of 20 million polygons per second. Thus, the graphics synthesizer 200 can draw a film quality image.

  The sound processor unit (SPU) 300 is effectively the sound card of this system, also known as digital theater surround (DTS®) sound, or AC-3 (Dolby Digital), a sound format for DVDs. 3D digital sound can be handled.

  A display / sound output device 305 such as a video monitor or a television provided with the attached speaker device 310 is connected to receive video signals and audio signals from the graphics synthesizer 200 and the sound processing unit 300.

  The main memory that supports the Emotion Engine 100 is an RDRAM (Rambus Dynamic Random Access Memory) module 500 licensed from Rambus Incorporated. The RDRAM memory subsystem includes a RAM, a RAM controller, and a bus that connects the RAM to the emotion engine 100.

  FIG. 2 schematically illustrates the architecture of the emotion engine 100 of FIG. The emotion engine 100 is a general term for several processing units that are connected to each other to realize a desired function set. From this context point of view, the Emotion Engine includes a floating point unit (FPU) 104, a central processing unit (CPU) core 102, a vector unit 0 (VU0) 106, and a vector unit 1 (VU1). 108, a graphics interface unit (GIF) 110, an interrupt controller (INTC) 112, a timer unit 114, a direct memory access controller 116, an image data processor unit (IPU) 118, and a dynamic random access memory controller (DRAMC). ) 120 and a sub-bus interface (SIF) 122, all these individual processing units are connected by a 128-bit main bus 124.

  The CPU core 102 is a 128-bit processor that operates with a clock of 300 MHz (actually 294.912 MHz, but 300 MHz tends to be used as an abbreviation for this number). The CPU core can access the 32 MB main memory via the DRAMC 120. The instruction set of CPU core 102 is based on MIPS III RISC, with some MIPS IV RISC instructions and additional multimedia instructions. MIPS III and IV are reduced instruction set computer (RISC) instruction set architectures owned by MIPS Technologies, Inc. The standard instruction is a 64-bit 2-way superscaler, which means that two instructions can be executed simultaneously. On the other hand, multimedia instructions utilize 128-bit instructions via two pipelines. The CPU core 102 has a 16 KB instruction cache, an 8 KB data cache, and a 16 KB scratch pad RAM. The scratch pad RAM is a part of a cache connected to the CPU via a dedicated bus. Can access data independently.

  The FPU 104 serves as a first coprocessor for the CPU core 102. The vector operation unit 106 functions as a second coprocessor. The FPU 104 has a floating point division calculator (FDIV). Vector arithmetic units 106 and 108 perform mathematical operations, but are essentially specialized FPUs with very fast evaluation of multiplication and addition of vector equations. These vector operation units use a floating point multiplier / adder (FMAC) for addition and multiplication operations and a floating point divider (FDIV) for division and square root operations. FMAC operates on a 32-bit value, so if the operation is performed on a 128-bit value (consisting of four 32-bit values), the operation can be performed on four parts simultaneously. For example, two vectors can be added simultaneously. The vector operation unit (VU) has a built-in memory for storing a microprogram, and the vector operation unit (VIF) (referred to by the same number as the corresponding vector operation unit) Interfacing with the rest of the system. Vector arithmetic unit 0 106 is essentially a second specialized FPU because it can function as a coprocessor to CPU core 102 via a dedicated 128-bit bus. On the other hand, the vector arithmetic unit 1 108 has a dedicated bus for the graphics synthesizer 200 and can therefore be considered a completely separate processor. By providing two vector operation units, the software developer can divide the work among different parts of the CPU, and the vector operation units can be used in series or parallel connection.

  The vector arithmetic unit 0 106 has four FMACs and one FDIV. The vector arithmetic unit 0 is connected to the CPU core 102 by a coprocessor connection. The vector operation unit 0 has a 4 KB vector operation unit memory for data and a 4 KB micro memory for instructions. Vector arithmetic unit 0 106 is useful for performing physical calculations related to the image to be displayed. Vector arithmetic unit 0 106, together with CPU core 102, primarily performs unpatterned geometric processing.

  The vector operation unit 1 108 has 5 FMACs and 1 FDIV. The vector operation unit 1 does not have a direct path to the CPU core 102 but has a direct path to the GIF unit 110. The vector operation unit 1 has a 16 KB vector operation unit memory for data and a 16 KB micro memory for instructions. Vector arithmetic unit 1 108 is useful for performing transformations. The vector operation unit 1 mainly executes the patterned geometric processing and outputs the generated display list directly to the GIF 110.

  The GIF 110 is an interface unit to the graphics synthesizer 200. The GIF 110 converts the data according to the tag specification at the beginning of the display list packet, transfers the drawing command to the graphics synthesizer 200, and arbitrates a plurality of transfers with each other. An interrupt controller (INTC) 112 arbitrates interrupts from peripheral devices other than the DMAC 116.

  The timer unit 114 has four independent timers with 16-bit counters. These timers are driven by a bus clock (1/16 or 1/256 interval) or an external clock. The DMAC 116 handles data transfer between the main memory and the scratch pad RAM, or between the main memory or the scratch pad RAM and the peripheral device. At the same time, the DMAC 116 arbitrates the main bus 124. Optimizing the performance of the DMAC 116 is the primary method for improving the performance of the emotion engine. An image processing unit (IPU) 118 is an image data processor used to decompress compressed moving images and texture images. Image processing unit 118 performs macroblock decoding, color space conversion, and vector quantization. Finally, the sub-bus interface (SIF) 122 is an interface unit to the IOP 700. The IPU has its own memory and bus to control I / O devices such as sound chips and storage devices.

  FIG. 3 is a diagram schematically showing the configuration of the graphics synthesizer 200. The graphics synthesizer has a host interface 202, a pixel pipeline 206, a memory interface 208, a local memory 212 including a frame page buffer 214 and a texture page buffer 216, and a video converter 210.

  The host interface 202 transfers data to and from the host (in this case, the GIF 110). Both drawing data and buffer data from the host pass through this interface. The output from the host interface 202 is supplied to the graphics synthesizer 200. The graphics synthesizer 200 decompresses the graphics and draws pixels based on the vertex information received from the emotion engine 100, and the RGBA value, depth for each pixel. Information such as value (Z value), texture value and fog value is calculated. The RGBA value designates red, green and blue (RGB) color components and an A component (alpha component) indicating the opacity of the image object. Alpha values can range from completely transparent to completely opaque. Pixel data is supplied to the pixel pipeline 206, which performs processes such as texture mapping, fogging, and alpha blending, and determines the final drawing color based on the calculated pixel information.

  The pixel pipeline 206 includes 16 pixel engines PE1, PE2,. . . , PE16, a maximum of 16 pixels can be processed simultaneously. The pixel pipeline 206 operates at 150 MHz (actually 294.912 / 2 MHz), is 32-bit color and has a 32-bit Z buffer. The memory interface 208 reads / writes data from / to the local graphics synthesizer memory 212. The memory interface 208 writes the drawing pixel values (RGBA and Z) to the memory at the end of the pixel operation, and reads the pixel values of the frame buffer 214 from the memory. These pixel values read from the frame buffer 214 are used for pixel testing or alpha blending. The memory interface 208 also reads RGBA values for the current contents of the frame buffer from the local memory 212. The local memory 212 is a 32 Mbit (4 MB) memory built in the graphics synthesizer 200. The local memory 212 can be configured as a frame buffer 214, a texture buffer 216, and a Z buffer 215. The frame buffer 214 is a part of the video memory, and stores pixel data such as color information.

  The graphics synthesizer uses a 2D-3D texture mapping process to give visual details to 3D figures. Each texture can be wrapped around a 3D image object, stretched, and distorted to give a 3D graphic effect. The texture buffer is used to store texture information for the image object. Z buffer 215 (also known as depth buffer) is a memory that can be used to store pixel depth information. An image is composed of basic building blocks known as graphics basic elements or polygons. When a polygon is rendered by Z buffering, the depth value of each of the pixels is compared with the corresponding value stored in the Z buffer. If the value stored in the Z buffer is greater than or equal to the depth value of the new pixel value, the pixel is determined to be visible, the pixel is rendered, and the Z buffer is updated with the new pixel depth value. However, if the depth value of the Z buffer is smaller than the new pixel depth value, the new pixel value is hidden by what has already been drawn and is not rendered. Alternatively, a Z buffer test can be used: (a) a new pixel always replaces the previous value, or (b) if the new pixel depth is greater than or equal to the previous value stored in the Z buffer. , The new pixel replaces the previous pixel value.

  The local memory 212 includes a 1024-bit read port and a 1024-bit write port for accessing the frame buffer and the Z buffer, and a 512-bit port for reading textures. Video converter 210 is operable to display the contents of the frame memory in a specified output format.

  Next, a configuration that enables emulation of the system described with reference to FIGS. 1 to 3 will be described. It should be noted that for the sake of convenience, the processing unit shown in FIGS. 1 to 3 is referred to as the “emulated side” processing unit, whereas in the emulation system described below, the processing unit of that (emulation) system. Will be referred to as the “emulation side” processing unit. To avoid any confusion that may arise, both types of processing units (both “emulated” units and “emulation side” units) are physical processing units and are appropriate native to those processing units. It should be noted that each software can be executed.

  FIG. 4 schematically illustrates the overall system architecture of a Sony® PlayStation 3® entertainment device. The system unit 910 is provided with various peripheral devices that can be connected to the system unit.

  The system unit 910 includes a cell processor 1100, a Rambus® dynamic random access memory (XDRAM) unit 1500, a reality synthesizer graphics unit 1200 including a dedicated video random access memory (VRAM) unit 1250, an I / O And a bridge 1700.

  The system unit 910 also includes a Blu-ray (registered trademark) disk BD-ROM (registered trademark) optical disk reader 1430 for reading the disk 1440, and a removable slot-in hard disk drive (HDD) 1400. Can be accessed via the I / O bridge 1700. Optionally, the system unit also has a memory card reader 1450 for reading a CompactFlash® memory card, a Memory Stick® memory card, etc., as well via an I / O bridge 1700. Can be accessed.

  The I / O bridge 1700 also includes six universal serial bus (USB) 2.0 ports 1710, a Gigabit Ethernet port 1720, an IEEE 802.11b / g wireless network (Wi-Fi) port 1730, It is connected to a Bluetooth® wireless link port 1740 that can support seven Bluetooth connections.

  In operation, the I / O bridge 1700 handles all wireless, USB, and Ethernet data, including data from one or more game controllers 1751. For example, if the user is playing a game, the I / O bridge 1700 receives data from the game controller 1751 via the Bluetooth link and directs the data to the cell processor 1100, which in accordance with the game's Update the current state.

  In addition to the game controller 1751, other peripheral devices can be connected through a wireless port, a USB port, and an Ethernet (registered trademark) port. As such peripheral devices, a remote controller 1752, a keyboard 1753, a mouse 1754, a Sony PlayStation Portable ( A portable entertainment device 1755 such as a registered trademark entertainment device, a video camera 1756 such as an eye toy video camera, a microphone headset 1757, and the like. Accordingly, such peripheral devices can in principle be connected to the system unit 910 wirelessly. For example, portable entertainment device 1755 can communicate over a Wi-Fi ad hoc connection and microphone headset 1757 can communicate over a Bluetooth link.

  The provision of these interfaces means that the PlayStation 3 device has other peripherals such as a digital video recorder (DVR), set-top box, digital camera, portable media player, voice over IP phone, mobile phone, printer, scanner, etc. It means that there is a possibility that the device can be supported.

  In addition, a legacy memory card reader 1410 can be connected to the system unit via the USB port 1710 so that the type of memory card 1420 used by the PlayStation® or PlayStation 2® device can be read. It becomes possible.

  In the present embodiment, the game controller 1751 can perform wireless communication with the system unit 910 via a Bluetooth link. However, as an alternative, the game controller 1751 may be connected to a USB port, whereby power to charge the battery of the game controller 1751 can be supplied. In addition to one or more analog joysticks and conventional control buttons, the game controller can sense six degrees of freedom movement corresponding to translation and rotation on each axis. As a result, in addition to or in place of the conventional buttons or joystick commands, gestures and actions by the game controller user can be converted into input to the game. Optionally, other peripheral devices that can be used wirelessly, such as a PlayStation portable device, can be used as the controller. In the case of a PlayStation portable device, additional game information or control information (eg, a control command or a number that can be retried until the game is over) can be provided on the screen of the device. Other alternative or auxiliary control devices can be used, such as a dance mat (not shown), light gun (not shown), steering wheel and pedal (not shown), or quick response Custom controllers such as one or several large buttons for a quiz game can also be used.

  The remote controller 1752 can also perform wireless communication with the system unit 910 via the Bluetooth link. The remote controller 1752 has appropriate controls for the operation of the Blu-ray Disc BD-ROM reader 1430 and the operation of the disc content.

  The Blu-ray Disc BD-ROM reader 1430 can read CD-ROMs suitable for PlayStation and PlayStation 2 devices in addition to conventional recorded or write-once CDs and so-called super audio CDs. The reader 1430 can also read DVD-ROMs compatible with PlayStation 2 and PlayStation 3 devices in addition to conventional recorded or write-once DVDs. Further, the reading device 1430 can read a BD-ROM adapted to the PlayStation 3 in addition to a conventional recorded or write-once Blu-ray disc.

  The system unit 910 can provide audio and video via an audio connector and a video connector to a display / sound output device 1300 such as a monitor or television having a display screen 1305 and one or more speakers 1310. Those audio and video are generated or decoded by the PlayStation 3 device by the reality synthesizer graphics unit 1200. Audio connector 1210 can include conventional analog as well as digital outputs, while video connector 1220 includes various component video, S-video, composite video, and one or more high definition multimedia interface (HDMI) outputs. Can do. As a result, the video output can be in a PAL format, NTSC format, or a high definition format in 720p, 1080i, 1080p.

  Audio processing (generation, decoding, etc.) is performed by the cell processor 1100. The PlayStation 3 device operating system supports decoding Dolby 5.1 Surround Sound, Dolby® Theater Surround (DTS), and 7.1 Surround Sound from Blu-ray® discs .

  In this embodiment, the video camera 1756 has one charge-coupled device (CCD), an LED indicator, and a hardware-based real-time data compression encoding device. It can be transmitted in a format suitable for decoding by the system unit 910, such as a motion picture expert group (MPEG) standard. The LED indicator of the camera is adapted to illuminate light in accordance with appropriate control data from the system unit 910, and informs that the lighting conditions are bad, for example. Embodiments of video camera 1756 can be connected to system unit 910 in various ways, such as via USB, Bluetooth, or Wi-Fi communication ports. Video camera embodiments can include an associated microphone and can also transmit audio data. In video camera embodiments, the CCD resolution may be suitable for high definition video capture. In use, the image captured by the video camera can be incorporated into the game or interpreted as input to control the game.

  In general, in order to successfully implement data communication with a peripheral device such as a video camera or remote control via one of the communication ports of the system unit 910, appropriate software such as a device driver must be provided. . Device driver technology is well known and will not be described in detail here, but it will be known to those skilled in the art that a device driver or similar software interface is required in this embodiment.

  Referring now to FIG. 5, the architecture of cell processor 1100 includes four basic components: an external input / output structure having a memory controller 1160 and dual bus interface controllers 1170A, 1170B, and a power processing element (PPE) 1150. A main processor referred to, eight coprocessors referred to as synergistic processing elements (SPE) 1110A-1110H, and a circular data bus referred to as an element interconnect bus 1180 connecting the components Yes. The overall floating point arithmetic performance of the cell processor is 218 GFLOPS, and the Emotion Engine of the PlayStation 2 device is 6.2 GFLOPS.

  The power processing element (PPE) 1150 is based on a power PC core (PPU) 1155 that supports a bidirectional multi-threading power 970 that operates with an internal clock of 3.2 GHz. The PPE 1150 has a 512 kB secondary (L2) cache and a 32 kB primary (L1) cache. The PPE 1150 can perform single precision operations 8 times per clock cycle, in other words, 25.6 GFLOPS at 3.2 GHz. The main role of the PPE 1150 is to function as a controller for the synergistic processing elements 1110A-1110H, and the synergistic processing elements 1110A-1110H handle the majority of the computational workload. In operation, PPE 1150 maintains a job queue, schedules jobs for synergistic processing elements 1110A-1110H, and monitors their progress. As a result, each of the synergistic processing elements 1110A-1110H executes a kernel, but the role of the kernel is to fetch and execute jobs and synchronize with the PPE 1150.

  Each synergistic processing element (SPE) 1110A-1110H includes a respective synergistic processing unit (SPU'-to distinguish it from the sound processing unit) 1120A-1120H and a respective memory flow controller (MFC) 1140A- Each memory flow controller MFC includes a dynamic memory access controller (DMAC) 1142A-1142H, a respective memory management unit (MMU) 1144A-1144H, and a bus interface (not shown). Not). Each SPU'1120A-1120H is a RISC processor driven by a 3.2 GHz clock and has a 256 kB local RAM 1130A-1130H, but the local RAM can be expanded to 4 GB in principle. Each SPE can theoretically realize single-precision computing performance of 25.6 GFLOPS. SPU 'can perform operations on four single precision floating point numbers, or four 32-bit numbers, or eight 16-bit integers in a single clock cycle. In the same clock cycle, SPU 'can also perform memory operations. SPU'1120A-1120H does not directly access system memory XDRAM 1500. The 64-bit address created by SPU'1120A-1120H is handed over to MFC 1140A-1140H so that MFC 1140A-1140H accesses the memory via its element interconnect bus 1180 and memory controller 1160 to its DMA controller 1142A-1142H. Command.

  An element interconnect bus (EIB) 1180 is a logically circulating communication bus in the cell processor 1100. The processor element, that is, the PPE 1150, the memory controller 1160, the dual bus interfaces 1170A and 1170B, and the eight SPEs 1110A. -1110H, ie a total of 12 participating elements. Participating elements can simultaneously read from and write to the bus at a rate of 8 bytes per clock cycle. Each SPE 1110A-1110H has a DMAC 1142A-1142H as described above to schedule a long read or write sequence. The EIB has four channels, two clockwise and two counterclockwise. Thus, for 12 participating elements, the longest stepwise data flow between any two participating elements is 6 steps in the appropriate direction. Thus, the theoretical peak instantaneous EIB bandwidth for 12 slots is 96B (bytes) per clock, when fully utilized by arbitration between participating elements. This is equivalent to a theoretical peak bandwidth of 307.2 GB / s (gigabytes / second) for a clock rate of 3.2 GHz.

  The memory controller 1160 has an XDRAM interface 1162 developed by Rambus Incorporated. The memory controller interfaces to the Rambus XDRAM 1500 with a theoretical peak bandwidth of 25.6 GB / s.

  The dual bus interfaces 1170A, B have Rambus FlexIO (registered trademark) system interfaces 1172A, B. The interface is organized into 12 channels, each channel is 8 bits wide, 5 paths are inbound and 7 paths are outbound. Thus, 62.4 GB / s (outbound 36.4 GB / s) is transmitted between the cell processor and the I / O bridge 1700 via the controller 1170A and between the reality simulator graphics unit 1200 via the controller 1170B. , A theoretical peak bandwidth of inbound 26 GB / s) is provided.

  The data sent to the reality simulator graphics unit 1200 by the cell processor 1100 usually consists of a display list. The display list is a command for drawing vertices, a command for applying textures to polygons, a command for specifying lighting conditions, etc. This is the sequence.

  Referring now to FIG. 6, the reality simulator graphics (RSX) unit 1200 is a video accelerator based on the NVidia® G70 / 71 architecture that processes the list of commands generated by the cell processor 1100. , Render. The RSX unit 1200 includes a host interface 1202 capable of communicating with the bus interface controller 1170B of the cell processor 1100, a vertex pipeline (VP) 1204 including eight vertex shaders 1205, and a pixel pipe including 24 pixel shaders 1207. It includes a line (PP) 1206, a render pipeline (RP) 1208 with eight render output units (ROP) 1209, a memory interface 1210, and a video converter 1212 that generates video output. The RSX 1200 is complemented by a 256 MB double data rate (DDR) video RAM (VRAM) 1250 that operates with a 600 MHz clock and can interface with the RSK 1200 with a theoretical peak bandwidth of 25.6 GB / s. In operation, the VRAM 1250 holds a frame buffer 1214 and a texture buffer 1216. Texture buffer 1216 provides texture to pixel shader 1207 and frame buffer 1214 stores the results of the processing pipeline. The RSX can access the main memory 1500 via the EIB 1180 to load textures into the VRAM 1250, for example.

  The vertex pipeline 1204 primarily handles vertex transformations and transformations that define the polygons in the rendered image.

  The pixel pipeline 1206 primarily handles the application of color, texture, and lighting to those polygons, including pixel transparency. The pixel pipeline also generates red, green, blue and alpha (transparency) values for each pixel processed. Texture mapping can be simply applying a graphics image to the surface, or bump mapping (a method that generates highlights and shades in the lighting model by perturbing the conceptual orientation of the surface according to the texture value) or Displacement mapping (a method in which the applied texture further perturbs the position of the vertices to produce a deformed surface that matches the texture).

  The render pipeline 1208 compares the depth between pixels to determine which to render in the final image. As an option, if the pixel process in the middle does not affect the depth value (for example, if there is no transparency or displacement mapping), the render pipeline and the vertex pipeline 1204 notify each other of the depth information, and the invisible elements are processed by pixel processing. By removing it in advance, the overall rendering efficiency can be improved. In addition, the render pipeline 1208 also applies subsequent effects, such as full screen anti-aliasing, to the resulting image.

  Both the vertex shader 1205 and the pixel shader 1207 are based on the shader model 3.0 standard. Up to 136 shader operations can be performed every clock cycle, and the concatenated pipeline can perform 74.8 billion shader operations per second, outputting up to 840 million vertices and 10 billion pixels per second. The overall floating point performance of RSX1200 is 1.8TFLOPS.

In general, the RSX 1200 operates in close cooperation with the cell processor 1100. For example, when displaying weather effects such as explosions, rain or snow, it is necessary to trace the traces of many particles, update them, and render them in the scene. In this case, the cell processor PPU 1155 must schedule one or more SPEs 1110A-1110H to calculate the trajectory of each swarm of particles. Meanwhile, if there is texture data (for example, snowflakes) that is not currently held in the video RAM 1250, the RSX 1200 sends the texture data from the main system memory 1500 via the element interconnect bus 1180, the memory controller 1160, and the bus interface controller 1170. read out. The (or each) SPE 1110A-1110H outputs the computed particle properties (typically coordinates and normals indicating position and orientation) directly to the video RAM 1250, but the (or each) SPE 1110-1110H DMA Controllers 1142A-1142H address video RAM 1250 via bus interface controller 1170B. Thus, the assigned SPE is effectively part of the video processing pipeline for the life of the task. In general, the PPU 1155 will thus assign tasks to six of the eight available SPEs in this way. assign. That is, one SPE is reserved for the operating system, while one SPE is arbitrarily disabled. When one SPE is prohibited from being used, the failure of the manufacturing process by one SPE can be allowed, so that the level of the allowable value at the time of manufacturing the cell processor can be increased. Alternatively, if all eight SPEs are operational, the eighth SPE can provide redundancy for later failure by one of the other SPEs during the lifetime of the cell processor.

  PPU 1155 can assign tasks to SPEs in various ways. For example, by chaining SPEs to each other, steps of complicated operations such as DVD access, video and audio decoding, error masking, etc. can be assigned to separate SPEs for handling. Alternatively or additionally, the input data can be assigned to be handled in parallel by two or more SPEs, such as in the case of the particle animation example described above.

  Software instructions executed by cell processor 1100 and / or RSX 1200 may be supplied at the time of manufacture and stored in HDD 1400 and / or by a data carrier or storage medium such as an optical disk or solid state storage device, or wired Alternatively, it may be supplied by a transmission medium such as a wireless network or Internet connection, or a combination thereof.

  The software supplied at the time of manufacture includes system firmware and an operation system (OS) of the PlayStation 3 device. In operation, the OS provides a user interface for the user to select from a variety of functions, such as playing games, listening to music, watching photos, or watching videos. included. This interface takes the form of a so-called cross media bar (XMB), in which various types of functions are arranged horizontally. The user operates by moving horizontally between functions so as to highlight a desired function using the game controller 1751, remote control 1752, or other suitable control device, but at the highlighted function location. The options related to the function appear as a list that can be scrolled vertically to a position centered on the function, and the list can be manipulated in a similar manner. However, when a game, audio or movie disc 1440 is inserted into the BD-ROM optical disc reader 1430, the PlayStation 3 device may automatically select the appropriate option (eg, start the game). Alternatively, an appropriate option (for example, selection between playback of an audio disc and compression of the content into the HDD 1400) may be provided.

  In addition, the OS provides online functionality, including an interface to a web browser and an online store where additional game content, demo versions, and other media can be downloaded, as well as other devices designated by the user of the device. A friend management function that provides online communication with the user of the PlayStation 3 device is included, and text, audio, and video may be used depending on the peripheral devices available. The online function also supports online communication, content download, and content purchase when playing a properly set game, and supports firmware and OS updates for the PlayStation 3 device itself.

  The fact that the emulation-side processing unit of FIGS. 4 to 6 has (roughly speaking) a different architecture, speed, memory access function, etc. compared to the emulation-side processing unit of FIGS. Nevertheless, the operation of the PS2 configuration described with reference to FIGS. 1 to 3 is reproduced (or almost reproduced) by software executed on the configurations of FIGS.

  The reproduction of the operation of the PS2 configuration is emulation rather than simulation. That is, not all of the operations that contribute to the PS2 function are reproduced on the emulation side system for each clock in an inflexible manner. Rather, certain functions may be performed in a time-sharing manner on a single emulation-side processing unit, and the processing units generally communicate with each other only when needed (within the emulated system).

  The PPE 1150 controls the overall operation of the emulation side system and executes an operating system (OS) for the emulation side system. The PPE 1150 also translates the native emotion engine PS2 instructions into native SPE instructions in a single thread and related information needed to execute each part of the emulation (such as allocation of emulation functions-see description below) To the appropriate SPE via the EIB. Other threads, on the other hand, provide the emulation system with the ability to recompile new code that is native and provide specific functionality defined by the translated PS2 code. The emulation of the various parts of the PS2 system described above is transferred to eight SPEs acting as emulation-side processing units, which emulate the PS2 functions shown below. It will be appreciated that the precise identification of individual SPEs is merely for convenience of notation and is not of technical importance due to the nature of message passing between SPEs. Thus, for example, operations assigned to SPEs 1110A and 1110B can be interchanged without any technical impact on the overall emulation process. It will also be appreciated that a task can actually be divided among the remaining 7 SPEs, as described above, since one SPE can be disabled.

SPE1110A IPU118
SPE1110B Emotion Engine CPU102 and Vector Arithmetic Unit 0
SPE1110C VIF0, VIF1, GIF110
SPE1110D Vector arithmetic unit 1
SPE1110E GS200 (ie PS2 specific part of GS200 operation; SPE1110G also interfaces with emulation graphics controller (not shown) for graphics operations not specific to PS2)
SPE1110F Although not generally used, the code can be recompiled to emulate the vector arithmetic unit 1 to reduce the load on one thread of the PPE1150. SPE1110G SPU300
SPE1110H IOP700 and SIF122
PS2 uses a conventional bus for communication between various emulated processing units. The emulation side system uses the EIB 1180 to pass messages between SPEs and between SPEs, PPEs 1150 and I / O bridges 1700 (and / or other system devices such as RSX 1200). The PS2 system has a conventional memory access configuration for accessing the RDRAM 500. The emulated system uses a distributed DMA system (DMA controllers 1142A-1142H). The main system memory 1500 is treated as a common memory “pool” and all SPEs can access it.

  Each SPE operates locally with its own time clock. The SPE executes software to allow emulation of some of the functions of the PS2 system. With respect to the EPUs, synchronization is required only when the processing units to be emulated that are emulated by the EPU need to communicate with each other. At that time, synchronization is only performed between the devices involved, and is done using a message transfer mechanism via the EIB.

  To achieve this, if synchronization between the two SPEs (function of the emulated side) is required, one SPE issues a message on the EIB addressing the other SPE (source SPE identifier, destination Including the Nation SPE identifier). This message can include a charge for certain data, or it can include a data item sent to the other SPE that is involved in that particular synchronization. The transaction is completed when an acknowledgment is returned from the other SPE. While this is a reliable way to synchronize between the emulation side processors, it is a rather slow method.

  The manner in which the SPEs are logically arranged is shown schematically in FIG. Examples of logical communication paths between SPEs are also shown, but these are not exhaustive. If several functions share the same SPE, the need to use a message passing mechanism for communication can be completely avoided. Thus, providing emulation of two (or more) processed processing units on a single SPE can improve system performance by reducing the amount of communication required between SPEs.

  Another feature not shown exhaustively in FIG. 5 for the sake of clarity of the figure is that the emulated processing units emulated by two different SPEs are in large quantities with each other to perform a specific function of PS2. If there is a need to communicate, some of the functions of one actual processor can be performed by the SPE of the “other” processor.

  For example, a PS2 sound processing unit is almost emulated by one SPE. The SPE processes the samples and mixes them into the final sample for output. It also handles access to that register map. However, it is the SPE on the IOP that emulates the registers used to write to the sound processing unit's sample memory, which manages the access queue and directly accesses the sample memory image in the main memory, where they occur. Interrupts that can be generated are generated as if they were sent from the sound processing unit.

  Another example of a PS2 system device implemented with two or more SPEs is the DMAC, whose function is distributed to the components on the emulation side that are mainly used for the Emotion Engine, VIF, GIF, IPU, etc. The

  An example in which a single emulation-side SPE handles the emulation of multiple PS2 system devices is a case where a single emulation-side device shares the majority of PS2 IOP emulation and CD disk controller emulation. .

  The emulation of the processing unit to be emulated is divided into two (or more) SPEs (emulation processing units). This is a message necessary for realizing communication between the emulations of the processing units to be emulated. Traffic can still be reduced. The PPE can change which SPE emulates a particular emulated processing unit and / or which emulated processing unit is emulated by a particular SPE (overall emulation operations). ) Distribution of emulation tasks among SPEs can be changed.

  Computer program providing such software control when such an embodiment of the present invention described above is implemented (at least in part) using a software-controlled data processing device, such computer program It will be understood that a storage medium in which is stored and a transmission medium for transmitting such a computer program are envisaged as features of the present invention. It should be noted that such software can be provided by a storage medium such as an optical disc or hardware memory and / or a transmission medium such as a network connection or the Internet.

Claims (13)

A data processor having a plurality of interconnected emulation-side processing units arranged to emulate the operation of a processor to be emulated with a plurality of interconnected emulation-side processing units,
At least one emulated processing unit is emulated by the contribution of two or more emulation processing units,
At least one emulation processing unit contributes to the emulation of two or more emulated processing units;
A data processor characterized by that. The data processor according to claim 1, wherein the emulation-side processing units communicate with each other by a message passing communication protocol. 3. A data processor according to claim 2, wherein the emulation processing unit is configured to synchronize the emulated operation via the message passing communication protocol. 4. A data processor according to claim 2, wherein the emulation-side processing units are interconnected by a circular data bus. 5. The data processor according to claim 4, wherein the data bus is a bidirectional bus. A data processor according to any one of the preceding claims, comprising a supervisory processor, wherein the supervisory processor translates instructions relating to the emulated processor so that the translated instructions can be executed. A data processor for providing information to the processing unit on the emulation side. 7. The data processor according to claim 6, wherein the information supplied to the emulation-side processing unit has an object code native to the emulation-side processing unit. 8. A data processor according to claim 6 or claim 7, wherein the monitoring processor is configured to change which emulation-side processing unit is emulated by an emulation-side processing unit. A data processor, characterized in that it is operable to change the allocation to the processing unit. A data processing method for a system having a plurality of interconnected emulation-side processing units arranged to emulate the operation of a processor to be emulated having a plurality of interconnected emulation-side processing units. And
The method
Emulating an emulated processing unit with the contribution of two or more emulation processing units;
Emulating two or more emulation-side processing units with one emulation-side processing unit;
A data processing method characterized by comprising: Computer software for performing the method of claim 9. A medium for providing the computer software according to claim 10. The medium according to claim 11, wherein the medium is a storage medium. 12. A medium according to claim 11, wherein the medium is a transmission medium.

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