JP2011227756A - Terminal apparatus with high temperature detection counter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for detecting the optimal period for performing an action by a simple method when the temperature of the inside of an apparatus with a device whose characteristics deteriorate in a high temperature becomes high.SOLUTION: A terminal apparatus is provided with: a high temperature detection counter circuit which detects the temperature of the apparatus, and integrates stress acceleration time weighted according to the detected temperature as a stress count value, and outputs an interruption signal when the stress count value becomes equal to or more than a set value; and a CPU which controls the operation of the apparatus. When the total value of a cumulative stress acceleration time obtained by cumulatively counting the interruption signal from the high temperature detection counter circuit and a system time from a timer circuit exceeds a set stress management time, the CPU performs rewriting to a non-volatile memory.

Description

  The present invention relates to a terminal device, and in particular, includes a high-temperature detection counter circuit that detects a temperature inside the device and counts the time of a high-temperature state according to the temperature, and before the retention characteristics deteriorate due to high temperature, the device The present invention relates to a terminal device that rewrites data in a non-volatile memory provided in.

  For portable terminal devices and information terminal devices, devices whose characteristics deteriorate when the temperature inside the device becomes high, such as nonvolatile memories, are used. In portable terminal devices and information terminal devices, application programs necessary for device operation are stored in a nonvolatile memory. In recent years, with the enhancement of functions of devices, such application programs have become very large in scale, and it has become necessary to use a large-capacity nonvolatile memory. As a large-capacity nonvolatile memory, there are two types of NAND devices, SLC (Single Level Cell) -NAND and MLC (Multi Level Cell) -NAND. Of these two types of NAND devices, the MLC-NAND can record a plurality of bits in one memory cell, so that the capacity can be easily increased compared to the SLC-NAND. For this reason, the MLC-NAND is frequently used in devices that require miniaturization, such as portable terminal devices and information terminal devices.

  However, the MLC-NAND needs to finely control the threshold level (Vt) of the memory cell in order to record a plurality of bits in one memory cell, and is less reliable than the SLC-NAND. If the device is used for a long time in an environment where the device ambient temperature is high, the retention characteristics may deteriorate and the data of the write data may be corrupted. The retention characteristic is a data retention characteristic indicating whether written data is correctly retained. For example, when the retention characteristic deteriorates, electrons in the memory cell leak and the Vt of the memory cell fluctuates, so that the data changes to data different from that at the time of writing. Such garbled data is different from that at the time of writing. In particular, the influence is large when the temperature is high, and the retention characteristics are likely to deteriorate. If garbled data occurs due to the retention characteristic, there is a possibility that a malfunction may occur in the operation of the apparatus. Therefore, a means for preventing this is necessary.

  Furthermore, recent portable terminal devices and information terminal devices tend to have higher internal temperatures. As a first factor, it is necessary to improve the processing performance of the central processing unit (CPU) due to the necessity of improving the application performance and communication performance, and the temperature inside the device increases as the processing performance of the CPU increases. . A second factor is that a memory device is arranged in the vicinity of a CPU that generates a large amount of heat for high-density mounting by downsizing the portable terminal device. For example, with the POP (Package On Package) technology or the like, a case where a memory device is solder-mounted on top of a CPU device is increasing.

  As a third factor, it is necessary to increase the airtightness in the specifications of the device itself such as a waterproof function, and the temperature inside the device tends to increase. Further, as a fourth factor, since the number of electrons stored per non-volatile memory cell is reduced due to miniaturization of the memory device manufacturing process, the retention characteristic (data retention characteristic) of the device itself is also deteriorated. Tend. Non-Patent Document 1 describes that the retention characteristic (data retention characteristic) of a memory cell deteriorates due to the device temperature of the non-volatile memory being increased, and the risk of data corruption is higher than that used at room temperature. Yes.

  In this way, the device itself tends to become high temperature, and the device itself also tends to have low retention characteristics (data retention characteristics). For this reason, the risk of data corruption due to retention characteristics in recent mobile terminal devices and information terminal devices (hereinafter sometimes abbreviated as terminal devices) is increasing. For this reason, the terminal device needs a means for monitoring the device temperature history and notifying the system with a simple circuit with low power consumption.

  There are the following documents as prior patent documents for monitoring the apparatus temperature and preventing troubles. In Patent Document 1, the apparatus temperature is measured at every constant elapsed time, and the elapsed time weighted according to the measured temperature is counted. A technique is described in which when a weighted elapsed time exceeds a predetermined time, a write operation is performed again in the nonvolatile memory. Further, Patent Document 2 discloses a temperature detection device that periodically measures the ambient temperature, a count value that is +1 if the detected temperature is within the standard range, and an arithmetic device that adds +2 if the detected temperature is outside the standard range, and a count A technique for outputting an alarm when a value exceeds a set value is shown.

JP 2000-11670 A JP 2001-144243 A

Toshiba Corporation, Reliability Test Data (http://www.semicon.toshiba.co.jp/shared/reliability_pdf/bdj0128e_chap03.pdf) Numonyx NAND device data sheet (http://www.numonyx.com/Documents/Datasheets/NAND_08GW3C2B.pdf) Data sheet for National Semiconductor LMC555 (http://www.national.com/JPN/ds/LM/LMC555.pdf)

  As described above, in the terminal device, when the application is operated, the CPU, the memory, and the peripheral circuit generate heat, so that the temperature inside the device becomes high. When the temperature inside the device becomes high, in a non-reliable nonvolatile memory, write data is garbled due to deterioration of retention characteristics, which causes a decrease in system reliability. Data corruption can be prevented by rewriting data before data corruption occurs. In the above-described patent document, data corruption is prevented by rewriting data. However, in the above-described patent document, the ambient temperature is measured at regular intervals, and the measured temperature is set as the temperature at the time interval. However, recent terminal devices have many applications, and the device temperature varies greatly depending on which application is operating. Therefore, the technique described in Patent Literature that measures the device temperature at regular intervals is inaccurate and cannot be used for a terminal device. For this reason, there is a problem that means for detecting the timing for rewriting more accurately is required by a simple method that can be used for the terminal device.

  The present invention provides a means for detecting an optimum timing for performing treatment in a simple manner when the inside of the apparatus becomes high temperature in such an apparatus having a device whose characteristics deteriorate at a high temperature. It is in.

  According to one aspect of the present invention, the temperature inside the apparatus is detected, the stress acceleration time weighted according to the detected temperature is integrated as a stress count value, and the stress count value is equal to or greater than a set value. A high-temperature detection counter circuit that sometimes outputs an interrupt signal, and a CPU that controls the operation of the device, the CPU cumulatively accelerating the interrupt signal from the high-temperature detection counter circuit, and a timer circuit Thus, when the total value of the system time obtained from the time information exceeds the set stress management time, a terminal device is obtained in which rewriting is performed in the nonvolatile memory inside the device.

  According to another aspect of the present invention, a plurality of temperature sensors that detect the temperature inside the apparatus using different temperature thresholds, and a temperature sensor that detects the lowest temperature among the plurality of temperature sensors. An oscillation circuit that outputs a clock signal in response to a high temperature detection signal; a counter circuit that accumulates the number of times the clock signal is input as a stress count value that is weighted corresponding to each of the high temperature detection signals from the plurality of temperature sensors; The counter circuit outputs an interrupt signal and resets the stress count value when the stress count value exceeds a set maximum value. can get.

  According to still another aspect of the present invention, the CPU reads the system time read from the timer circuit into each register of the management table, the accumulated stress acceleration time that has been backed up, the system time, and the accumulated stress acceleration time. The initialization step of writing the total value and the set stress management time and writing the stress count value backed up to the register of the high temperature detection counter circuit, and the high temperature detection counter circuit detects the temperature inside the device. Then, the stress count value weighted according to the detected temperature is cumulatively counted in the register of the high temperature detection counter circuit, and when the cumulative count of the stress count value exceeds a certain value, the high temperature detection counter circuit Is output to the CPU, and the CPU accumulates the interrupt signal. Counting up as stress acceleration time, the high temperature detection counter circuit further resets the stress count value, and repeats the operation of accumulating and counting the stress count value weighted according to the detected temperature again in the register of the high temperature detection counter circuit And a writing step of rewriting the nonvolatile memory inside the device when the total value of the system time and the accumulated stress acceleration time exceeds the stress management time. A characteristic rewriting method for a nonvolatile memory can be obtained.

  The terminal device of the present invention includes a high temperature detection counter circuit and a CPU that controls the operation of the device. The high-temperature detection counter circuit detects the temperature inside the device, integrates the stress acceleration time weighted according to the detected temperature as a stress count value, and generates an interrupt signal when the stress count value exceeds the set value. Is output. The CPU is nonvolatile when the total value of the accumulated stress acceleration time obtained by accumulating the interrupt signal from the high temperature detection counter circuit and the system time obtained from the time information of the timer circuit exceeds the set stress management time. Rewrite to the memory.

  As described above, according to the present invention, the nonvolatile memory in which the application program and the like are stored can be rewritten within the stress management time in which data retention is guaranteed. Therefore, it is possible to prevent problems caused by the retention characteristics of the nonvolatile memory.

It is a system block diagram of the terminal device in this invention. It is a circuit block diagram of a high temperature detection counter circuit in the present invention. It is a truth table of the counter circuit in the present invention. It is a setting example of the stress acceleration time of the counter circuit in the present invention. It is an example of setting the MAX value of the stress count value in the present invention. It is a timing chart which shows operation | movement of the high temperature detection counter circuit in this invention. It is an example of the management table preserve | saved at the register | resistor of CPU in this invention. It is a flowchart which shows the operation example at the time of carrying the structure of this invention in a mobile telephone.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a system configuration diagram of a terminal device. 2 is a circuit block diagram of the high temperature detection counter circuit, FIG. 3 is a truth table of the counter circuit, FIG. 4 is a setting example of the stress acceleration time of the counter circuit, and FIG. 5 is a setting example of the MAX value of the stress count value in the present invention. , Respectively. FIG. 6 is a timing chart showing the operation of the high temperature detection counter circuit. FIG. 7 shows an example of a management table stored in the CPU register.

  FIG. 1 shows a system configuration of a terminal device such as a portable terminal device or an information terminal device. The terminal device includes a volatile memory (101), a peripheral circuit (102), a timer circuit (103), a CPU (104), a high temperature detection counter circuit (105), and a nonvolatile memory (106). The volatile memory (101) is a volatile memory (DRAM) for operating an application. The peripheral circuit (102) includes a wireless circuit, an LCD, a key input / output device, and the like. The timer circuit (103) indicates the time that has elapsed since the writing of the nonvolatile memory. The high temperature detection counter circuit (105) is composed of a sensor for detecting a high temperature, a counter circuit, and an oscillation circuit, and is the most characteristic circuit in the present invention. The nonvolatile memory (106) is a nonvolatile memory (MLC-NAND memory) in which program codes and data are stored.

  The CPU (104) controls the operation of the entire terminal device. For example, as a general operation of a mobile phone system, when starting the system, the CPU (104) reads out an application program stored in the nonvolatile memory (106) and develops it in the volatile memory (101). To do. Next, the CPU (104) is configured to execute the program using the application program developed in the volatile memory (101). As described above, the CPU (104) realizes various functions required for the apparatus by controlling various peripheral circuits (102) in accordance with the description of the program code and application program.

  The operation of a call performed on the mobile terminal device is realized as follows, for example. The user presses a dial key and a call button of the peripheral circuit (102) for a call operation. The CPU (104) detects the operation by a key input in the peripheral circuit (102), and develops an application program necessary for a call from the nonvolatile memory (106) to the volatile memory (101). Next, the CPU (104) uses the application program to control the wireless circuit of the peripheral circuit (102) and perform wireless communication with the base station. The nonvolatile memory (106) is a general NAND device, and for example, a Numonyx NAND device shown in the data sheet of Non-Patent Document 2 can be used.

  FIG. 2 is a circuit block diagram illustrating the circuit configuration of the high temperature detection counter circuit (105) of the present invention. The high temperature detection counter circuit (105) includes a counter circuit (203), an oscillation circuit (207), a temperature sensor 2 (208), and a temperature sensor 1 (209). Temperature sensor 1 (209) and temperature sensor 2 (208) are set such that the detected temperature threshold values are different from each other. The temperature sensor 1 (209) outputs “H” as a high temperature detection signal when it detects the first high temperature or higher which is the temperature threshold value. When the temperature sensor 2 (208) detects a second high temperature or higher, which is a temperature higher than the temperature sensor 1, as a temperature threshold value, it outputs “H” as a high temperature detection signal.

  The oscillation circuit (207) outputs a 1 Hz clock signal (206) only when the temperature sensor 1 (209) detects a high temperature and outputs "H" as a high temperature detection signal. The counter circuit (203) counts the stress value (also referred to as stress acceleration time) weighted by the outputs (204 and 205) of each temperature sensor in synchronization with the rising edge of the clock signal (206) of the oscillation circuit. Accumulate in register as count value. When the stress count value reaches the set MAX value, an interrupt signal (201) is output to the CPU. When the reset signal (202) is received from the CPU, the stress count value accumulated in the internal register is reset to “0”.

  FIG. 3 is a truth table (220) of the counter circuit (203). As an input of the counter circuit (203), a reset signal (202) output from the CPU, an output (205) of the temperature sensor 1 from two temperature sensors, an output (204) of the temperature sensor 2, and an output of the oscillation circuit There is a clock (206). The output of the counter circuit (203) is an interrupt signal (201) output to the CPU.

  The operation of the counter circuit (203) will be described with reference to the truth table (220). When the reset signal (202) from the CPU is “L”, the counter circuit resets the internal register value (stress count value) Q to “0” regardless of other input signals (condition 1). Condition 2 and after are when the reset signal (202) from the CPU is "H". When the output (205) of the temperature sensor 1 is “L”, the internal register value Q is held as it is even when the “H” rising edge of the clock signal (206) comes (condition 2). In condition 2, since the apparatus temperature is close to room temperature and is equal to or lower than the first detection temperature, the counter circuit does not count up and maintains the current value.

  When the output (205) of the temperature sensor 1 is “H” and the output (204) of the temperature sensor 2 is “L”, the value of the internal register value Q is changed to the temperature at the “H” rising edge of the clock signal (206). Counts up only for the stress acceleration time td1 when sensor 1 is detected (td1 will be described later) (condition 3). When the output (205) of the temperature sensor 1 is “H” and the output (204) of the temperature sensor 2 is “H”, the value of the internal register value Q is changed to the temperature at the “H” rising edge of the clock signal (206). Counts up only for the stress acceleration time td2 at the time of sensor 2 detection (td2 will be described later) (condition 4). Under these conditions 3 and 4, the apparatus temperature is high, and the counter circuit counts up the stress count value, which is an internal register value, according to the stress acceleration time by weighting each set temperature.

  Thus, in a state where the temperature sensors 1 and 2 detect a high temperature, the internal register value (stress count value) of the counter circuit is counted up for each clock signal. When the internal register value Q of the counter circuit is counted up to the upper limit (MAX) or more, the interrupt signal (201) “H” is output to the CPU at the rising edge of the clock signal (206) (condition 5). . The counter circuit outputs an interrupt signal (201), and further resets the next internal register value (stress count value) to “0”.

  FIG. 4 shows a setting example (230) of the stress acceleration time. In this example, the stress acceleration time (td1, td2) at the time of detection of each temperature sensor is determined from information on how many times the device is subjected to stress at the detected temperature of each sensor as in the remarks column (236). The set value (231) is shown. In order to make the explanation easy to understand, an example of the data retention characteristic is taken and described with specific numerical values.

  As a precondition, the temperature sensor 1 (209) outputs “H” when a high temperature of 70 ° C. or higher is detected, and the temperature sensor 2 (208) outputs “H” when a high temperature of 80 ° C. or higher is detected 2 Assume that two temperature sensors are used. In addition, according to prior experiments, when the retention characteristics of nonvolatile memory at high temperatures are 70 ° C. or higher and lower than 80 ° C., stress is 3 times higher than normal temperature, and at 80 ° C. or higher, it is 10 times higher than normal temperature. It shall be known. When the temperature is 70 ° C. or higher and lower than 80 ° C., the temperature sensor 1 (209) is in the high temperature detection state and the temperature sensor 2 (208) is in the high temperature non-detection state. As described above, when the temperature is 70 ° C. or more and less than 80 ° C., the stress received in one second is equivalent to 3 seconds at room temperature, and is stressed by 2 seconds more than the stress received in room temperature for 1 second. . In this case, the stress acceleration time td1 is 2 (234).

  When the temperature is 80 ° C. or higher and the temperature sensor 2 (208) detects a high temperature, the stress that the non-volatile memory device receives in 1 second is equivalent to 10 seconds at room temperature. I was stressed a lot by the second. In this case, the stress acceleration time td2 is 9 (235). The stress acceleration time is defined as a value indicating how many seconds the stress received at a high temperature for 1 second corresponds to acceleration at room temperature. For example, in the present invention, the stress acceleration time td1 is 2 when the temperature of the apparatus is 70 ° C. or more and less than 80 ° C., and the stress acceleration time td2 is 9 when the temperature of the device is 80 ° C. or more. As described above, the stress acceleration time when the temperature is 80 ° C. or higher is longer than the stress acceleration time when the temperature is 70 ° C. or higher and lower than 80 ° C.

  The setting of the temperature threshold value of these temperature sensors is not particularly limited, and can be freely set to a temperature that may cause a problem in the terminal device. In FIG. 2, the temperature sensor 1 and the temperature sensor 2 are two temperature sensors. However, the number of temperature sensors is not limited to two, and the number of temperature sensors may be three or more. In this case, the temperature range and the stress acceleration time may be set respectively. Even when the number of temperature sensors is increased, by operating the oscillation circuit with the output of the temperature sensor set to the lowest temperature (first temperature), the stress acceleration time td3 at the third high temperature is set. The configuration can be the same as that described above. Further, when the number of temperature sensors is increased, the stress acceleration time depending on the temperature can be set more finely, so that the accuracy of the stress amount can be increased.

  FIG. 5 shows a setting example (240) of the MAX value of the stress count value of the counter circuit. In this example, as described in the remarks (243), the MAX value (241) for outputting an interrupt signal (201) to the CPU every time the device is subjected to stress acceleration equivalent to 3600 seconds (1 hour) at room temperature due to high temperature. It is an example of setting. Since the oscillation frequency of the oscillation circuit (207) is 1 Hz, when the stress count value is 3600 (242), it can be detected that stress acceleration corresponding to one hour has been received at room temperature. When the internal register (stress count) value of the counter circuit becomes 3600 or more, the counter circuit outputs an interrupt signal (201) to the CPU, and further resets the internal register (stress count) value to “0”.

  FIG. 6 is an operation timing chart of the high temperature detection counter circuit of the present invention. The timing chart includes a reset signal (201), an output (209) of the temperature sensor 1, an output (208) of the temperature sensor 2, a clock signal (206) from the oscillation circuit, an internal register (stress count) value of the counter circuit, An interrupt signal (201) to the CPU is shown.

  Initially, the system is activated by the operator. At time t0, the CPU (104) outputs a reset signal (201) to the counter circuit (203). In response to this, the counter circuit resets the internal register value to “0” (340). When the application operates and the temperature inside the apparatus reaches 70 ° C. or more at time t1, the temperature sensor 1 (209) determines that the set temperature (temperature threshold value) has been exceeded, and the temperature detection signal output becomes “H”. (311). Upon receiving the “H” output of the temperature sensor 1 (209), the oscillation circuit (207) starts oscillation and outputs a 1 Hz clock (331). The counter circuit (203) detects the rising edge (331) of the output signal of the oscillation circuit, and when the temperature sensor 1 output (205) is “H” and the temperature sensor 2 output (204) is L, only td1 is obtained. Count up (341). In this way, the internal register (stress count) value Q is increased by td1 from time t1 to time t2 in response to the rising edge of the oscillation circuit output. In the figure, td1 = 2 is increased at each rising edge of the 1 Hz clock.

  Next, when the temperature inside the apparatus becomes 80 ° C. or higher (time t2), the temperature sensor 2 (208) determines that the set temperature has been exceeded, and the output becomes “H” (321). The counter circuit (203) counts up by td2 when the temperature sensor 1 output (205) is "H" and the temperature sensor 2 output (204) is "H" at the rising edge (332) of the clock signal. (342). In this way, the internal register (stress count) value Q is increased by td2 = 9 from time t2 to time t3 in response to the rising edge of the oscillation circuit output. Next, when the temperature inside the apparatus becomes lower than 80 ° C. (time t3), the temperature sensor 2 (208) determines that the temperature has become lower than the set temperature, and the output becomes “L” (322). The counter circuit (203) sets the temperature sensor 1 output (205) to "H" and the temperature sensor 2 output (204) to "L" at the rising edge (333) of the clock signal, so that td1 is set to the internal register value. Add to Q (343). In this way, the internal register value Q is increased by td1 from time t3 to time t4 in response to the rising edge of the oscillation circuit output.

  Next, when the operation of the application ends, for example, when the temperature inside the apparatus falls below 70 ° C. (time t4), the temperature sensor 1 (209) determines that the temperature falls below the set temperature, and the output becomes “L”. (312). In response to this, the oscillation circuit stops the clock signal, and the internal register (stress count) value Q holds that value.

  Next, immediately before time t5, the operation from time t1 to t4 is repeated, and the internal register value Q of the counter circuit (203) is in the state immediately before the Max value (max = 3600) of the counter circuit. To do. When the operation of the application is started again and the temperature inside the apparatus reaches 70 ° C. or more (time t5), the temperature sensor 1 (209) determines that the set temperature has been exceeded and the output becomes “H” (313). . In response to the “H” output of the temperature sensor 1 (209), the oscillation circuit (207) starts oscillation again. Since the counter circuit (203) detects the rising edge (334) of the output signal of the oscillation circuit, the temperature sensor 1 output (205) is “H” and the temperature sensor 2 output (204) is “L”. , Td1 is added to the internal register value Q. At this time, since the internal register value Q is equal to or greater than Max (MAX = 3600), a one-shot pulse of an interrupt signal to the CPU is output (351). Further, an operation of resetting the internal register value Q to 0 is performed (344).

  FIG. 7 shows a management table (400) stored in a register inside the CPU (104). There are the following four registers in the management table (400). The system time tt1 (401) is an elapsed time of the system obtained by the CPU reading from the timer circuit (103). The accumulated stress acceleration time tt2 (402) is an accumulated time corresponding to room temperature that is accelerated due to the high temperature of the apparatus by accumulating the number of occurrences of the interrupt signal (201) from the high temperature detection counter circuit (105). The current stress time tt3 (403) is the sum of the system time tt1 (401) and the accumulated stress acceleration time tt2 (402). The stress management time tt4 (404) is a stress time corresponding to room temperature to be managed.

  During operation of the apparatus, the CPU (104) receives the interrupt signal (201) from the high temperature detection counter circuit (105). Upon receipt of the interrupt signal (201), the system time tt1 (401) and the current stress time tt3 (403) are continuously updated while the cumulative stress acceleration time (402), which is a register in the CPU (104), is incremented by one. . Further, the CPU (104) compares the current stress time tt3 (403) and the stress management time tt4 (404) at regular intervals, and the current stress time tt3 (403) exceeds the stress management time tt4 (404). For example, it is determined that the retention characteristic of the nonvolatile memory has exceeded the management time, and the CPU (104) rewrites the nonvolatile memory (106).

  In this way, when actually managing the retention characteristics of the nonvolatile memory, calculate the stress time from the time when the nonvolatile memory was written, including the normal temperature state where the device is not operating, and set the rewriting time. It is necessary to judge. For managing the retention characteristics of the nonvolatile memory, the system time (tt1) is used together with the cumulative stress acceleration time (tt2). The system time is time information indicated by the timer circuit, and includes time when the apparatus is not operating. For example, the system time is the time that has elapsed since the device was manufactured, or the time that has elapsed since the writing of an application program or other nonvolatile memory. The sum of the accumulated stress acceleration time (tt2) and the system time (tt1) (current stress time tt3) can be defined as a stress time corresponding to room temperature. Therefore, if the stress time corresponding to room temperature exceeds the stress management time (tt4) determined in advance, the CPU rewrites the nonvolatile memory.

  The value in the management table of the CPU (104) here is a time unit. That is, the internal register value of the high temperature detection counter circuit (105) is accurately counted in seconds according to the temperature change, and the interrupt signal (201) to the CPU is output in 3600 seconds (1 hour). The CPU (104) counts the number of occurrences of the interrupt signal (201) and accumulates the number of times to convert from the second unit to the time unit. The internal register value of the high temperature detection counter circuit (105) is in seconds, and the stress acceleration time is counted more accurately according to the temperature change. However, the time until the rewriting of the nonvolatile memory is several thousand hours to several years to 10 years, and the number of digits becomes too large when counting in seconds. Therefore, the value of the management table of the CPU (104) is set to the time unit, thereby simplifying complicated processing of the number of digits. In this way, by converting the unit in the CPU from second to time from the high temperature detection counter circuit, the circuit scale of each register can be set to an appropriate scale.

  In the portable terminal device and the information terminal device of the present invention, a plurality of temperature sensors are arranged in the vicinity of a device whose characteristics deteriorate when the temperature becomes high, and the internal temperature of the device in operation is monitored. The plurality of temperature sensors are set as temperature thresholds so as to detect the first temperature and a different temperature higher than the first temperature. The oscillation circuit serving as the clock of the counter circuit is operated only while the temperature sensor that detects the lowest first temperature among the plurality of temperature sensors detects the high temperature. In order to obtain a history of the time during which the inside of the apparatus is at a high temperature, the stress count value weighted for each of the plurality of temperature sensors is counted by the counter circuit in synchronization with the clock from the oscillation circuit. Thus, if the circuit configuration is such that the oscillation circuit is operated only while the temperature sensor that detects the first temperature is detecting a high temperature, there is no operation of the oscillation circuit except when the high temperature is detected. Can be small.

  Further, the weighting for each of the plurality of temperature sensors can be determined in advance by desktop design or prior evaluation of the memory device. If it is a desktop design, the retention characteristic of the nonvolatile memory may be considered that the risk of bit corruption increases as the temperature increases, as shown in Non-Patent Document 1, and is an index known by the Arrhenius equation. Functional weighting is recommended. In addition, if it is determined in advance evaluation of the device, with regard to the retention characteristics of the nonvolatile memory, data on how many times bit bit breakage is likely to occur at the temperature of the temperature sensor compared to normal temperature is obtained through experiments, It is only necessary to determine the stress acceleration time to be weighted.

  In this way, while the terminal device is operating, the temperature inside the device is monitored, and the stress value weighted for each of the plurality of temperature sensors is continuously counted. From this stress count value, it is possible to know how many seconds at room temperature the amount of stress received by the device has been accelerated because the temperature inside the apparatus has become high. Then, an upper limit value (MAX) to be counted by the counter circuit is determined and notified to the CPU as an interrupt signal when the counter reaches the upper limit value (MAX). By notifying the interrupt signal, the CPU on the system side can detect that the amount of stress received by the device has reached a certain value because the temperature inside the apparatus has become high. If the CPU counts the number of notified interrupt signals and manages it on the register of the CPU, the amount of stress (accumulated stress acceleration time) received by the device can be grasped when the inside of the apparatus becomes high temperature. .

  To manage the retention characteristics of the nonvolatile memory, “accumulated stress acceleration time” and “system time” are used. The sum of “accumulated stress acceleration time” and “system time” becomes “current stress time”. If the “current stress time” exceeds the stress management time set in advance, the CPU rewrites the nonvolatile memory. The CPU can rewrite the memory to obtain a system with improved reliability.

(Example)
Next, as an embodiment, a case where the present invention is mounted on a mobile phone will be described with reference to FIG. FIG. 8 shows an example of an operation flowchart when the configuration of the present invention is mounted on a mobile phone.

  First, in step 501, the operator starts the system. Next, as step 502, the CPU (104) writes it in the register as initialization of the management table. The CPU (104) reads the current system time from the timer circuit (103) and writes it in the system time tt1 (401) on the register inside the CPU (104). The CPU (104) writes the value of the accumulated stress acceleration time backed up in the nonvolatile memory (106) when the system was turned off as the accumulated stress acceleration time tt2 (402) on the register in the CPU (104). In the case of the first system start-up, 0 is written as an initial value because the backed-up accumulated stress acceleration time is 0. The CPU (104) reads the system time tt1 (401) and the cumulative stress acceleration time tt2 (402), obtains the total value thereof, and writes the result as the current stress time tt3 (403). The CPU (104) writes the stress management time stored in advance in the nonvolatile memory (106) as the stress management time tt4 (404).

  The CPU (104) initializes the register of the counter circuit. The stress count value backed up in the nonvolatile memory (106) at the previous system OFF is written to the register of the counter circuit (203) of the high temperature detection counter circuit (105). The stress count value of the counter circuit can be backed up to the nonvolatile memory using the same path as the interrupt signal when the system is OFF, and can be written using the path where the reset signal is notified at initialization. In the case of the first system start-up, 0 is written as an initial value because the backed-up stress count value is 0.

  Next, the CPU (104) starts the operation of the high temperature detection counter circuit (step 503). As the operation of the high temperature detection counter circuit (105), the same operation as the timing chart of FIG. 6 described above is performed. During the high temperature detection operation, the high temperature detection counter circuit (105) monitors the temperature history of the apparatus, counts up a preset stress acceleration time according to the high temperature of the apparatus, and integrates it as a stress count value. Every time the stress count value obtained by integrating the stress acceleration time weighted by temperature is counted up to the maximum stress count value MAX (241), an operation of continuously outputting an interrupt signal to the CPU (104) is performed.

  Next, the CPU (104) checks whether there is an interrupt signal from the high temperature detection counter circuit (step 504). If there is no interrupt signal, the process proceeds to the next step (step 506). When there is an interrupt signal, the cumulative stress acceleration time tt2 (402) on the register in the CPU (104) is incremented by +1 (step 505), and then the process proceeds to the next step (step 506).

  Next, the CPU (104) updates the system time tt1 (401), the accumulated stress acceleration time tt2 (402), and the current stress time tt3 (403) in the management table (step 506). The CPU (104) reads the current system time from the timer circuit (103) and writes it in the system time tt1 (401) on the register inside the CPU (104). The CPU (104) reads the system time tt1 (401) and the cumulative stress acceleration time tt2 (402), obtains the total value, and writes the result as the current stress time tt3 (403).

  Next, the CPU (104) compares the current stress time tt3 (403) with the stress management time tt4 (404) (step 507). If the current stress time tt3 (403) does not exceed the stress management time tt4 (404), the process returns to step 504. If the current stress time tt3 (403) exceeds the stress management time tt4 (404), it is determined that the retention characteristic of the nonvolatile memory has exceeded the management time, and the CPU (104) Rewriting is performed (step 508). After rewriting to the nonvolatile memory (106), the CPU (104) resets the timer circuit (103) (reset the time to 0) and resets the accumulated stress acceleration time tt2 (402). Further, the CPU (104) outputs a reset signal to the high temperature detection counter circuit (105) to reset the counter circuit (203) (step 509). Next, returning to step 504, the high temperature detection operation by the high temperature detection counter circuit is performed again.

  As described above, the CPU (104) always checks whether the retention characteristic of the nonvolatile memory (106) has exceeded the management time during the operation of the apparatus, and determines the optimum timing for rewriting the nonvolatile memory (106). To detect. When the management time is exceeded, the CPU (104) rewrites the nonvolatile memory (106). After rewriting the nonvolatile memory, the “accumulated stress acceleration time” recorded in the CPU register and the “system time” of the timer circuit are reset. By resetting the register in this way, it becomes possible to determine again the next rewriting time of the nonvolatile memory. When the system power is turned off, the CPU (104) backs up the accumulated stress acceleration time tt2 and the stress count value in the nonvolatile memory (106). This makes it possible to count again from the backup time at the next system startup. Thus, the reliability of the system can be improved by checking the optimum timing for rewriting the nonvolatile memory continuously and causing the CPU to rewrite the nonvolatile memory.

  The terminal device of the present invention arranges a plurality of temperature sensors in the vicinity of a device whose characteristics deteriorate when the temperature becomes high, and monitors the temperature inside the device during operation. Of the plurality of temperature sensors, the oscillation circuit serving as the clock of the counter circuit is operated only while the temperature sensor that detects the first temperature, which is the lowest temperature, detects the high temperature. In order to obtain a history of the time during which the inside of the apparatus is at a high temperature, the counter circuit counts the stress count value weighted for each of the plurality of temperature sensors in synchronization with the clock from the oscillation circuit. Then, an upper limit value (MAX) of the stress count value counted by the counter circuit is determined and notified to the CPU as an interrupt signal when the counter reaches the upper limit value (MAX). The CPU counts the number of interruptions and stores it as the accumulated stress acceleration time on the CPU register.

  The accumulated stress acceleration time and the system time are used for managing the retention characteristics of the nonvolatile memory. The sum of the accumulated stress acceleration time and the system time becomes the current stress time. If the current stress time exceeds a preset stress management time, the CPU rewrites the nonvolatile memory. As described above, in the present invention, by monitoring the stress time, the data reliability due to the deterioration of the data retention characteristics of the nonvolatile memory is rewritten before the data corruption occurs, thereby improving the reliability of the system. Can be increased.

  In the circuit configuration of the present invention, the following effects can be obtained. The first effect is that the stress of the device whose characteristics deteriorate when the temperature becomes high can be realized with a simple circuit and a small current consumption. In the circuit configuration of the present invention, the oscillation circuit that generates the clock of the counter circuit is driven only when the temperature sensor that detects the lowest temperature inside the apparatus detects. Therefore, when the temperature is not high (when the temperature is close to normal temperature and equal to or lower than the first detection temperature), the oscillation circuit is not driven, so that current consumption can be minimized.

  For example, assume that this oscillation circuit is realized by a general timer IC. In a data sheet of a general timer IC (for example, LMC555 manufactured by National semiconductor, Non-Patent Document 3), the current consumption during the oscillation operation is 250 uA and is 1 uA or less during the stop. Since oscillation does not occur when the temperature is equal to or lower than the first detection temperature, it is advantageous in terms of current consumption. In particular, during the standby operation of a mobile phone, the operation of the CPU is mainly performed to check whether there is an incoming call, so the load is relatively small and the possibility that the inside of the apparatus will be hot is small. Thus, a means for minimizing the power consumption during the standby operation in which the apparatus temperature does not become high is very important.

  When the present invention is applied to a general mobile phone and the oscillation circuit is operated only at a high temperature, the following effects can be obtained by taking the standby time (battery holding time) as an example. The capacity of the rechargeable battery (battery pack) of the mobile phone is 500 mAh, and the normal current consumption other than the high-temperature counter circuit of the mobile phone is 1 mA. As a conventional example, even when waiting for a mobile phone, regardless of the internal temperature of the device, the condition (1) for operating the oscillation circuit is stopped. The consumption current in the condition (2) to be compared is compared.

  In the case of condition (1), the sum of the current consumption 250 uA of the high-temperature counter circuit and the other current consumption 1 mA is 1.25 mA. On the other hand, in the condition (2), the sum of the current consumption 1 uA of the high-temperature counter circuit and the other current consumption 1 mA is 1.001 mA. As a result, the standby time is 400 hours (≈500 ÷ 1.25) for condition (1) (conventional example) and 500 hours (≈500 ÷ 1.001) for condition (2) (present invention). , 100 hours standby time has been improved. The standby time is an important item of the merchantability of the mobile phone, and by using the high-temperature detection counter circuit of the present invention, it is possible to realize a desired detection means without shortening the standby time (battery holding time). it can.

  A second effect obtained by using the circuit configuration of the present invention is to prevent data corruption caused by the retention characteristics of the memory device. For example, many write data in a general nonvolatile memory are guaranteed to retain data for several years to 10 years at room temperature. However, there are cases where the mobile phone is used in a high temperature state. In this case, the retention characteristics are deteriorated, and there is a possibility that data corruption occurs. However, by using the present invention, an application program or the like necessary for the operation of the apparatus can be rewritten within the guarantee of data retention. Such rewriting is automatically performed inside the apparatus, and it is possible to prevent problems caused by the retention characteristics of the nonvolatile memory without being noticed by the user.

  Furthermore, by using the circuit configuration of the present invention, it is possible to prevent data corruption that occurs due to the retention characteristics of the memory device due to the high temperature of the device. Therefore, the following effects can be obtained in the design of the mobile phone. In recent mobile phones, there is a case where a device is mounted on the upper part of the CPU by POP (Package On Package). In this case, heat is generated during the operation of the CPU, which has a considerable influence on the retention characteristics of the memory device. When the operating frequency of the CPU is lowered for the purpose of suppressing the generation of heat in order to secure the retention characteristics of the memory device, there is a demerit that the operability of the mobile phone is lowered and the merchantability is impaired.

Also, in order to ensure the retention characteristics of the memory device, if the CPU and the memory device are not stacked without using a POP for the purpose of separating the distance from the heat source, there is an effect on the increase in the board area and the design of the mobile phone. The demerit that the performance is impaired occurs. For example, in the case where the device area of the nonvolatile memory chip is 100 mm ² , and the POP of the CPU and the memory device can be designed on a 30 mm × 30 mm printed board, the printed board is 900 mm ² . On the other hand, in order to secure the retention characteristics of the memory device, when the memory device is arranged at a different location on the printed board in order to keep the distance from the heat source, the area of the memory device is required at a location different from the CPU. , 1000 mm ² is required. The present invention prevents memory corruption occurring in the retention characteristic due to the memory device, when enabled the design of the POP, so that could reduce the ^{11% (= 1000mm 2 / 900mm} 2) printed circuit board. In a mobile phone, if the outer dimensions of the printed board can be reduced, the degree of freedom in design can be improved and the product quality as a product can be improved.

  In the present invention, data corruption caused by the retention characteristic of the memory device due to the high temperature of the apparatus can be prevented, so that it is free from many design restrictions as described above, and free design can be performed. Thus, while ensuring design freedom, it is possible to prevent design disadvantages of the mobile phone, further reduce the external dimensions, increase the degree of design freedom, and increase the commercial value of the product.

  As mentioned above, although this invention was demonstrated in detail as preferable embodiment and an Example, this invention is not limited to these embodiment and an Example, In the range which does not deviate from the summary of this invention, it changes suitably. Is possible.

101 volatile memory 102 peripheral circuit 103 timer circuit 104 central processing unit (CPU)
105 High temperature detection counter circuit 106 Non-volatile memory 201 Interrupt signal 202 Reset signal 203 Counter circuit 204 Output 205 of temperature sensor 2 Output 206 of temperature sensor 1 Clock 207 Oscillation circuit 208 Temperature sensor 2
209 Temperature sensor 1

Claims (8)

  A high temperature detection counter that detects the temperature inside the apparatus, integrates the stress acceleration time weighted according to the detected temperature as a stress count value, and outputs an interrupt signal when the stress count value exceeds a set value And a CPU for controlling the operation of the apparatus, wherein the CPU is configured to accumulatively count an interrupt signal from the high temperature detection counter circuit, and a system time obtained from time information of the timer circuit. A terminal device, wherein when the total value exceeds a set stress management time, rewriting is performed in a nonvolatile memory inside the device.   The high temperature detection counter circuit includes a temperature sensor that detects a high temperature inside the apparatus, an oscillation circuit that outputs a clock signal in response to a high temperature detection signal from the temperature sensor, and a counter circuit that counts the number of times the clock signal is input. The terminal device according to claim 1.   The high temperature detection counter circuit includes a plurality of temperature sensors with different temperature thresholds to be detected, and the oscillation is detected when the temperature sensor that detects the lowest temperature among the plurality of temperature sensors detects a high temperature. The terminal device according to claim 2, wherein the circuit is driven and a clock signal is output.   4. The counter circuit according to claim 2, wherein the counter circuit integrates the number of times the clock signal is input as a weighted stress count value corresponding to each of the high temperature detection signals from the plurality of temperature sensors. Terminal equipment.   5. The counter circuit according to claim 2, wherein the counter circuit generates an interrupt signal and resets the stress count value when the accumulated stress count value exceeds a set maximum value. A terminal device according to any one of the above.   The CPU includes a management table register for storing the cumulative stress acceleration time, the system time, a total value of the cumulative stress acceleration time and the system time, and the stress management time, respectively. The terminal device according to any one of claims 1 to 5. A plurality of temperature sensors that detect the temperature inside the device using different temperature thresholds;
An oscillation circuit that outputs a clock signal by a high temperature detection signal from a temperature sensor that detects the lowest temperature among the plurality of temperature sensors;
A counter circuit for integrating the number of times the clock signal is input as a stress count value weighted in correspondence with each of the high temperature detection signals from the plurality of temperature sensors;
The counter circuit outputs an interrupt signal and resets the stress count value when the stress count value exceeds a set maximum value, and the high temperature detection counter circuit is characterized in that . The CPU reads the system time read from the timer circuit into each register of the management table, the accumulated stress acceleration time that was backed up, the total value of the system time and the accumulated stress acceleration time, and the set stress management time And an initialization step of writing a stress count value backed up to a register of the high temperature detection counter circuit,
The high temperature detection counter circuit detects the temperature inside the apparatus, and cumulatively counts the stress count value weighted according to the detected temperature in the register of the high temperature detection counter circuit, and the accumulated count value of the stress reaches a certain value or more. The high temperature detection counter circuit outputs an interrupt signal to the CPU, the CPU counts up the interrupt signal as a cumulative stress acceleration time, and the high temperature detection counter circuit further resets the stress count value and detects again. Repeatedly performing an operation of accumulating the stress count value weighted according to the measured temperature in the register of the high temperature detection counter circuit;
The CPU includes a writing step of performing rewriting to a nonvolatile memory inside the apparatus when a total value of the system time and the accumulated stress acceleration time exceeds the stress management time. How to rewrite to memory.

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