JP2011223391A - Semiconductor integrated circuit and imaging system equipped with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine whether or not a data signal is a video signal based on the data signal itself outputted from an image sensor, with no provision of an additional signal line between the image sensor and DSP.SOLUTION: The imaging system includes an image sensor (1) that contains a pixel array (101), a code generation part (102), and a transmission interface (103), and a semiconductor integrated circuit (2) which processes an output signal outputted from the image sensor (1). The semiconductor integrated circuit (2) includes a reception interface (201) which receives an output signal outputted from the image sensor (1), a signal delay part (202) which delays the received output signal for outputting a first signal, an error correction part (206) which corrects error of a code sequence of the first signal, and an image signal determination part (211) which determined whether or not an external signal is an image signal based on the processing result of the error correction part(206).

Description

  The present invention relates to an imaging system including an image sensor and a receiving circuit, and particularly belongs to a technique effective when applied to an imaging system of a camera such as a digital still camera.

  In recent years, digital still cameras have become widespread, and competition among companies regarding performance such as image quality has intensified. In particular, the number of pixels of the image sensor is an important factor that determines the image quality. Due to the improvement in the number of pixels, it is required to increase the speed of the interface between the image sensor and the system LSI that controls image processing.

  If the speed between the image sensor and the DSP is increased by using a digital interface, it is necessary to adjust the data fetch timing on the DSP side. In view of this, there is a technique in which data can be captured at a correct timing on the DSP side by adjusting the phase of a capture clock signal when a test pulse is input from the image sensor to the DSP and received. Further, by performing this test pulse generation in the horizontal or vertical blanking period, it is possible to perform periodic adjustment and cope with delay time fluctuation during use (see, for example, Patent Document 1).

JP 2007-194963 A

  The test pulse is for adjusting the phase of data acquisition in the DSP, and does not indicate at what timing the video signal is transmitted from the image sensor. That is, the DSP needs to know at what timing the video signal is sent from the image sensor, but it is difficult to know such timing from the test pulse. In the above prior art, since a test pulse is sent separately from the video signal from the image sensor, a dedicated pin for receiving the test pulse is required for the DPS.

  In view of such a problem, the present invention makes it possible to determine whether or not the data signal output from the image sensor on the DSP side is a video signal without adding a signal line between the image sensor and the DSP. Is an issue.

  In order to solve the above problems, the present invention has taken the following measures. That is, a pixel array including a collection of light receiving elements, a code generation unit that generates a code sequence including an error correction code, and a transmission interface that transmits a signal output from the pixel array and a code sequence generated by the code generation unit to the outside An image sensor, and a semiconductor integrated circuit that processes an external signal output from the image sensor. The semiconductor integrated circuit includes a reception interface that receives an external signal output from the image sensor, and A signal delay unit that delays the received external signal and outputs the first signal, an error correction unit that performs error correction of the code sequence of the first signal, and an external signal based on the processing result of the error correction unit It is assumed that an image signal determination unit that determines whether the signal is an image signal is provided.

  According to this, a data signal including an error correction code is repeatedly transmitted from the image sensor to the semiconductor integrated circuit during part or all of the horizontal and / or vertical blanking period, and the semiconductor integrated circuit is based on the error correction processing result. It is then determined whether the data signal is an image signal.

  According to the present invention, it is possible to determine whether or not it is a video signal from the data signal itself output from the image sensor without providing an additional signal line between the image sensor and the DSP.

FIG. 1 is a configuration diagram of an imaging system according to the first embodiment. FIG. 2 is a schematic diagram of a data transmission cycle of the image sensor. FIG. 3 is a timing chart of the data signal and clock signal of each delay amount after the phase adjustment is completed. FIG. 4 is a timing chart of the data signal and clock signal of each delay amount before the phase adjustment is completed. FIG. 5 is a flowchart of signal delay amount increase / decrease in the signal delay unit. FIG. 6 is a flowchart for making a phase adjustment possible from a state where the phase is completely out of phase. FIG. 7 is a configuration diagram of an imaging system according to the second embodiment. FIG. 8 is a timing chart of data signals and clock signals output from the image sensor.

(First embodiment)
FIG. 1 shows a configuration of an imaging system according to the first embodiment. The video system according to the present embodiment includes an image sensor 1 and a system LSI 2 that are connected to each other via a data signal line 104 and a clock signal line 105. In the image sensor 1, the pixel array 101 and the code generation unit 102 with an error correction code addition function are connected to the transmission interface 103. The transmission interface 103 does not always output pixel data, but is generated from the code generation unit 102 during a part or all of the invalid period for generating an image, which is generally called a blanking period. Send a signal. It is possible to control how many of the invalid periods are used for transmission of the error correction signal, and it is also possible to set the power saving mode during a period in which neither the error correction signal nor the pixel data is output. .

  In the system LSI 2, the reception interface 201 receives an external signal output from the image sensor 1. The signal delay unit 202 can generate three types of delays: a relatively large delay, a relatively small delay, and an intermediate delay between the signals received by the reception interface 201. Each time-delayed data signal is connected to a standard delay FF 203, a small delay FF 204, and a large delay FF 205, respectively. However, FF is an abbreviation for flip-flop. Since these FFs are connected to the same clock signal, the latch operation is performed at timings before, in the middle, and after the data signal.

  The signals latched in the small delay FF 204 and the large delay FF 205 are then held by the shift registers 207 and 208. The number of bits of the shift registers 207 and 208 is adjusted to the number of bits per pixel in the pixel array 101. For example, in the case of 8 bits per pixel, the shift registers 207 and 208 are also configured as 8-bit shift registers. The signal latched in the standard delay FF 203 is subjected to video processing such as pre-processing and YC processing through the image processing unit 210, and is recorded on an SD memory card (not shown) or the like and input to the error correction unit 206. .

  The error correction unit 206 always looks at the reception result of the standard delay FF 203 and performs error correction processing on the code sequence of the signal latched in the standard delay FF 203. Each code sequence includes a data part and an error correction code part, and is continuously transmitted from the image sensor 1 in the following code output area. The error correction unit 206 notifies the delay adjustment unit 209 of information regarding whether or not there is an error in the code sequence and the position information of the error in the code sequence. The delay adjustment unit 209 receives the notification from the error correction unit 206, determines whether or not the delay control is necessary by means described later, and if an error has occurred and the delay control is necessary, the signal delay The delay time is increased or decreased for the unit 202.

  Next, the signal output format of the image sensor 1 will be described. FIG. 2 is a schematic two-dimensional representation of the signal of the image sensor 1 that is output horizontally for each row. The data transmission cycle of the image sensor 1 is roughly classified into two, a pixel output period and a vertical blanking period. A period during which valid video information is actually transmitted is a pixel output period, and video information is not included in the vertical blanking period. In the power saving period, the image sensor 1 stops output for power reduction, and then continuously outputs a signal including an error correction code continuously in the code output period. Note that the data transmission cycle of the image sensor 1 is not limited to this example, and may further include a blanking period in the horizontal direction or no power saving period.

  Returning to FIG. 1, the image signal determination unit 211 determines whether the data signal sent from the image sensor 1 is an image signal based on the processing result of the error correction unit 206. Specifically, as a first determination method, by storing information on how many cycles the effective pixel area is reached in the data portion in each code sequence, the image signal determination unit 211 is based on the information. It is possible to detect the timing at which the image signal is sent and prepare the operation of each internal circuit such as the image processing unit 210.

  As a second determination method, the image signal determination unit 211 may determine an effective image region based on whether or not code sequence errors continuously occur. In the code output area, the image sensor 1 and the system LSI 2 both transmit and receive an error correction code obtained by a predetermined calculation formula, so that the result of the error correction decoding operation is always error-free. On the other hand, the value of each pixel of the image array 101 is transferred in the effective image area. The value of the pixel is a result of light reception by the image array 101. For example, in a situation where intense light enters and is saturated, it becomes 0xFF, and in a situation where no light enters at all, it becomes 0x00. Therefore, the value of each pixel depends on the subject to be photographed, and is a virtually random value.

  When an error correction decoding operation is performed on such a random value, an error occurs in almost all cases. In rare cases, even if there is no error, the probability that it will continue is so small that it can be ignored. To be more careful, the value is set to 1 when a fixed value is output so that the first effective pixel area always has an error, or when the pixel data coincides with the error correction code. It is possible to take a countermeasure such that an error is intentionally detected by shifting.

  As shown in FIG. 2, the effective pixel area and the code output area appear alternately. Therefore, an error has occurred in the code output area as soon as the error correction unit 206 has reached the effective image area. That is, when errors occur continuously in the error correction unit 206, it can be determined that it is an effective image area. By adopting both the first and second determination methods, the reliability of image region determination can be further increased.

  Next, the phase adjustment of the data signal by the delay adjustment unit 209 will be described. FIG. 3 is a timing chart of the data signal and clock signal of each delay amount after the phase adjustment is completed. The data signal becomes effective in order from the smallest delay amount. Since each FF latches the data signal at the rising edge of the clock signal, in the case of FIG. 3, any FF can latch the data signal at the correct valid timing.

  FIG. 4 is a timing chart of the data signal and clock signal of each delay amount before the phase adjustment is completed. In the case of FIG. 4, only a data signal with a small delay amount is effective at the rising edge of the clock signal. That is, valid data (for example, “0”) is latched if the data signal has a small delay amount, and invalid data (for example, “1”) is latched if the data signal has other delay amounts. Since the system LSI 2 may malfunction in this state, the delay adjustment unit 209 adjusts the delay amount in the signal delay unit 202 as follows.

  FIG. 5 shows a flow of increasing / decreasing the signal delay amount in the signal delay unit 202. The error correction unit 206 performs error correction processing of the code sequence. If there is an error, the delay adjustment unit 209 compares the error correction processing target code sequence with the outputs of the shift registers 207 and 208, respectively. Based on this, the signal delay amount in the signal delay unit 202 is increased or decreased. For example, it is assumed that the code sequence subject to error correction is “10111011” and there is an error in the third bit. Assume that the outputs of the shift registers 207 and 208 are “10011011” and “10111011”, respectively. In this case, the delay adjustment unit 209 compares the third bit of the code sequence subject to error correction processing with the third bit of the output of the shift registers 207 and 208, and the output of the shift register 207 having a different bit value is correct. That is, it is determined that the delay amount of the data signal should be reduced. Then, the signal delay unit 202 is instructed to reduce the signal delay amount as a whole. As a result, the phase of the data signal changes from the state shown in FIG. 4 to the state shown in FIG. 3, and the data signal can be correctly latched in the system LSI 2.

  Next, with reference to FIG. 6, a method of transitioning from a state in which the phase is completely off immediately after power-on or the like to a state in which the above-described phase adjustment is possible will be described. First, the error correction unit 206 always decodes the data signal that is sent and detects the code output area. This period is, for example, two screens. If this period is waited, the code output period should elapse at least once. Strictly speaking, the waiting time for the code output period to elapse once may be shorter than two screens. However, for simplification of explanation, two screens are waited here. If the code output area can be detected at this time, the phase is roughly adjusted, and after that, normal phase adjustment may be performed. When the code output area cannot be detected, the delay time is shifted as a whole to search for a delay time that can be detected by the code output area. As a method of implementing this brute force, a method of starting from a predetermined initial value or a method of starting from the minimum value of the adjustment range can be considered, but as long as the entire range of the adjustment range can be covered as a result, The method may be used.

  As described above, according to the present embodiment, it is possible to determine whether or not the data signal is a video signal from the error correction processing result of the data signal output from the image sensor 1, and to adjust the latch timing of the data signal.

(Second Embodiment)
FIG. 7 shows a configuration of an imaging system according to the second embodiment. Hereinafter, differences from the first embodiment will be described. In the image sensor 1, the code generation unit 102 with a code recording function stores a plurality of predetermined code sequences, and outputs an appropriate code sequence according to the state of the image sensor 1. The bit width of the data signal line 104 is 8 bits, and the transmission interface 103 transmits the data signal by shifting the timing bit by bit from the MSB of the data signal line 104 in order.

  In the system LSI 2, the signal delay unit 202 can generate three types of delays, that is, a relatively large delay, a relatively small delay, and an intermediate delay for each bit of the signal received by the reception interface 201. . In other words, the system LSI 2 has three buses: a bus max having a relatively large delay, a bus min having a relatively small delay, and a bus type having an intermediate delay. These buses are connected to latch logics 213, 214, and 215 with a signal line selection function, respectively. The latch logics 213, 214, and 215 have a function of latching a data signal from the MSB of each bus and sending a signal to the subsequent stage for each cycle.

  Next, a method for adjusting a delay of a plurality of bits will be described. FIG. 8 is a timing chart of data signals and clock signals output from the image sensor. The code generation unit 102 stores seven patterns of 8-bit codes from code A to code G. The code A consists of 8 bits A0, A1, A2, A3, A4, A5, A6 and A7. When outputting the code A in the code output area, the transmission interface 103 outputs A0 to Data [7], which is the most significant bit of the data signal 104, in the first cycle. In the next cycle, A1 is output to the second Data [6] from the top. In this manner, A7 is finally output to Data [0]. The same output is performed for the code B and thereafter, and after the code G is finally output, the same output is repeated from the code A. Therefore, error correction codes are scattered over all bits of the data bus.

  Since the latch logics 213, 214, and 215 send signals to the subsequent stage in order from the MSB, for example, assuming that A0 starts the operation to send to the subsequent stage at the timing of Data [7], the code A is finally sent to the subsequent stage. Will be. If B0 is at the timing of Data [7], the code B is sent to the subsequent stage. As described above, if the image sensor 1 transmits a code over a plurality of bits bus according to a predetermined rule and the system LSI 2 receives the code according to the rule, the original code can be restored.

  The signal delay amount is increased or decreased for each bit. That is, the delay adjustment unit 209 controls the signal delay unit 202 so that the signal delay amount of Data [5] is reduced when there is an error in the third bit as in the example shown in FIG.

  As described above, according to the present embodiment, when the image sensor 1 and the system LSI 2 are connected by a data signal having a plurality of bit widths, the phase of the circuit according to the first embodiment can be reduced with a circuit scale smaller than simply arranging the configuration according to the bit width. Adjustments can be made. In addition, since the bit position of the code is uniquely determined from the bit of the data signal line, it is advantageous in performing error correction operation that the bit position of the code is shifted every cycle.

  The imaging system according to the present invention can determine whether or not it is a video signal from the data signal itself output from the image sensor without providing an additional signal line between the image sensor and the DSP. Therefore, it is useful as a digital video camera or a digital still camera that requires moving images or continuous shooting.

DESCRIPTION OF SYMBOLS 1 Image sensor 101 Pixel array 102 Code generation part 103 Transmission interface 2 System LSI (semiconductor integrated circuit)
201 reception interface 202 signal delay unit 206 error correction unit 209 delay adjustment unit 211 image signal determination unit

Claims (9)

A receiving interface for receiving an external signal output from the image sensor;
A signal delay unit that delays the received external signal and outputs a first signal;
An error correction unit that performs error correction of the code sequence of the first signal;
A semiconductor integrated circuit comprising: an image signal determination unit that determines whether or not the external signal is an image signal based on a processing result of the error correction unit. The semiconductor integrated circuit according to claim 1.
The image signal determination unit determines that the external signal is an image signal when a code error of the code sequence of the first signal continuously occurs. The semiconductor integrated circuit according to claim 1.
The image signal determination unit detects a timing at which an image signal is transmitted from the image sensor based on information included in a code sequence of the first signal. The semiconductor integrated circuit according to claim 1.
The signal delay unit outputs the second and third signals by delaying the received external signal by a smaller delay amount and a larger delay amount than the first signal, respectively.
The semiconductor integrated circuit is
Based on the presence or absence of a code error in the code sequence of the first signal and the comparison result between the code sequence of the first signal and the code sequences of the second and third signals, the signal delay in the signal delay unit A semiconductor integrated circuit comprising a delay adjustment unit for increasing or decreasing the amount. The semiconductor integrated circuit according to claim 4.
The reception interface receives an external signal having a plurality of bit widths from the image sensor,
The semiconductor integrated circuit according to claim 1, wherein the delay adjusting unit increases or decreases a signal delay amount independently of each bit of the received external signal. A pixel array including a collection of light receiving elements, a code generation unit that generates a code sequence including an error correction code, and a transmission interface that transmits a signal output from the pixel array and a code sequence generated by the code generation unit to the outside An image sensor having
An imaging system comprising: the semiconductor integrated circuit according to claim 1, which processes an external signal output from the image sensor. A pixel array including a collection of light receiving elements, a code generation unit that generates a code sequence including an error correction code, and a transmission interface that transmits a signal output from the pixel array and a code sequence generated by the code generation unit to the outside An image sensor having
A semiconductor integrated circuit according to claim 4 for processing an external signal output from the image sensor;
The imaging system according to claim 1, wherein the transmission interface transmits a signal having a plurality of bit widths, and transmits each bit of the signal having the plurality of bit widths at different timings. The imaging system according to any one of claims 6 and 7,
The code generation unit outputs a stored predetermined code sequence. The imaging system according to any one of claims 6 and 7,
The code generation unit generates a code sequence by calculation.

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