JP2011222074A - Semiconductor integrated circuit, refresh control circuit and refresh control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which necessary irreducible refresh intervals of a memory matrix can be set.SOLUTION: A semiconductor integrated circuit includes a memory matrix 165 having cells, a refreshing control part 155 that refreshes the cells, and an RFC control part 150 which verifies the refreshing. The cells are used for data storage and verification. The RFC control part determines whether an address of the refreshing matches an address of a cell for verification; when they match each other, saves data of the cell for verification; changes a write potential for the cell for verification to a write potential in the verification; determines whether writing at the write potential is successful; and outputs a control signal for making the intervals of refreshing long when being successful and short when ending in failure to the refreshing control part 155. The refreshing control part 155 changes the intervals of refreshing in accordance with the control signal. The RFC control part writes the saved data back to the cell for verification.

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a refresh control circuit and a refresh control method for a semiconductor integrated circuit.

  In recent years, semiconductor integrated circuits are required to have low power consumption. In particular, a memory cell constituting a DRAM (Dynamic Random Access Memory) has a leak, so that the retained charge flows out and data is lost. For this reason, it is necessary to perform a data write-back process called refresh at regular intervals. Since the refresh process involves current consumption, it is desired to perform the refresh process with the minimum necessary.

  Generally, when the temperature becomes higher or lower than normal temperature due to operation or environmental change, the leak amount of the memory cell changes. Accordingly, it is necessary to change the refresh interval. Currently, as a method of changing the refresh interval, measures are taken such as a method of giving a large margin to the refresh interval, or a method of roughly changing the refresh interval by a temperature gradient of an internal element such as a resistor. However, these methods cannot obtain an optimal refresh interval, and always involve useless current consumption.

  As a related technique, Japanese Patent No. 3285611 discloses a dynamic semiconductor memory device (DRAM). The DRAM described in Japanese Patent No. 3285611 will be described. FIG. 1 is a block diagram showing a configuration of a specific example of a DRAM according to Japanese Patent No. 3285611. This DRAM comprises an input means 1, a column control means 2, a row control means 4, a sense amplifier 5, a memory matrix 3, and a refresh means 8. The input means 1 includes an external address information (A1 to A11) input stage EAD and an input stage IN to which a control signal, a row address strobe RAS (bar) and a column address strobe CAS (bar) are input. Is done. The column-related control means 2 includes a column-related control circuit 21, a column-related address buffer 22 and a column decoder 23. The row-related control means 4 includes a row-related control circuit 41, a row-related address buffer 42 and a row decoder 43. The refresh unit 8 refreshes information stored in each of the memory matrices provided in the memory matrix 3. This DRAM is further provided with a refresh check cell array 6. At least one refresh check cell array 6 is provided in parallel with either the word line or the bit line of the memory matrix 3 to adjust the refresh time.

  In this DRAM, a refresh check cell array 6 composed of memory cells having the same configuration as a plurality of memory cells constituting the memory matrix 3 is arranged adjacent to the memory matrix 3. The refresh check cell array 6 is refreshed at the timing when the memory matrix 3 is refreshed. By discriminating the results of these refresh operations by a method to be described later, it is detected whether or not the refresh operation has been executed normally. When it is determined that the refresh operation is normal, the time interval of the refresh operation, that is, the generation cycle of the refresh clock is lengthened or left unchanged. Conversely, when it is determined that the refresh operation is abnormal, an adjustment operation is performed so as to shorten the time interval of the refresh operation, that is, the generation period of the refresh clock.

  In this DRAM, the memory cells constituting one word line WL of the memory matrix 3 are arranged outside the memory matrix 3 and adjacent to the memory matrix 3 and in parallel with the word lines WL of the memory matrix 3. A refresh check cell array 6 having the same number of memory cells is provided. Further, refresh read / write means 7 is provided for writing predetermined information to each memory cell of the refresh check cell array 6 and reading predetermined information therefrom. Further, refresh check means 9 is provided for determining the refresh state of the refresh check cell array 6 based on the result of the refresh read / write means 7 reading the information contained in the refresh check cell array 6. Further, a new row decoder 43-1 is provided in the row decoder 43 of the row control means 4 so that the address of the refresh check cell array 6 can be specified. Further, in order to designate the row decoder 43-1, the counter in the refresh address counter 83 in the refresh means 8 is incremented by one so that, for example, the 4096 + 1th address can be designated.

  Next, the refresh operation of this DRAM will be described. When a refresh operation for each memory cell of the memory matrix 3 is entered, the first word line WL-1 to the word line WL- of the memory matrix 3 are followed according to a clock generated from the clock generating means 81 with a period of 16 μs. Each word line WL up to 4096 is selected sequentially. Then, predetermined information from the external address is written into each memory cell of the selected word line WL via the sense amplifier 5. When such a refresh operation reaches the 4096th word line WL, then the refresh address counter 83 of the refresh means 8 designates the 4096 + 1th address, whereby the row address corresponding to the refresh check cell array 6 is obtained. Since the row address decoder 43-1 is selected via the row address buffer, the refresh check cell array 6 is selected as a refresh target.

  The refresh read / write means 7 writes information “1”, that is, “H” level in advance in all the memory cells of the refresh check cell array 6 via the sense amplifier 5. When the refresh check cell array 6 is selected in the refresh operation, all the memory cells of the refresh check cell array 6 are “1” or the information of at least one memory cell is changed to “0”. The refresh check means 9 determines whether or not there is any. After executing such a determination, the refresh read / write means 7 sends information “1” to all the memory cells of the refresh check cell array 6 through the sense amplifier 5 again to the selected refresh check cell array 6. Write and put.

  With this configuration, the refresh check cell array 6 is refreshed at predetermined intervals, and at the same time, it is determined whether or not the refresh is normally performed. That is, in this DRAM, the refresh check cell array 6 is refreshed at least in the same cycle as each memory cell in the memory matrix 3. If there is a memory cell whose information changes to “0” among the memory cells in the refresh check cell array 6, the refresh in all the memory cells in the memory matrix 3 is performed. It is determined that the required time is shortened. Based on the determination, the refresh control circuit is adjusted so as to shorten the time interval for performing the refresh operation, that is, the refresh operation cycle.

Japanese Patent No. 3285611

  In the technology disclosed in Japanese Patent No. 3285611 (DRAM in FIG. 1), a refresh check cell array (refresh check cell array 6) is placed in parallel with either the word line WL or the bit line BT of the memory matrix 3. The refresh time of the memory cells in the memory cell matrix 3 is checked instead of the memory cells of the refresh check cell array (refresh check cell array 6). This is intended to reduce the refresh time of the memory cells in the memory matrix 3.

  However, when the memory cell characteristics in the memory matrix 3 are to be substituted with the refresh check cell array 6 arranged on one side of the memory matrix 3 as in this DRAM, a margin is provided for the refresh interval (reducing the refresh interval). ) There is a need. Therefore, there is a problem that wasteful current consumption occurs due to the allowance.

  The reason is as follows. As the storage capacity of the semiconductor memory device increases, the number of memory cells arranged on one side increases. The shape of the memory cell itself is affected by the regularity and density of the peripheral pattern of the memory cell. For this reason, the shape of the memory cell itself is often different between the periphery and the center of the memory matrix 3. Therefore, the characteristics of the memory cells may change greatly between the periphery and the center of the memory matrix 3. Further, since the power supplied to the center of the memory matrix 3 is limited, it is also affected by wiring. Further, when a defective cell in the memory matrix 3 is replaced with a replacement circuit or the like, the characteristics of the replacement circuit may differ from the characteristics of the memory cell in the memory matrix 3 due to the influence of the replacement destination wiring or peripheral circuit. Conceivable. Furthermore, when the characteristics are checked by substituting the memory matrix 3 with the refresh check cell array 6, the memory cells in the refresh check cell array 6 and the memory cells in the memory matrix 3 have different usage frequencies, so they do not appear immediately. It is also conceivable that the characteristics of the memory cells in the memory matrix 3 are deteriorated as compared with the refresh check cell array 6 due to such characteristic changes. In that case, it becomes a defective refresh product.

  The refresh check cell array 6 arranged on one side of the memory matrix 3 is greatly different from the memory matrix 3 in the number, arrangement and use frequency of the memory cells. Therefore, it is extremely difficult to find the true minimum refresh time of the memory matrix 3 only by looking at the characteristics of the refresh check cell array 6. This is because, as described above, the memory matrix 3 has variations in the characteristics of the memory cells constituting the matrix. For this reason, if the refresh interval is long, the data in the memory cell having a large leak (poor characteristic) due to variations will be lost. In order to prevent data loss, it is necessary to provide a margin by shortening the refresh interval in consideration of variations. As a result, the number of refresh operations increases and wasteful current consumption occurs.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the embodiments for carrying out the invention. These numbers and symbols are added with parentheses in order to clarify the correspondence between the description of the claims and the mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  The semiconductor integrated circuit according to the present invention includes a memory matrix (165) having a plurality of memory cells, a refresh control unit (155) for executing refresh of the plurality of memory cells, and an RFC for verifying whether refresh is properly executed. And a control unit (150, 162, 170, 171, 173, 174). Multiple memory cells are used for both data storage and verification. The RFC control unit (150 or the like) includes a refresh address storage unit (151) that holds an address of a verification memory cell among a plurality of memory cells, and a data storage unit (a data storage unit that saves data of the verification memory cell). 174) and a write potential storage unit (153) for storing a write potential for verification. The RFC control unit (150, etc.) determines whether the address of the memory cell to be refreshed by the refresh control unit (155) matches the address of the refresh address storage unit (151). If the determination results match, the data in the verification memory cell is saved in the data storage unit (174). Based on the write potential at the time of verification of the write potential storage unit (153), the write potential for the verification memory cell is changed to the write potential at the time of verification. The success or failure of the result of writing to the memory cell with the write potential at the time of verification is determined. If the determination result is successful, the refresh interval is lengthened, and if it is unsuccessful, a control signal for shortening the refresh interval is output to the refresh control unit (155). The refresh control unit (155) changes the refresh interval based on the control signal. The RFC control unit (150 or the like) writes the data in the data storage unit (174) back to the verification memory cell.

  Since the semiconductor integrated circuit of the present invention has the above-described configuration, the minimum refresh interval is inspected using the memory matrix (165) itself without using the substitute check array, and the refresh time is set according to the inspection result. Can be set. As a result, the refresh time can be extended to eliminate unnecessary refresh operations and reduce current consumption.

In the semiconductor integrated circuit refresh control method according to the present invention, the semiconductor integrated circuit has a memory matrix (165) having a plurality of memory cells, a refresh control unit (155) for performing refresh of the plurality of memory cells, and refresh is appropriate. And an RFC controller (150, 162, 170, 171, 173, 174) for verifying whether or not it is executed. Multiple memory cells are used for both data storage and verification. The RFC control unit (150, 162, 150, 162, 170, 171, 173, 174) includes a refresh address storage unit (151) that holds an address of a verification memory cell among a plurality of memory cells, and a verification A data storage unit (174) for saving data of the memory cells and a write potential storage unit (153) for storing a verification write potential.
In the refresh control method of the semiconductor integrated circuit, the address of the memory cell that the RFC control unit (150, etc.) intends to refresh and the address of the refresh address storage unit (151) match. If the determination result is coincident with the determination result, the RFC control unit (150 or the like) saves the data of the verification memory cell in the data storage unit (174) and the RFC control unit (150 or the like). ) Changes the write potential to the verification memory cell to the write potential at the time of verification based on the write potential at the time of verification of the write potential storage unit (153), and the RFC control unit (150, etc.) A step of determining success or failure of a result of writing to the memory cell at a write potential at the time of verification; and an RFC controller (150 However, if the determination result is successful, the refresh interval is lengthened. If the failure is unsuccessful, a control signal for shortening the refresh interval is output to the refresh controller (155), and the refresh controller ( 155) includes a step of changing a refresh interval based on the control signal, and a step in which the RFC control unit (150, etc.) writes the data in the data storage unit (174) back to the verification memory cell. To do. Also in this case, the same effect as the semiconductor integrated circuit of the present invention can be obtained.

  According to the present invention, the minimum necessary refresh interval of the memory matrix can be set. As a result, the refresh time can be extended to eliminate unnecessary refresh operations and reduce current consumption.

FIG. 1 is a block diagram showing a configuration of a specific example of a DRAM according to Japanese Patent No. 3285611. FIG. 2 is a block diagram showing an example of the configuration of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention. FIG. 3A is a flowchart showing an example of operations of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention. FIG. 3B is a flowchart showing an example of operations of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention. FIG. 4 is a flowchart showing an example of the read operation of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 5 is a flowchart showing an example of the write operation of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a block diagram showing an example of the configuration of the semiconductor integrated circuit and the refresh control circuit according to the second embodiment of the present invention.

  Embodiments of a semiconductor integrated circuit, a refresh control circuit, and a refresh control method according to the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
A configuration of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention will be described.
FIG. 2 is a block diagram showing an example of the configuration of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention. FIG. 2 shows an example of a circuit including a DRAM (Dynamic Random Access Memory) as a semiconductor integrated circuit. The MUX shown below is an abbreviation for MULTIPLEXER (multiplexer), and is a destination switching device.

  This semiconductor integrated circuit includes a refresh control circuit 155, an RFC control circuit 150, an address MUX 160, an address latch 161, an address comparison circuit 162, a predecoder 163, a row decoder 164, a column decoder and sense amplifier 166, a data amplifier 167, and a memory matrix 165. , A command control circuit 169, a timing controller 168, a memory cell write potential change circuit 171, a refresh success / failure determination circuit 170, a data MUX 173, a data register 174, and a data latch 172.

  The refresh control circuit 155 is paused when the refresh enable 127 signal from the command control circuit 169 is not received (the signal is not activated, the same applies hereinafter). When the signal from the refresh enable 127 is received (the signal is activated, the same applies hereinafter) and the refresh control change signal 120 is not received from the RFC control circuit 150, the refresh address 122 is output to the address MUX 160. The refresh timing 131 is output to the timing controller 168. The operation when the refresh control change signal 120 is not received is a normal refresh operation performed by a general DRAM. When the refresh control change signal 120 from the RFC control circuit 150 is received while the signal from the refresh enable 127 is received from the command control circuit 169, the refresh check in the memory matrix 165 is performed in response to the refresh increase / decrease signal 121. The refresh operation is executed. In addition, the refresh address 122 is output to the address MUX 160. The refresh check will be described later.

The refresh control circuit 155 includes an oscillation circuit 156, a refresh time adjustment circuit 157, a refresh continuous increase counter 158, and a refresh interval register 159.
The transmission circuit 156 transmits a predetermined oscillation frequency for adjusting the refresh interval.
The refresh time adjustment circuit 157 is a circuit that adjusts the interval for performing the refresh operation, and adjusts the interval of the refresh operation with reference to the signal of the oscillation circuit 156 and the value of the refresh interval register 159.
The refresh continuous increase counter 158 responds to the refresh control change signal 120 and the refresh increase / decrease signal 121 from the RFC control circuit 150. When an increase direction signal comes to the refresh increase / decrease signal 121, the number of times the increase direction signal has been received is counted. This is a count for determining whether the refresh interval can be increased (expanded, the same applies hereinafter) for all cells. The refresh interval can be increased by counting the number of cells in the memory matrix 165. And the value of the refresh interval register 159 is increased. When the refresh increase / decrease signal becomes a decrease direction signal, the data in the memory matrix 165 is destroyed unless the refresh interval is reduced (shortened, hereinafter the same), and therefore the value of the refresh interval register 159 is decreased. When the value of the refresh interval register 159 is increased or decreased, the refresh continuous increase counter 158 is reset.
The refresh interval register 159 stores a value indicating the timing of the refresh operation (refresh interval) performed at the time of the refresh check, and is increased or decreased in response to the refresh continuous increase counter 158 and the refresh increase / decrease signal 121.

  The RFC (refresh check) control circuit 150 is suspended in a state where the refresh enable 127 signal from the command control circuit 169 is not received. When the signal of the refresh enable 127 from the command control circuit 169 is received and the signal from the RC (refresh check) -enable 100 is not received, the refresh control change signal 120 is turned off to the refresh control circuit 155. When the signal from the RC-enable 100 is received in the state where the signal of the refresh enable 127 from the command control circuit 169 is received, the refresh check is executed. The refresh check refers to whether there is no data destruction when refreshing at an interval specified by the refresh interval register 159 with respect to an address given by RC-RAS and RC-CAS (a memory cell is correctly recharged). And a refresh increase / decrease signal 121 is output to the refresh control circuit 155 to set a refresh interval (time). In this embodiment, the refresh interval is inspected using cells specified by RC-RAS and RC-CAS in the memory matrix 165 without using a substitute check array. The difference between the normal refresh operation and the refresh check refresh operation is whether or not the control of the refresh interval is left to the RFC control circuit 150.

  The RFC control circuit 150 performs a refresh check when a signal from the RC-enable 100 is received in a state where the signal of the refresh enable 127 from the command control circuit 169 is received, and performs the refresh check at that time. RC-RAS and RC-CAS indicating addresses in the memory matrix 165 are received, and a refresh control change signal 120 and a refresh increase / decrease signal 121 are output. Further, the RFC control circuit 150 outputs an address and control signal 124 to the address comparison circuit 162. In response to this, an address hit signal 123 is returned from the address comparison circuit 162. In addition, a refresh test signal 135 is output to the refresh success / failure determination circuit 170. In response to the refresh test signal 135, a refresh success / failure signal 136 is returned from the refresh success / failure determination circuit 170. Further, the data flow control 138 is output to the data register 174 and the data MUX 173. Write control 133 is output to the write potential change circuit 171 of the memory cell. A read control write back control signal 125 at the time of hit is output to the timing controller 168.

The RFC control circuit 150 includes a refresh address register 151, a hit count register 152, a memory cell write potential register 153, and a data write back flag 154.
The refresh address register 151 stores the address of the memory cell to be refreshed in the memory matrix 165 input from the RC-RAS 101 and RC-CAS 102. The address fetch timing from the RC-RAS 101 and RC-CAS 102 to the refresh address register 151 is determined by the RFC control circuit 150 according to the progress of the refresh check (details of the operation will be described later).
The number-of-hits register 152 stores the number of times the address hit signal 123 coming from the address comparison circuit 162 has been received (how to count the number and the timing of clearing will be described later).
The memory cell write potential register 153 stores data indicating the write potential when writing to the refresh check target memory cell during the refresh check. This exists in order to change the potential to be written at the refresh check with respect to the potential to be written in the normal refresh operation.
The data write-back flag 154 indicates that data to be stored at the address indicated by the refresh address register 151 is destroyed (erased) when a refresh check is performed on the address indicated by the refresh address register 151 in the memory matrix 165. This indicates that the data saved in the data register 174 needs to be written back to the memory matrix 165 when the refresh check is completed.

  The address MUX 160 is used in a general operation (data refresh enable from the command control circuit 169) for reading and writing data to the address on the memory matrix 165 specified by the external input address RAS 103 and the address CAS 104. If the address 127 is not received), the address signals RAS 103 and CAS 104 are output to the address latch 161. When the refresh enable 127 is received from the command control circuit 169, the refresh address 122 from the refresh control circuit 155 is output to the address latch 161 as an address signal.

  The address latch 161 outputs an address signal from the address MUX 160 to the address comparison circuit 162 in response to the active 126 from the command control circuit 169.

  The address comparison circuit 162 outputs the address signal from the address latch 161 to the predecoder 163. At that time, based on the address from the RFC control circuit 150 and the control signal 124, the address signal from the address latch 161 and the address signal from the RFC control circuit 150 are compared. Output to the RFC control circuit 150.

  The predecoder 163 compares the address to the row decoder 164, the column decoder, and the sense amplifier 166 in response to a decode timing 128 (generated when reading, writing, or refreshing an address in the memory matrix 165) from the timing controller 168. An address signal from the circuit 162 is output.

  The row decoder 164 responds to the address signal from the predecoder 163 and the decode timing 128 from the timing controller 168 (occurred when reading, writing or refreshing the address in the memory matrix 165). For example, a word line is selected and driven.

  The column decoder and sense amplifier 166 receives the address signal from the predecoder 163 and sense / decode timing 129 from the timing controller 168 (occurred when reading, writing, or refreshing the address in the memory matrix 165). In response, for example, bit lines of the memory matrix 165 are selected and driven. Then, data is read from the memory matrix 165 to the data 139. Further, the data from the data amplifier 167 is written into the memory matrix 165.

  The data amplifier 167 executes input / output of data between the data MUX 173 and the memory matrix 165 in accordance with the write timing 130 from the timing controller 168 (generated at the time of writing or refreshing the address in the memory matrix 165). To do. Further, the write potential 134 is received from the write potential change circuit 171 of the memory cell, and writing is executed at the write potential.

  The timing controller 168 receives the control signal 125 at the time of hit from the RFC control circuit 150, the refresh timing 131 from the refresh control circuit 155, and the active / write 132 signal from the command control circuit 169, and sends it to the memory matrix 165. In order to perform read, write, and refresh operations, the decode timing 128 is output to the predecoder 163 and the row decoder 164, the sense / decode timing 129 is output to the column decoder and the sense amplifier 166, and the write timing is output to the data amplifier 167. 130 is output.

  The command control circuit 169 responds to control signals (commands) including externally input CLK (clock) 105, CSB (chip select) 106, WEB (read / write switching) 107, and REFB (refresh mode) 108, and the memory A refresh enable 127 is output to the refresh control circuit 155, the address MUX 160, and the RFC control circuit 150, and an active 126 is output to the address latch 161 in order to perform read, write, and refresh operations designated by external input to the matrix 165. Then, the active / write 132 is output to the timing controller 168 and the read / write 137 is output to the data latch 172.

  The refresh success / failure determination circuit 170 is suspended when the refresh test signal 135 from the RFC control circuit 150 is not received (other than during refresh check). When the refresh test signal 135 is received from the RFC control circuit 150 (during the refresh check), the check data is written into the memory matrix 165 via the data MUX 173 and the data 139 when the refresh check data is written. When the refresh check data is read, the check data is read from the memory matrix 165 via the data 139 and the data MUX 173, and a refresh success / failure signal 136 indicating whether or not the check data written when the refresh check data is written is normal. Output to the RFC control circuit 150.

  The memory cell write potential changing circuit 171 is a circuit for changing the potential to be written when data is written to the memory matrix 165. When the write control 133 from the RFC control circuit 150 is not present, the DRAM general write potential is set. Is output to the data amplifier 167. When the write potential control 133 comes from the RFC control circuit, the write potential 134 indicating the refresh check write potential is output to the data amplifier 167.

  Based on the read / write 137 from the command control circuit 169, the data latch 172 outputs the data-in 109 that is an external input to the data MUX 173 as the data 139, and the data 139 that is the input from the data MUX 173 to the outside. The data output 110 is output.

  The data MUX 173 switches the connection between the data latch 172, the data amplifier 167, the refresh success / failure determination circuit 170, and the data register 174 based on the data flow control 138 from the RFC control circuit 150 and changes the path of the data 139. .

  The data register 174 inputs / outputs data 139 (saved data) via the data MUX 173 based on the data flow control 138 from the RFC control circuit 150.

  In each of the above configurations, the RFC control circuit 150, the address comparison circuit 162, the refresh success / failure determination circuit 170, the memory cell write potential change circuit 171, the data MUX 173, and the data register 174 control the refresh check in this embodiment. Therefore, it can be regarded as an RFC control unit.

  Next, operations (refresh control method) of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention will be described.

First, the refresh operation (refresh mode) will be described. It is assumed that the command control circuit 169 enters the refresh mode in response to the external input REFB 108 and the refresh enable 127 is output.
The initialization process will be described with reference to FIG. When the power is turned on, the refresh interval register 159 is set to a predetermined value. The reason why the predetermined value is set is to prevent destruction (disappearance) of data due to the refresh time not being adjusted during the first refresh operation. The hit count register 152 is reset to “0” when a transition is made from the normal operation state (a state in which reading or writing to the memory matrix 165 is performed) to the refresh mode. Also, when the RC-enable 100 changes to “1”, the hit count register 152 is reset to “0”.

  When the RC-enable 100 is “0”, the RFC control circuit 150 does not output the refresh control change signal 120 (or goes to a low level) because it is in an inactive state so that the refresh control circuit 155 does not receive the refresh increase / decrease signal 121. To. The refresh control circuit 155 in a state in which the refresh increase / decrease signal 121 is not received outputs the refresh address 122 with the same operation and timing as the refresh control circuit generally used conventionally. However, the same operation as that of a refresh control circuit that is generally used conventionally includes generation of a refresh address and a refresh timing at a predetermined interval. At that time, the address range is the entire range of the memory matrix 165. All the memory cells in the memory matrix 165 are refreshed by sequentially refreshing all addresses. During the refresh mode, it is repeated to refresh all addresses in order. Hereinafter, it is referred to as “normal refresh”.

  When the RC-enable 100 is “1”, the refresh control circuit 155 receives the refresh increase / decrease signal 121 by the refresh control change signal 120. In this case, the refresh address 122 generated by the refresh control circuit 155 has the same address range as the normal refresh, but the refresh timing is the timing determined by the refresh interval register 159. That is, the refresh timing is changed to a desired value.

  3A and 3B are flowcharts showing an example of the operation (refresh control method) of the semiconductor integrated circuit and the refresh control circuit according to the first embodiment of the present invention. This figure shows the operation in the refresh mode. However, it is assumed that initialization processing at the time of transition to the refresh mode has been completed. It is assumed that the address to be refreshed is switched from the external RAS 103 and CAS 104 to the refresh address 122 from the refresh control circuit 155 by the address MUX 160.

  In the refresh mode in which the RFC control circuit 150 responds to the refresh enable 127, the RFC control circuit 150 determines whether the RC-enable 100 is “0” or “1” (S100). When the RC-enable 100 is “0” (S100: “0”), the RFC control circuit 150 determines whether the data write-back flag 154 is “0” or “1” (S101). When the data write-back flag 154 is “0” (S101: “0”), the RFC control circuit 150 does not output the refresh control change signal 120 (or sets it to the low level). This prevents the refresh control circuit 155 from receiving the refresh increase / decrease signal 121. The refresh control circuit 155 in a state in which the refresh increase / decrease signal 121 is not received performs normal refresh on the memory matrix 165 (S102: If the flow enters the flow of FIG. 3 for the first time, the data write-back flag 154 is “0”. "So this is the behavior).

When the data write-back flag 154 is “1” in the refresh mode in which the RFC control circuit 150 responds to the refresh enable 127 (S101: “1”:
The data write-back flag 154 may become “1” when the flow of FIG. 3 is entered for the second time or later), and the RFC control circuit 150 sends the value of the refresh address register 151 to the address and The address signal coming from the address latch 161 that is currently sent through the control 124 and is currently being refreshed is compared (S103). Specifically, the RFC control circuit 150 outputs the value of the refresh register 151 to the address comparison circuit 162 as an address and control signal 124. The address comparison circuit 162 compares the address signal indicating the address to be refreshed from the address latch 161 with the address from the RFC control circuit 150 and the control signal 124. If the addresses are the same, the address comparison circuit 162 outputs an address hit signal 123 to the RFC control circuit 150.

  When the value of the address signal to be refreshed from the refresh address register 151 is different from the value of the address signal coming from the address latch 161 (hereinafter referred to as “through”) (S103: through), the RFC control circuit 150 The write control 133 is controlled so that the write potential change circuit 171 is refreshed at a normal refresh potential. When the value of the address signal from the refresh address register 151 and the value of the address signal to be refreshed currently coming from the address latch 161 are the same (hereinafter referred to as “hit”) (S103: hit), the RFC control circuit 150 uses the data MUX 173. In response, the data flow control signal 138 outputs a data path switching signal. The data MUX 173 switches the data path connection from the memory matrix 165 to the path connected to the data register 174 via the data MUX 173 based on the data path switching signal of the data flow control 138. As a result, the data saved in the data register 174 (data saved from the memory matrix 165 is included because the data write-back flag 154 is “1”) is output to the memory matrix 165. Then, the data saved in the memory cell (refresh-checked memory cell) existing at the address on the memory matrix 165 that is currently refreshed from the address comparison circuit 162 is written back (S104). After completion of the write-back, the RFC control circuit 150 changes the data write-back flag 154 to “0”, and further connects the data path from the data flow control 138 to the data MUX 173 in a normal state where data can be read / written from the outside ( In order to input / output data, the connection of the data path is returned to the path connected to the data amplifier 167 from the data latch 172 via the data MUX 173 (normal data path) (S105).

When the RC-enable 100 is “1” (S100: “1”), the RFC control circuit 150 determines whether or not the value of the hit count register 152 is “0” (S106). When the number of hits is 0 (S106: Yes), the addresses of the RC-RAS 101 and RC-CAS 102 are stored in the refresh address register 151 (S107). If the number of hits is other than 0 (S106: No), the process proceeds to S108. The refresh address stored in the refresh address register 151 in S107 is compared with the address currently being refreshed (S108). Specifically, as in the case of S103, the value of the address signal from the refresh address register 151 is compared with the value of the address signal to be refreshed that comes from the address latch 161 to check whether it is hit or through.
When the refresh address of the refresh address register 151 is different from the address to be refreshed (S108: Through), the address on the memory matrix 165 to be refreshed is refreshed at a normal potential (S102). When the refresh address of the refresh address register 151 is the same as the address to be refreshed (S108: hit), the value of the hit count register 152 is incremented by 1 (S109). The process is executed at the jump destination corresponding to the value of the hit number register 152 (hit number: examples; 1, 2, 3, 4) (S110).

  When the number of hits (the value of the hit number register 152) is 1 (S110: “1”), the RFC control circuit 150 passes the data path from the data flow control 138 to the data MUX 173 via the memory matrix 165 and the data MUX 173. A signal for switching to the path connected to the data register 174 is sent. Thereby, the data read from the hit address in the memory matrix 165 is stored in the data write-back register 174 via the data MUX 173 (S112). That is, the data stored in the cell on the memory matrix 165 that hits the address indicated by the refresh dress register 151 is saved in the data register 174. After the saving is finished, the RFC control circuit 150 changes the data write-back flag 154 to “1” (S113). At the same time, the data flow control 138 controls the data MUX 173 so that the connection of the data path becomes a normal data path from which data can be read and written.

  When the number of hits (the value of the hit number register 152) is 2 (S110: “2”), the RFC control circuit 150 passes the data path from the data flow control 138 to the data MUX 173 via the data amplifier 167 and the data MUX 173. A signal for switching to the path connected to the refresh success / failure determination circuit 170 is sent. Further, the RFC control circuit 150 sends the value of the write potential register 153 of the memory cell to the write potential change circuit 171 of the cell through the write control 133, and the write potential 134 is transferred from the write potential change circuit 171 of the cell to the normal refresh potential (write). The potential is changed to a slightly lower potential (S114). Thereafter, the RFC control circuit 150 outputs the refresh test signal 135 to the refresh success / failure determination circuit 170, thereby writing to the memory matrix 165 with the changed potential (S115). However, since it is data for checking data destruction of the memory cell due to leakage, “1” is normally written as data for supplying a potential to the memory cell. Thereafter, the RFC control circuit 150 controls the data MUX 173 so that the data flow connection from the data flow control 138 becomes a normal data path from which data can be read and written from the outside. Further, the RFC control circuit 150 returns the value of the write potential register 153 of the memory cell to the normal refresh potential (S116). Thereby, the write potential of the memory cell is restored.

  When the number of hits (the value of the hit number register 152) is 3 (S110: “3”), the RFC control circuit 150 passes the data path from the data flow control 138 to the data MUX 173 via the data amplifier 167 and the data MUX 173. A signal for switching to the path connected to the refresh success / failure determination circuit 170 is sent. The data written in the second hit S115 (data written in the memory matrix 165 at a potential slightly lower than the normal refresh potential) is read to the refresh success / failure determination circuit 170 (S117). The refresh success / failure determination circuit 170 compares the read data with the data written in S115 and outputs a determination result as to whether the data is normal to the RFC control circuit 150 through the refresh success / failure signal 136 (S118). When the data is normal (S118: Yes), the RFC control circuit 150 outputs a refresh increase / decrease signal 121 to the refresh control circuit 155 so as to increase the refresh interval by a predetermined interval (S119). If the data is abnormal (S118: No), the RFC control circuit 150 outputs a refresh increase / decrease signal 121 to the refresh control circuit 155 so as to shorten the refresh interval by a predetermined interval (S120). Thereafter, the RFC control circuit 150 controls the data MUX 173 so that the data flow connection from the data flow control 138 becomes a normal data path from which data can be read and written from the outside.

  When the hit count (value of the hit count register 152) is 4 (S110: “4”), the RFC control circuit 150 changes the hit count register 152 to “0” (S111). The RFC control circuit 150 sends a signal for switching the data path from the data flow control 138 to the path connected to the data register 174 from the memory matrix 165 via the data MUX 173 to the data MUX 173. As a result, the data saved in the data register 174 is output to the memory matrix 165 and written back to the original data (S104). The RFC control circuit 150 changes the data write-back flag 154 to “0”. After the completion of the write back, the RFC control circuit 150 controls the data MUX 173 so that the data flow connection from the data flow control 138 becomes a normal data path from which data can be read / written from the outside (S105).

The operation performed according to the number of hits for the memory cells of the memory matrix 165 to be refresh-checked is briefly described as follows.
First, the data in the memory cell is saved when the hit count is 1 (S112-S113), and when the hit count is 2, the write potential to the memory cell is changed and the data is experimentally written (S114-S115). When the number of times is 3, the experimentally written data is read to determine whether it is normal, and the refresh interval is changed based on normality / abnormality (S117-S120). Returning to 0, the saved data is written back to the memory cell (S111, S104).

  That is, while refreshing the memory matrix 165, with respect to the memory cell subject to the refresh check, from the time of refreshing at a certain time (hit number 1) to the time of performing the fourth refresh (hit number 4), The operation from hit count 1 to hit count 4 is executed. Thereby, the optimum refresh interval can be inspected for the memory cell to be refresh checked. By performing such a refresh check in all the memory cells of the memory matrix 165, it is possible to finally determine an optimum refresh interval for the memory matrix 165.

  The refresh check is performed by dividing the refresh check into a plurality of hits for the following reason. In this embodiment, since a refresh check is performed using a normal memory cell, there is a possibility that an access is performed even during the refresh check. For this reason, the refresh check is not performed all at once but is divided into four steps so that writing or reading may be performed during the refresh check. Note that writing and reading performed during the refresh (check) will be described later.

  The potential slightly lower than the normal refresh potential that is written when the refresh is determined in S115 will be described. The slightly lower potential is about the value of the minimum write potential generated by the variation of the memory cells in the memory matrix 165, and is sufficiently lower than the normal write potential. However, the minimum write potential caused by the variation is the variation of the memory cell even when a normal refresh potential is applied, and the potential applied to a certain memory cell is low, and the value is the minimum in the memory matrix 165. It is a potential. The reason why the potential to be written in the memory cell is written at a potential lower than the normal writing potential (potential with sufficient margin from the minimum writing potential) is as follows. If the data read in S118 is not normal, a refresh failure has occurred at a write potential lower than the potential written to a normal memory cell. Even in this refresh failure state, the memory matrix 165 is adjusted by adjusting the refresh interval using the minimum potential by leaving a margin up to the minimum potential at which the data of the memory cell refreshed at the normal potential is destroyed. It is possible to prevent the data refreshed at the normal write potential written in the memory from being destroyed. That is, by adjusting the refresh interval with a potential lower than the normal writing potential, the adjusted refresh interval can have a margin.

Next, a method for adjusting the refresh interval (time) will be described.
A value indicating a refresh interval is set in the refresh interval register 159 in advance. The refresh time adjustment circuit 157 refers to the value of the refresh interval register 159 and adjusts the refresh interval based on the signal of the oscillation circuit 156. The refresh control circuit 155 generates a refresh address 122 and a refresh timing 131 according to the adjusted refresh interval.

  Here, when the refresh control change signal 120 does not come from the RFC control circuit 150 to the refresh control circuit 155, the refresh interval register 159 has a predetermined value. On the other hand, when the refresh control change signal 120 is received, the operation changes depending on the content of the refresh increase / decrease signal 121 from the RFC control circuit 150. When a signal for shortening the refresh interval comes as the refresh increase / decrease signal 121, the refresh control circuit 155 adjusts the value of the refresh interval register 159 so that the refresh interval is shortened, and clears the refresh increment counter 158. When a signal for increasing the refresh interval is received as the refresh increase / decrease signal 121 and when a “predetermined number of times” is continuously received, the refresh control circuit 155 increases the value of the refresh interval register 159 to increase the refresh interval. Adjust as follows. The adjustment is performed for the predetermined number of times. The refresh continuous increment counter 158 counts the adjusted number of times for each memory cell. For example, when the refresh interval is increased, all the memory cells in the memory matrix 165 are inspected and there are no cells with poor characteristics in the middle. In order to confirm this, the memory matrix 165 has a counter length for continuously counting by the number of all memory cells. By increasing or decreasing the refresh interval, memory cell leakage increases at high temperatures, and when memory cell data is prone to corruption, shortening the refresh interval prevents data corruption and reduces memory cell leakage at low temperatures. In a state where it is difficult to destroy, it is possible to adjust the refresh timing optimally without destroying data by extending the refresh interval.

  Next, a normal operation state (a state in which reading, writing, or the like is performed on the memory matrix 165) is described. That is, reading and writing performed during the refresh (check) will be described. However, it is assumed that the address to be read or written is switched to the external input address RAS 103 and CAS 104 by the address MUX 160.

  The reading state (operation) will be described with reference to the flow of FIG. FIG. 4 is a flowchart showing an example of the read operation of the semiconductor integrated circuit according to the first embodiment of the present invention. In the read state, first, the RFC control circuit 150 checks the data write-back flag 154 (S201). When the data write-back flag 154 is “0” (S201: “0”), since there is no memory cell in which data is saved, data is read from the memory matrix 165 by a normal process (S202). When the write-back flag 154 is “1” (S201: “1”), since there is a memory cell in which data is saved, the address to be read and the address of the refresh address register 151 (data is saved) The address of the memory is compared using the address comparison circuit 162 (S203). If the addresses are different (S203: Through), the data of the memory cell to be read is not saved, so the data is read from the memory matrix 165 by a normal process (S202). If the addresses are the same (S203: hit), the data of the memory cell to be read is saved, and the RFC control circuit 150 outputs the data flow control 138 to the data MUX 173. Based on the data flow control 138, the data MUX 173 switches the data path connection to a path connected from the data latch 172 to the data register 174 via the data MUX 173. As a result, data is read from the data register 174, which is a data save destination, via the data latch 172. Thereafter, the RFC control circuit 150 outputs the data flow control 138 to the data MUX 173, and restores the connection of the data MUX 173 so that the data path becomes a path connected from the data latch 172 to the data amplifier 167 via the data MUX 173. (S204).

  A writing state (operation) will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart showing an example of the write operation of the semiconductor integrated circuit according to the first embodiment of the present invention. In the write state, first, the RFC control circuit 150 checks the data write-back flag 154 (S301). When the data write-back flag 154 is “0” (S301: “0”), there is no memory cell in which data is saved, so the data input from the data-in 109 is written to the memory matrix 165 by a normal process. (S302). When the data write-back flag 154 is “1” (S301: “1”), since there is a memory cell in which data is saved, the address to be written and the address of the refresh address register 151 (the memory in which the data is saved) Are compared using the address comparison circuit 162 (S303). If the addresses are different (S303: through), the data in the memory cell to be written is saved, so the data input from the data-in 109 is written to the memory cell 165 in the memory matrix 165 by a normal process. (S302). When the addresses are the same (S303: hit), since the data of the memory cell to be written is saved, the RFC control circuit 150 changes the write-back flag 154 to “0” (S304). Then, the data input from the data-in 109 is written into the memory cell to be written in the memory matrix 165 by a normal process (S302).

In the present embodiment, by using each memory cell in the memory matrix 165 for the refresh check, an optimum refresh interval (time) that matches the characteristics of the memory cells in the memory matrix 165 can be obtained. Thereby, the refresh interval can be lengthened to reduce power consumption.
The reason is as follows. In the prior art, the characteristics of the memory cell are substituted for the cells of the refresh check cell array 6 around the memory matrix 3, and therefore the characteristics of the memory matrix 3 are not necessarily reflected as they are. However, in this embodiment, data at a specific location in the memory matrix 165 used for the refresh check is saved in the data register 174, the refresh time is adjusted based on the result of the refresh check, and the data is saved after the refresh check is completed. Since the data is retained by rewriting the original data to the original location, the cells in the memory matrix 165 used as the memory including the replacement destination cell replaced by the characteristic deterioration are used for the refresh check. The minimum refresh time required for the memory matrix used in the process can be applied.

(Second Embodiment)
The configurations of the semiconductor integrated circuit and the refresh control circuit according to the second embodiment of the present invention will be described.
FIG. 6 is a block diagram showing an example of the configuration of the semiconductor integrated circuit and the refresh control circuit according to the second embodiment of the present invention. As compared with the first embodiment, the semiconductor integrated circuit according to the present embodiment adds a cyclic address generation circuit 180 to each input terminal portion of the RC-RAS 101 and the RC-CAS 102 and generates a refresh address 122 as a cyclic address. The difference is that the signal is input to the circuit 180.

  The cyclic address generation circuit 180 generates a desired address that circulates (all addresses, address skips, or rounds of a specific address) within the address of the memory matrix 165, and receives the refresh address 122 to generate the next desired address.

  As an operation, the RC-enable 100 and the RC-RAS 101 are set to the memory cells of the memory matrix 165 corresponding to the address generated by the cyclic address generation circuit 180 by fixing the RC-enable 100 to “1”. An address for refreshing is output to the RC-CAS 102. Next, the process proceeds to S106 in FIG. 2 (operation when the RC-enable 100 is “1”). Thereafter, the operation is the same as that of the first embodiment. In the present embodiment, RC-RAS 101 and RC-CAS 102 which are external inputs in the first embodiment are replaced with automatic generation by the cyclic address generation circuit 180.

  A refresh check is performed in the same manner as in the first embodiment, and a desired address is adjusted to the minimum required refresh interval. Further, the memory cell other than the desired address is also adjusted to the refresh interval set above.

  By setting the address generated as the cyclic address to the address of the memory cell having the largest amount of leakage measured in advance, it is possible to perform refresh in accordance with the memory cell having the largest amount of leakage. It is desirable that the number of input terminals be small because various factors (static electricity, noise, etc.) enter from outside. For this reason, external input terminals can be reduced by adding an address generation circuit for generating an address for refresh check.

In each embodiment of the present invention, the following effects can be obtained.
As a first effect, power consumption can be reduced. The reason is that the minimum refresh interval can be inspected using a memory matrix without using a substitute check array, and the refresh interval (time) can be set according to the inspection result. This is because an unnecessary refresh operation can be eliminated by lengthening the current consumption, thereby reducing current consumption.

As a second effect, a decrease in yield due to the memory cell can be suppressed.
The reason for this is that there is no need to prepare refresh check cells separately from the memory matrix, and the peripheral circuit is made with a sufficient margin for the elements and wirings with respect to the cells of the memory matrix. This is because the occurrence rate of defects due to wiring cuts, shoots and shape abnormalities is generally much lower than that of cells, so that a decrease in yield due to cells can be suppressed to the extent that there are no refresh check cells.

  The present invention is not limited to the embodiments described above, and it is obvious that the embodiments can be appropriately modified or changed within the scope of the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 1 Input means 2 Column system control means 3 Memory matrix 4 Row system control means 5 Sense amplifier 6 Refresh check cell array 7 Refresh read / write means 8 Refresh means 9 Refresh check means 21 Column system control circuit 22 Column system address buffer 23 Column decoder 41 Row system control circuit 42 Row system address buffer 43 Row decoder 83 Refresh address counter 100 RC-enable 101 RC-RAS
102 RC-CAS
103 RAS
104 CAS
105 CLK
106 CSB
107 WEB
108 REFB
109 Data-in 110 Data-out 120 Refresh control change signal 121 Refresh increase / decrease signal 122 Refresh address 123 Address hit signal 124 Address and control 125 Hit control signal 126 Active 127 Refresh enable 128 Decode timing 129 Sense / decode timing 130 Write timing 131 Refresh Timing 132 Active / write 133 Write control 134 Write potential 135 Refresh test signal 136 Refresh success / failure signal 137 Read / write 138 Data flow control 139 Data 150 RFC control circuit 151 Refresh address register 152 Hit count register 153 Memory cell write potential register 154 Data writing Flags 155 refresh control circuit 156 oscillation circuit 157 refresh time adjustment circuit 158 refresh continuous increase counter 159 refresh interval register 160 address MUX
161 Address latch 162 Address comparison circuit 163 Predecoder 164 Row decoder 165 Memory matrix 166 Column decoder and sense amplifier 167 Data amplifier 168 Timing controller 169 Command control circuit 170 Refresh success / failure determination circuit 171 Cell write potential change circuit 172 Data latch 173 Data MUX
174 Data register 180 cyclic address generation circuit

Claims (12)

A memory matrix having a plurality of memory cells;
A refresh controller for performing refresh of the plurality of memory cells;
An RFC control unit for verifying whether the refresh is properly executed, and
The plurality of memory cells are used for both data storage and verification;
The RFC control unit
A refresh address storage unit for holding an address of the verification memory cell among the plurality of memory cells;
A data storage unit for saving data of the verification memory cell;
A write potential storage unit for storing the verification write potential,
The RFC control unit
Determining whether the address of the memory cell to be refreshed by the refresh control unit matches the address of the refresh address storage unit;
When the determination result is coincident, the data of the verification memory cell is saved in the data storage unit,
Based on the write potential at the time of the verification of the write potential storage unit, the write potential to the verification memory cell is changed to the write potential at the time of verification,
Determine the success or failure of the result of writing to the memory cell with the write potential at the time of verification,
When the determination result is successful, the refresh interval is lengthened, and when it is unsuccessful, a control signal for shortening the refresh interval is output to the refresh control unit,
The refresh control unit changes the refresh interval based on the control signal,
The RFC control unit writes data in the data storage unit back to the verification memory cell. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
The RFC control unit
An address comparison unit for determining whether the address of the memory cell to be refreshed by the refresh control unit matches the address of the refresh address storage unit;
Based on the write potential at the time of verification of the write potential storage unit, the write potential change unit that changes the write potential to the verification memory cell to the write potential at the time of verification, and the write potential at the time of verification A semiconductor integrated circuit comprising: a refresh success / failure determination unit for determining success / failure of a result of writing to a memory cell. The semiconductor integrated circuit according to claim 1 or 2,
The RFC control unit
When the match of the determination results is the first, the data of the verification memory cell is saved in the data storage unit,
When the determination result coincides with the second time, the write potential to the verification memory cell is changed to the write potential at the verification,
When the determination result coincides with the third time, the control signal is output to the refresh control unit to change the refresh interval,
When the determination result coincides with the fourth time, the data in the data storage unit is written back to the verification memory cell. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1 or 2,
The refresh control unit
A refresh interval storage unit storing the refresh interval that is increased or decreased in response to the control signal;
A semiconductor integrated circuit comprising: a refresh time adjustment unit that adjusts the refresh interval with reference to the refresh interval storage unit. The semiconductor integrated circuit according to claim 1 or 2,
The RFC control unit further includes a data write-back storage unit indicating whether or not the data in the data storage unit is written back to the verification memory cell,
In reading data from a memory cell to be read included in the plurality of memory cells,
When the RFC control circuit refers to the data write-back storage unit and the write-back is not completed,
Determining whether the address of the memory cell to be read and the address of the refresh address storage unit match;
A semiconductor integrated circuit that reads data from the data storage unit when the determination result is coincident, and reads data from the memory cell to be read when the result is not coincident. The semiconductor integrated circuit according to claim 5,
In writing data to a write target memory cell included in the plurality of memory cells,
When the RFC control circuit refers to the data write-back storage unit and the write-back is not completed,
Determining whether the address of the memory cell to be written matches the address of the refresh address storage unit;
If the determination result is coincident, the data write-back storage unit is put in a state where the write-back is completed,
A semiconductor integrated circuit for writing data to the memory cell to be written. The semiconductor integrated circuit according to any one of claims 1 to 6,
A semiconductor integrated circuit, further comprising: a cyclic address generation unit that supplies an address that circulates within an address of the memory matrix as the address of the refresh address storage unit. A refresh control method for a semiconductor integrated circuit, comprising:
The semiconductor integrated circuit is:
A memory matrix having a plurality of memory cells;
A refresh controller for performing refresh of the plurality of memory cells;
An RFC control unit for verifying whether the refresh is properly executed, and
The plurality of memory cells are used for both data storage and verification;
The RFC control unit
A refresh address storage unit for holding an address of the verification memory cell among the plurality of memory cells;
A data storage unit for saving data of the verification memory cell;
A write potential storage unit for storing the verification write potential,
The semiconductor integrated circuit refresh control method comprises:
The RFC control unit determining whether or not the address of the memory cell that the refresh control unit intends to refresh matches the address of the refresh address storage unit;
If the determination result is coincident, the RFC control unit saves the data of the verification memory cell in the data storage unit;
The RFC control unit changing a write potential for the verification memory cell to the write potential at the time of verification based on the write potential at the time of verification of the write potential storage unit;
The RFC control unit determining success or failure of a result of writing to the memory cell at a write potential at the time of verification;
The RFC control unit, when the determination result is successful, to increase the refresh interval, and to fail, output a control signal to the refresh control unit to shorten the refresh interval;
The refresh control unit changing the refresh interval based on the control signal;
A refresh control method for a semiconductor integrated circuit, wherein the RFC control unit includes a step of writing back the data in the data storage unit to the verification memory cell. The semiconductor integrated circuit refresh control method according to claim 8,
The RFC controller is
When the determination result matches first, the step of saving the data of the verification memory cell in the data storage unit;
A step of changing a write potential to the verification memory cell to a write potential at the time of verification when the determination result coincides with the second time;
Outputting the control signal to the refresh controller when the determination result coincides with the third time, and changing the refresh interval;
A refresh control method for a semiconductor integrated circuit, further comprising the step of writing back the data in the data storage unit to the verification memory cell when the determination result matches four times. The semiconductor integrated circuit refresh control method according to claim 8,
The RFC control unit further includes a data write-back storage unit indicating whether or not the data in the data storage unit is written back to the verification memory cell,
The semiconductor integrated circuit refresh control method comprises:
In reading data from a memory cell to be read included in the plurality of memory cells,
When the RFC control circuit refers to the data write-back storage unit and the write-back is not completed,
Determining whether the address of the memory cell to be read matches the address of the refresh address storage unit;
A refresh control method for a semiconductor integrated circuit, further comprising: reading data from the data storage unit if the determination result is coincident; and reading data from the memory cell to be read if the result is disagreement. The semiconductor integrated circuit refresh control method according to claim 10,
The semiconductor integrated circuit refresh control method comprises:
In writing data to a write target memory cell included in the plurality of memory cells,
When the RFC control circuit refers to the data write-back storage unit and the write-back is not completed,
Determining whether the address of the memory cell to be written matches the address of the refresh address storage unit;
If the determination result is coincident, the step of putting the data write-back storage unit in a state where the write-back is completed;
A method of controlling refresh of a semiconductor integrated circuit, further comprising: writing data to the memory cell to be written. The refresh control method for a semiconductor integrated circuit according to any one of claims 8 to 11,
A refresh control method for a semiconductor integrated circuit, further comprising the step of supplying an address that circulates within an address of the memory matrix as the address of the refresh address storage unit.

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