JP2011217173A - Two-dimensional/three-dimensional video processor and video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-dimensional/three-dimensional video processor which can further reduce the size of a circuit, a memory scale, cost, and power consumption.SOLUTION: The two-dimensional/three-dimensional video processor includes: a 2D/3D detection part 10 for detecting whether an input video signal is a two-dimensional video signal or a three-dimensional video signal; a 2D/3D frame generating part 20 for generating a two-dimensional output frame signal or a three-dimensional output frame signal based on a detection result of the 2D/3D detection part 10; and a 2D/3D output timing control part 30 for outputting the two-dimensional output frame signal or the three-dimensional output frame signal in a desired sequence and timing based on a detection result of the 2D/3D detection part 10. The 2D/3D frame generating part 20 and the 2D/3D output timing control part 30 are used in common when the input video signal is the two-dimensional video signal and the three-dimensional video signal.

Description

  The present invention relates to video display processing, and more particularly to a 2D / 3D video processing apparatus that can display 2D and 3D video on the same video display apparatus.

  Currently, the spread of 3D video devices in commercial facilities such as movie theaters is being promoted, and the installation of televisions for home use is about to begin.

  As shown in FIG. 6, in 3D video processing, an input video signal is, for example, a side-by-side format of a broadcasting standard defined by HDMI, which is a standard setting organization, or a Blu-ray Disc (package media). It is transmitted in the top and bottom system of the registered trademark standard. A 3D video apparatus that has received transmissions using these methods, for example, when applying the shutter glasses method, which is one of the 3D video output methods, converts the stereoscopic video signal after performing conversion processing to the frame sequential method. And the viewer wears shutter glasses to view a 3D image.

  On the other hand, in 2D video processing, when the response speed of the display element is slow, such as when a liquid crystal panel is used, an afterimage (moving image blur) may occur in a video with intense movement such as sports. Therefore, so-called double speed conversion processing for doubling the frequency of the input video is performed to eliminate this phenomenon. In the double speed conversion process, for example, a video signal of 60 frames / second (Hz) is converted to 120 frames / second (Hz).

  In the case of displaying 2D and 3D video on the same video display device, in order to perform 2D and 3D video signal processing with different video signal processing contents, conventionally, for 2D video signal processing and 3D video signal Processing was performed by providing a processing circuit and a memory.

  For example, as shown in FIG. 7, a conventional 2D / 3D video display device includes a 2D video signal processing unit 100, a 3D video signal processing unit 110, a 2D / 3D detection unit 120, and a video. And a signal selector 130. The two-dimensional video signal processing unit 100 performs double-speed conversion processing for improving the above-described moving image characteristics, and includes a 2D memory 101, a motion detection circuit 102, an interpolation frame generation circuit 103, and a 2D output timing control circuit 104. It is made up of. The three-dimensional video signal processing unit 110 performs the above-described video signal system conversion processing, and includes a 3D memory 111, a 3D double speed processing circuit 112, and a 3D output timing control circuit 113.

  However, in the conventional technology as described above, since the two-dimensional video signal processing unit and the three-dimensional video signal processing unit are provided, the circuit / memory scale / cost increases and the power consumption also increases. There is a problem that it ends up.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a 2D / 3D video processing apparatus capable of reducing the circuit, memory scale, cost, and power consumption. .

  In order to solve the above problems, a 2D / 3D video processing apparatus according to the present invention includes a 2D / 3D detection unit that detects whether an input video signal is a 2D video signal or a 3D video signal, and an input video signal. It has a frame memory that is used in common in the case of a 2D video signal and a case of a 3D video signal, and 2 based on the input video signal read from the frame memory based on the detection result of the 2D / 3D detector. 2D / 3D frame generation processing unit for generating a 3D output frame signal or a 3D output frame signal, and the 2D output generated by the 2D / 3D frame generation processing unit based on the detection result of the 2D / 3D detection unit And a 2D / 3D output timing controller that outputs a frame signal or a three-dimensional output frame signal in a desired order and timing.

  According to the above configuration, regardless of whether the input video signal is a 2D video signal or a 3D video signal, the input video signal is temporarily stored in a common frame memory and then 2D based on the detection result of the 2D / 3D detection unit. An output frame signal or a three-dimensional output frame signal is generated. As a result, the memory can be reduced as compared with the conventional configuration in which circuits and memories for 2D video signal processing and 3D video signal processing are provided and processed.

  In the 2D / 3D video processing apparatus, the 2D / 3D output timing control unit receives the 2D output frame signal or the 3D output frame signal generated by the 2D / 3D frame generation processing unit as data. And a clock selection unit that selects a desired clock based on the detection result of the 2D / 3D detection unit, and the logic gate element unit is a clock selected by the clock selection unit. Accordingly, the two-dimensional output frame signal or the three-dimensional output frame signal can be output in a desired order and timing.

  According to the above configuration, the two-dimensional output frame signal or the three-dimensional output frame signal input to the logic gate element unit is output in a desired order and timing with a desired clock selected by the clock selection unit. be able to. In this configuration, the logic gate element unit can be used in common for the 2D video signal and the 3D video signal, and the circuit configuration of the 2D / 3D output timing control unit can be simplified. Also, by selecting the optimum clock for each of the 2D video signal and the 3D video signal, the clock output, which was conventionally performed for both processing, is not performed. Electricity will be reduced.

  In the 2D / 3D video processing apparatus, the 2D / 3D detection unit detects whether the input video signal is a 2D video signal or a 3D video signal by detecting a 2D / 3D flag included in the input video signal. Or by extracting features of the input video signal to detect whether the input video signal is a two-dimensional video signal or a three-dimensional video signal.

  In the 2D / 3D video processing apparatus, the 2D / 3D frame generation processing unit performs 2D processing on the frame memory and a 2D video signal read from the frame memory to perform 2D processing. A two-dimensional signal processing unit that generates a double-speed video signal as an output frame signal, and a stereoscopic video signal as a three-dimensional output frame signal by performing a stereoscopic video signal generation process on the three-dimensional video signal read from the frame memory. Based on the detection result of the 3D signal processing unit that generates the video signal and the 2D / 3D detection unit, the double-speed video signal generated by the 2D signal processing unit and the stereoscopic image generated by the 3D signal processing unit An output selection unit that selects and outputs one of the visual video signals can be employed.

  With the above configuration, in the 2D / 3D frame generation processing unit in which the frame memory is shared between the case of 2D video and the case of 3D video, a 2D output frame signal or a 3D output frame signal is appropriately generated. Can be output.

  In the 2D / 3D video processing device, the 2D / 3D output timing control unit may control the video signal at different output timings depending on whether the input video signal is a 2D video signal or a 3D video signal. Can be configured to output.

  In the 2D / 3D video processing apparatus, the 2D / 3D output timing control unit can output a video signal at 120 Hz for 2D video output and 240 Hz for 3D video output. .

  As described above, the 2D / 3D video processing apparatus of the present invention includes a 2D / 3D detection unit that detects whether an input video signal is a 2D video signal or a 3D video signal, and the input video signal is a 2D video signal. And a three-dimensional video signal are used in common, and a two-dimensional output frame signal from the input video signal read from the frame memory based on a detection result of the 2D / 3D detection unit. Alternatively, the 2D / 3D frame generation processing unit that generates a 3D output frame signal and the 2D output frame signal generated by the 2D / 3D frame generation processing unit based on the detection result of the 2D / 3D detection unit or 3 The configuration includes a 2D / 3D output timing control unit that outputs a dimension output frame signal in a desired order and timing.

  Therefore, regardless of whether the input video signal is a two-dimensional video signal or a three-dimensional video signal, the input video signal is temporarily stored in a common frame memory, and then, based on the detection result of the 2D / 3D detection unit, A three-dimensional output frame signal is generated. As a result, it is possible to reduce the memory as compared with the conventional configuration in which circuits and memories for 2D video signal processing and 3D video signal processing are provided and processed.

1 is a diagram illustrating a basic configuration of a 2D / 3D video processing apparatus according to an embodiment of the present invention. It is a figure which shows one Example of the 2D / 3D frame production | generation part in the said 2D / 3D video processing apparatus. It is a figure which shows one Example of the 2D / 3D output timing control part in the said 2D / 3D video processing apparatus. It is a figure which shows the timing chart in case the input signal of the said 2D / 3D output timing control part is two-dimensional. It is a figure which shows the timing chart in case the input signal of the said 2D / 3D output timing control part is three-dimensional. It is a figure which shows the input-output data format of a three-dimensional television. It is a figure which shows the conventional 2D and 3D video signal processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing the basic configuration and signal processing flow of a 2D / 3D video processing apparatus (hereinafter, this processing apparatus) according to the present invention. As shown in FIG. 1, the processing apparatus includes a 2D / 3D detection unit 10, a 2D / 3D frame generation processing unit 20, and a 2D / 3D output timing control unit 30. In the video signal processing unit of FIG. 1, a case where a 60 Hz signal is input as an input video signal when the signal is a two-dimensional signal, and a 60 Hz signal is input in a side-by-side format when the signal is a three-dimensional signal. Show.

  The input video signal is input to the 2D / 3D detection unit 10 where it is detected whether or not it is a three-dimensional signal. Specifically, the input video signal includes a 2D / 3D flag indicating whether the input video signal is a two-dimensional video or a three-dimensional video specified by the HDMI standard, and the flag indicates that the input video signal is a three-dimensional video. Is a value indicating that the input video signal is a three-dimensional signal. In addition, when the input video signal does not include the 2D / 3D flag defined by the HDMI standard or the like, the feature when the input video signal is a three-dimensional video is extracted, so that the input video signal is 3 It can be determined that the image is a three-dimensional image. When the three-dimensional signal is in a side-by-side format as in the present embodiment, a feature of the side-by-side format, such as a strong correlation between the left image and the right image, By extracting, it is detected that the input video signal is a three-dimensional signal. When the 2D / 3D detection unit 10 detects that the input video signal is a three-dimensional signal, the 2D / 3D detection unit 10 outputs a value indicating that the input video signal is a three-dimensional signal. When the 2D / 3D detection unit 10 determines that the input video signal is not a three-dimensional video, the 2D / 3D detection unit 10 outputs a value indicating that the input video signal is a two-dimensional signal.

  Further, the input video signal is also input to the 2D / 3D frame generation processing unit 20. The 2D / 3D frame generation processing unit 20 performs frame generation processing according to the result of the 2D / 3D detection unit 10 determining whether the input video signal is a 2D video or a 3D video. That is, when the input video signal is determined to be a two-dimensional video, an original frame video signal and an interpolated frame video signal for performing double speed conversion processing are generated as a two-dimensional output frame signal. Output separately to the two signal lines.

  In addition, when the input video signal is determined to be a 3D video, a process of interpolating the resolution in the horizontal (line) direction with reference to the left half and the right half of the signal input in the side-by-side format And each signal is output separately to two signal lines. That is, a “left video signal” and a “right video signal” are generated as a three-dimensional output frame signal, and each signal is separately output to two signal lines.

  Two systems of signals output from the 2D / 3D frame generation processing unit 20 are output to the 2D / 3D output timing control unit 30. The 2D / 3D output timing control unit 30 controls the output timing of the two systems of signals according to the result of the 2D / 3D detection unit 10 determining whether the input video signal is a two-dimensional video or a three-dimensional video. That is, when the input video signal is determined to be a two-dimensional video, double-speed conversion processing is performed by alternately outputting the original frame video signal and the above-described interpolated frame video signal, and the double-speed video signal (120 Hz) is converted. Output. In addition, when the input video signal is determined to be a three-dimensional video, the “left video signal” and the “right video signal” interpolated with the horizontal resolution described above are adapted to the frame sequential method. That is, a stereoscopic video signal (240 Hz) is output by outputting in the order of “left video signal”, “left video signal”, “right video signal”, and “right video signal”.

  Next, the flow of signal processing in the above-described 2D and 3D video display processing will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an embodiment of the 2D / 3D frame generation processing unit 20 according to the present invention. As shown in FIG. 2, the 2D / 3D frame generation processing unit 20 includes a frame memory 21, a motion detection circuit (two-dimensional signal processing unit) 22, an interpolation frame generation circuit (two-dimensional signal processing unit) 23, and a left-side signal resolution. An interpolation circuit (three-dimensional signal processing unit) 24, a right-side signal resolution interpolation circuit (three-dimensional signal processing unit) 25, a first switch (output selection unit) 26, and a second switch (output selection unit) 27 are provided. Has been.

  First, a case where the input video signal is a two-dimensional video signal is shown. The input video signal is first supplied to the frame memory 21, and then supplied from the frame memory 21 to the motion detection circuit 22, the interpolation frame generation circuit 23, and the second switch 27. The motion detection circuit 22 detects image motion using the video signal supplied from the frame memory 21, and obtains a motion detection signal. This motion detection signal is supplied to the interpolation frame generation circuit 23. The interpolation frame generation circuit 23 generates an interpolation frame video signal using the video signal supplied from the frame memory 21 based on the motion detection signal. The interpolated frame video signal generated by the interpolated frame generation circuit 23 is supplied to the 2D input terminal of the first switch 26. The video signal supplied from the frame memory 21 to the second switch 27 is supplied to the 2D input terminal of the second switch 27.

  When the video signal is a 2D video signal, the 2D side input is selected in the first switch 26 and the second switch 27 based on the 2D / 3D detection signal supplied from the 2D / 3D detection unit 10. That is, the interpolation frame video signal generated by the interpolation frame generation circuit 23 is output from the Cre / L output of the first switch 26, and supplied from the frame memory 21 from the Org / R output of the second switch 27. The original video signal is output.

  Next, a case where the input video signal is a three-dimensional video signal will be described. The input video signal is first supplied to the frame memory 21, and is supplied from the frame memory 21 to the left signal resolution interpolation circuit 24 and the right signal resolution interpolation circuit 25. The left-side signal resolution interpolation circuit 24 refers to the left half of the video signal input in the side-by-side format and interpolates the resolution in the horizontal (line) direction to generate a “left-side video signal”. I do. An example of processing for interpolating the resolution in the horizontal direction is to obtain a weighted average of values of adjacent pixels and interpolate this value between adjacent pixels. The output of the left signal resolution interpolation circuit 24 is supplied to the 3D input terminal of the first switch 26. Similarly, the right signal resolution interpolation circuit 25 performs a process of interpolating pixels to generate a “right video signal”, and the output of the right signal resolution interpolation circuit 25 is supplied to the 3D input terminal of the second switch 27. Is done.

  When the video signal is a 3D video signal, the first switch 26 and the second switch 27 select the 3D side input based on the 2D / 3D detection signal supplied from the 2D / 3D detection unit 10. That is, the “left video signal” generated by the left signal resolution interpolation circuit 24 is output from the Cre / L output of the first switch 26, and the right signal signal is output from the Org / R output of the second switch 27. The “right video signal” generated by the resolution interpolation circuit 25 is output.

  As described above, the 2D / 3D frame generation processing unit 20 can use the frame memory 21 in common when the input video signal is a two-dimensional video and when the input video signal is a three-dimensional video.

  Next, the configuration and processing of the 2D / 3D output timing control unit 30 will be described. FIG. 3 is a diagram illustrating an example of the 2D / 3D output timing control unit 30. FIG. 4 is a timing chart when the input signal of the 2D / 3D output timing control unit 30 is two-dimensional. FIG. 5 is a timing chart when the input signal of the 2D / 3D output timing control unit 30 is three-dimensional.

  As shown in FIG. 3, the basic configuration of the 2D / 3D output timing control unit 30 includes flip-flops FF1 to FF3 (logic gate element units) and switches SW1 to SW3 (clock selection units). The Cre / L output of the 2D / 3D frame generation processing unit 20 is supplied to the D input terminal of the flip-flop FF1, and the clock signal selected by the switch SW1 is supplied to the CK input terminal. The Org / R output of the 2D / 3D frame generation processing unit 20 is supplied to the D input terminal of the flip-flop FF2, and the clock signal selected by the switch SW2 is supplied to the CK input terminal. Further, the output signal of either the flip-flop FF1 or FF2 is supplied to the D input terminal of the flip-flop FF3, and the clock signal selected by the switch SW3 is supplied to the CK input terminal.

  First, the case where the video signal is a two-dimensional video signal will be described with reference to FIGS. When the video signal is a two-dimensional video signal, the interpolated frame video signal is input to the D input terminal (FF1: D in FIG. 4) of the flip-flop FF1, and the D input terminal (FF2: D) of the flip-flop FF2 is input. The original video signal is input.

  Here, on the timing chart of FIG. 4, the original video signal is described as Org1, Org2, Org3,... In the order of input, and the interpolated frame video signal is Cre1, Cre2, Cre3,. It is described. The 2D / 3D output timing control unit 30 receives three types of clock signals, that is, Ck 60 Hz, Ck 120 Hz, and Ck 240 Hz.

  When the video signal is a two-dimensional video signal, Ck 60 Hz as an input clock is given to the CK input terminal (FF2: CK) of the flip-flop FF2 via the switch SW2. That is, the switch SW2 selects Ck 60 Hz input to one input terminal A based on the 2D / 3D detection signal. The original video signal Orgx is held at the rising edge of this clock signal by inputting a clock signal having the same phase as Ck60 Hz from the switch SW2 to the CK input terminal of the flip-flop FF2, and its output (FF2: Q ) Is applied to the D input terminal of the flip-flop FF3.

  On the other hand, the CK input terminal (FF1: CK) of the flip-flop FF1 is supplied with Ck 60 Hz, which is an input clock, via the logic inverting element and the switch SW1. That is, the switch SW1 selects the inverted clock of Ck 60 Hz input to one terminal A based on the 2D / 3D detection signal. The interpolated frame video signal Crex is held at the rising edge of the clock signal by inputting a clock signal having a phase opposite to that of Ck 60 Hz from the switch SW1 to the CK input terminal of the flip-flop FF1, and its output (FF1: Q ) Is applied to the D input terminal of the flip-flop FF3.

  Therefore, Org1, Cre1, Org2, Cre2,..., The original video signal and the interpolated frame video signal are alternately input to the D input terminal (FF3: D) of the flip-flop FF3. Furthermore, Ck 120 Hz, which is an input clock, is given to the CK input terminal (FF3: CK) of the flip-flop FF3 via the logic inversion element and the switch SW3. That is, the switch SW3 selects the inverted clock of Ck120Hz input to one terminal A based on the 2D / 3D detection signal. The flip-flop FF3 receives the clock signal having a phase opposite to that of Ck 120 Hz, holds the input data at the rising edge, and outputs (FF3: Q) as a double-speed video signal (120 Hz).

  Next, the case where the video signal is a three-dimensional video signal will be described with reference to FIGS. When the video signal is a three-dimensional video signal, the “left-side video signal” obtained by interpolating the horizontal resolution described above is input to the D input terminal (FF1: D in FIG. 5) of the flip-flop FF1. The “right-side video signal” obtained by interpolating the horizontal resolution described above is input to the D input terminal (FF2: D) of FF2.

  In the timing chart of FIG. 5, “left video signal” is described as L1, L2,... In the order of input, and “right video signal” is described as R1, R2,. ing.

  Here, a clock signal used for 3D video signal processing will be described. In the present embodiment, the following processing is performed on the input clock signal so as to conform to the frame sequential method required for displaying the three-dimensional video signal. Accordingly, a stereoscopic video signal (240 Hz) is output by outputting in the order of “left video signal”, “left video signal”, “right video signal”, and “right video signal”.

  Ck 60 Hz and Ck 240 Hz, which are input clocks, are applied to the input terminal B of the switch SW1 via a logical product element. At the time of 3D video signal processing, the switch SW1 selects the clock input to this terminal B based on the 2D / 3D detection signal. That is, when Ck60 Hz is at a high level, the logical product of Ck60 Hz and Ck240 Hz is supplied to the CK input terminal (FF1: CK) of FF1 so that the signal value of Ck240 Hz is effective as a clock operation.

  Accordingly, the flip-flop FF1 holds the “left video signal” input to the D input terminal at the rising edge of the clock signal input to the CK input terminal, and the output (FF1: Q) is D of the flip-flop FF3. Supplied to the input terminal.

  On the other hand, to the input terminal B of the switch SW2, an inverted clock of Ck 60 Hz and Ck 240 Hz, which are input clocks, are given via a logical product element. At the time of 3D video signal processing, the switch SW2 selects the clock input to this terminal B based on the 2D / 3D detection signal. That is, when Ck60 Hz is at a low level, the logical product of the inverted clock of Ck60 Hz and Ck240 Hz is supplied to the CK input terminal (FF2: CK) of FF2 so that the signal value of Ck240 Hz is valid as the clock operation.

  Thus, the flip-flop FF2 holds the “right video signal” input to the D input terminal at the rising edge of the clock signal input to the CK input terminal, and the output (FF2: Q) is D of the flip-flop FF3. Supplied to the input terminal.

  As a result, in the “left video signal” Lx, the data input to the flip-flop FF1 is held twice, and the data is given to the flip-flop FF3. Next, in the “right video signal” Rx, the data input to the flip-flop FF2 is held twice, and the data is given to the flip-flop FF3. Therefore, at the D input terminal (FF3: D) of the flip-flop FF3, the “left video signal” and the “right video signal” are set so as to be L1, L1, R1, R1, L2, L2,. Entered.

  The CK input terminal (FF3: CK) of the flip-flop FF3 is supplied with Ck 240 Hz as an input clock via a logic inversion element and a switch SW3. That is, the switch SW3 selects the inverted clock of Ck 240 Hz input to one terminal B based on the 2D / 3D detection signal. The flip-flop FF3 receives the clock signal having the opposite phase to Ck 240 Hz, holds the input data at the rising edge, and outputs (FF3: Q) as the stereoscopic video signal (240 Hz).

  As described above, the 2D / 3D output timing control unit 30 inputs the two-dimensional output frame signal or the three-dimensional output frame signal generated by the 2D / 3D frame generation processing unit 20 to the flip-flops FF1 to FF3. Then, by inputting the clock signal selected by the switches SW1 to SW3 based on the 2D / 3D detection signal to the logic gate element unit, the frame signal can be output in a desired order and timing. In this configuration, the flip-flops FF1 to FF3, which are logic gate element units, can be used in common in the case of the 2D video signal and the case of the 3D video signal, and the circuit configuration of the 2D / 3D output timing control unit 30 Can be simplified. In addition, the output for the 2D video signal is 120 Hz and the output for the 3D video signal is 240 Hz. By selecting the optimum clocks for each, the clock output that has been conventionally performed for both processes can be obtained. Since this is not performed, power consumption is reduced.

  In this way, the two-dimensional video signal processing unit and the three-dimensional video signal processing unit are not provided, but can be shared, thus eliminating the problem of high circuit / memory size / cost and power consumption. It becomes possible.

  A video display device can be configured by combining the present processing device and a display unit that displays an image corresponding to a frame signal output from the present processing device. In such a video display apparatus, the application of the present invention is suitable when the display unit is a liquid crystal panel. This is because the liquid crystal panel has a problem of moving image blurring because the response speed of the display element is slow, but moving image blurring can be eliminated by performing double speed conversion processing.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can reduce the circuit, memory size, cost, and power consumption in 2D / 3D video processing, and can be used for a 3D video apparatus or the like.

10 2D / 3D detection unit 20 2D / 3D frame generation processing unit 21 frame memory 22 motion detection circuit (two-dimensional signal processing unit)
23 Interpolation frame generation circuit (two-dimensional signal processing unit)
24 Resolution interpolation circuit for left side signal (3D signal processor)
25 Right-side signal resolution interpolation circuit (3D signal processor)
26 1st switch (output selection part)
27 Second switch (output selection unit)
30 2D / 3D output timing control unit FF1 to FF3 flip-flop (logic gate element unit)
SW1 to SW3 switch (clock selection part)

Claims (8)

A 2D / 3D detector that detects whether the input video signal is a 2D video signal or a 3D video signal;
The input video signal has a frame memory that is used in common when the input video signal is a 2D video signal and a 3D video signal, and is read from the frame memory based on the detection result of the 2D / 3D detection unit. A 2D / 3D frame generation processing unit for generating a two-dimensional output frame signal or a three-dimensional output frame signal from a video signal;
2D / 3D output timing for outputting the two-dimensional output frame signal or the three-dimensional output frame signal generated by the 2D / 3D frame generation processing unit in a desired order and timing based on the detection result of the 2D / 3D detection unit A two-dimensional / three-dimensional video processing apparatus characterized by comprising a control unit. The 2D / 3D output timing controller is
A logic gate element unit to which the 2D output frame signal or the 3D output frame signal generated by the 2D / 3D frame generation processing unit is input;
A clock selection unit for selecting a desired clock based on the detection result of the 2D / 3D detection unit,
The logic gate element unit outputs the two-dimensional output frame signal or the three-dimensional output frame signal in a desired order and timing according to a clock selected by the clock selection unit. The 2D / 3D image processing apparatus described.   The 2D / 3D detection unit detects whether the input video signal is a 2D video signal or a 3D video signal by detecting a 2D / 3D flag included in the input video signal, or extracts a feature of the input video signal. 3. The 2D / 3D video processing apparatus according to claim 1, wherein whether the input video signal is a 2D video signal or a 3D video signal is detected. The 2D / 3D frame generation processing unit
The frame memory;
A two-dimensional signal processing unit that generates a double-speed video signal as a two-dimensional output frame signal by performing double-speed processing on the two-dimensional video signal read from the frame memory;
A 3D signal processing unit that generates a stereoscopic video signal as a 3D output frame signal by performing a stereoscopic video signal generation process on the 3D video signal read from the frame memory;
Based on the detection result of the 2D / 3D detector, select and output one of the double-speed video signal generated by the two-dimensional signal processor and the stereoscopic video signal generated by the three-dimensional signal processor The 2D / 3D video processing apparatus according to claim 1, further comprising an output selection unit configured to perform the output selection.   5. The 2D / 3D output timing controller outputs video signals at different output timings depending on whether the input video signal is a 2D video signal or a 3D video signal. 2D / 3D image processing apparatus according to 1.   6. The 2D / 3D video processing apparatus according to claim 5, wherein the 2D / 3D output timing controller outputs a video signal at 120 Hz when outputting 2D video and 240 Hz when outputting 3D video. . A 2D / 3D image processing apparatus according to any one of claims 1 to 6;
A video display device comprising: a display unit that displays an image according to a frame signal output from the 2D / 3D video processing device.   The video display device according to claim 7, wherein the display unit is a liquid crystal panel.

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