JP2011215852A - Circuit verification device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit verification device and method, capable of verifying functions of a logical circuit including an asynchronous sequential circuit by more reliably assuming a metastable state.SOLUTION: A computer 2 for verifying functions of a logical circuit includes: a generation stage number calculation unit for calculating a generation stage number (c) of a metastable state value from an equation (1) based on a clock period Tdist of an asynchronous sequential circuit 201 and metastable convergence time Tmc of the first stage flip-flop circuit FF01 in the asynchronous sequential circuit 201; a sequential circuit specification part for specifying flip-flop circuits from the flip-flop circuit FF01 up to the n-th stage flip-flop circuit by analyzing a circuit design program; and a function simulation control unit for allowing the flip-flop circuits from the first up to n-th stage flip-flop circuit to output metastable state values by the number of clock cycles respectively equal to (generation stage number c-(n-1)) from the generation stage number c in function simulation.

Description

  The present invention relates to a circuit verification device and a circuit verification method, and more particularly to a circuit verification device and a circuit verification method for verifying an asynchronous circuit including a sequential circuit.

  At the time of circuit design, simulation is performed at the HDL (Hardware Description Language) level, the gate level, the transistor level, and the like, thereby verifying the function of the designed circuit. Hereinafter, the simulation performed for verifying the function of the circuit is referred to as function simulation.

  The circuit may include an asynchronous circuit. In an asynchronous sequential circuit having a plurality of clock signals, signal transfer may be performed between circuits operating with different clock signals. For example, an oscillation state output from a circuit that operates with one clock signal may propagate to an asynchronous sequential circuit or combination circuit that operates with another clock signal. In this case, the logic of the signal output from the sequential circuit in the previous stage is not determined. A state in which the logic of the output signal of the circuit is not determined in this way is called a metastable state. The fact that the sequential circuit is in the metastable state contributes to the abnormal operation of the logic circuit including the asynchronous sequential circuit.

Therefore, functional simulation is performed in consideration of the fact that the sequential circuit is in a metastable state at the HDL level.
For example, Patent Document 1 discloses an asynchronous circuit that performs a function simulation considering a metastable state by performing a process of outputting a signal stored in a storage unit as an output signal instead of a value indicating a metastable state. A verification method is described.

Patent No. 3953250

However, in the function simulation described in Patent Document 1, the value indicating the metastable state generated in the sequential circuit is an arbitrary time that does not exceed the cycle of the clock signal. For this reason, the functional simulation described in Patent Literature 1 can reproduce the metastable state that occurs in the preceding sequential circuit, but cannot reproduce the metastable state that occurs in the subsequent sequential circuit. .
Actually, if the sequential circuit in the previous stage is in the metastable state and the convergence time of the metastable state does not fall within one clock, the sequential circuit in the subsequent stage is also in the metastable state. Such a state cannot be reproduced by functional simulation.

The circuit verification apparatus according to the first aspect of the present invention is an apparatus for verifying the function of a logic circuit. The circuit verification device includes a generation stage number calculation unit, a sequential circuit identification unit, and a function simulation control unit. The generation stage number calculation unit is based on the clock cycle Tdist of the asynchronous sequential circuit included in the logic circuit and the metastable convergence time Tmc of the first sequential circuit of the asynchronous sequential circuit (1 ) To calculate the generation stage number c of the metastable state value. In addition, the sequential circuit specifying unit analyzes the circuit design program of the logic circuit described in a predetermined program language, so that the output of the sequential circuit of the first stage is output from the sequential circuit of the first stage. Up to the n-th sequential circuit (n is an integer satisfying n ≧ 2) connected to the side. In the functional simulation of the logic circuit, the function simulation control unit changes the number of generation stages c to the sequential circuits from the first stage to the n-th stage (the generation stage number c− (n−1)). The metastable state value is output for the number of clock cycles equal to.
c = int (Tmc / Tdist) +1 (1)

  In the first aspect of the present invention, in the asynchronous sequential circuit, the sequential circuit of the first stage is in a clock cycle equal to the number of generated stages c,..., The sequential circuit of the nth stage is (the number of generated stages c− (n− Output metastable state value during clock cycle equal to 1)). Therefore, in the asynchronous sequential circuit, it is possible to surely simulate the metastable state that occurs in the second and subsequent sequential circuits. Therefore, it is possible to verify the function of the logic circuit including the asynchronous sequential circuit by assuming the metastable state more reliably.

The circuit verification method according to the second aspect of the present invention is a method for verifying the function of a logic circuit. The circuit verification method is a method in which a computer executes a generation stage number calculation process, a sequential circuit identification process, and a function simulation control process. In the generation stage number calculation process, the computer, based on the clock cycle Tdist of the asynchronous sequential circuit included in the logic circuit and the metastable convergence time Tmc of the first sequential circuit of the asynchronous sequential circuit, The number of generation stages c of metastable state values is calculated by the following equation (1). In the sequential circuit specifying process, the computer analyzes the logic circuit circuit design program described in a predetermined program language, so that the first-stage sequential circuit is changed to the first-stage sequential circuit. Up to the nth stage (n is an integer satisfying n ≧ 2) sequential circuits connected to the output side of the sequential circuit are specified. In the functional simulation control process, the computer transfers the first to n-th sequential circuits from the generation stage number c (the generation stage number c− (n The metastable state value is output for the number of clock cycles equal to -1)).
c = int (Tmc / Tdist) +1 (1)

  In the second aspect of the present invention, in the asynchronous sequential circuit, the sequential circuit of the first stage is in a clock cycle equal to the number of generation stages c,..., The sequential circuit of the nth stage is (number of generation stages c− (n− Output metastable state value during clock cycle equal to 1)). Therefore, in the asynchronous sequential circuit, it is possible to surely simulate the metastable state that occurs in the second and subsequent sequential circuits. Therefore, it is possible to verify the function of the logic circuit including the asynchronous sequential circuit by assuming the metastable state more reliably.

  According to the present invention, it is possible to verify the function of a logic circuit including an asynchronous sequential circuit by more reliably assuming a metastable state.

It is a block diagram which shows an example of a structure of the circuit verification system which concerns on Embodiment 1 of this invention. It is a flowchart explaining the circuit verification method in the computer which concerns on Embodiment 1 of this invention. It is a figure which shows FF table which concerns on Embodiment 1 of this invention. It is a flowchart explaining the identification method of the sequential circuit in the circuit verification method which concerns on Embodiment 1 of this invention. It is a flowchart explaining the function simulation in the circuit verification method which concerns on Embodiment 1 of this invention. It is a flowchart explaining the function simulation in the circuit verification method which concerns on Embodiment 1 of this invention. It is a figure which shows an example of an asynchronous circuit. It is a timing chart explaining the functional simulation in the circuit verification method which concerns on Embodiment 1 of this invention. It is a flowchart explaining the function simulation in the circuit verification method which concerns on Embodiment 2 of this invention. It is a timing chart explaining the functional simulation in the circuit verification method which concerns on Embodiment 2 of this invention.

Hereinafter, embodiments to which the present invention can be applied will be described. Note that the present invention is not limited to the following embodiments.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing an example of the configuration of a circuit verification system 100 according to Embodiment 1 of the present invention.
As shown in FIG. 1, the circuit verification system 100 includes a server 1, computers 2,. The server 1 and the computer 2 (circuit verification device),... Are communicably connected via the network 3.
The server 1 also includes a recording medium 10. The recording medium 10 stores a CAD design tool such as a simulation program.
The recording medium 10 stores constants and variables such as a clock cycle Tdist, a metastable convergence time Tmc, and a variable c (described later).
Here, the metastable convergence time Tmc indicates that the signal output from the circuit operating with one clock signal is input, and the first sequential circuit of the asynchronous sequential circuit operating with another clock signal is in the metastable state. Is the time until the output of the sequential circuit in the first stage is stabilized.
The clock cycle Tdist is a clock cycle of an asynchronous sequential circuit that operates with another clock signal to which a signal output from a circuit that operates with one clock signal is input.
The variable c is the number of generation stages of the metastable state value Dm. Further, the metastable state value Dm is a value of a signal output from the sequential circuit in the metastable state.
The metastable convergence time Tmc and the clock cycle Tdist are values determined based on empirical rules.

The computer 2 is an engineer workstation or the like. The computer 2 includes, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), and the like. In FIG. 1, the CPU, RAM, and ROM are not shown.
The ROM (storage unit) stores various programs and various data for controlling each unit of the computer 2. The CPU executes various programs stored in the ROM and develops them in the RAM, thereby controlling each part of the computer 2.
For example, the CPU executes various programs stored in the ROM so that the CAD design tool, clock cycle Tdist, metastable convergence time Tmc, variable stored in the recording medium 10 of the server 1 via the network 3 Acquire constants such as c, variables, etc., and store them in ROM. The ROM stores an FF table 4 (described later) generated by the CPU.
Further, the CPU performs circuit verification by executing a CAD design tool stored in the ROM. For example, the CPU functions as a generation stage number calculation unit, a sequential circuit identification unit, a function simulation control unit, an FF table storage control unit, and the like by executing a CAD design tool stored in the ROM.

  The configuration of the computer 2 is not limited to the above. For example, the above-described various programs may be stored in various types of non-transitory computer readable media (non-transitory computer readable media). For example, the various programs include a magnetic recording medium (for example, a flexible disk, a magnetic tape, a hard disk drive), a magneto-optical recording medium (for example, a magneto-optical disk), a CD-ROM, a CD-R, a CD-R / W, a semiconductor memory ( For example, it may be stored in a mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM) or the like.

Next, a circuit verification method in the computer 2 according to Embodiment 1 of the present invention will be described with reference to the flowchart shown in FIG.
First, the computer 2 analyzes a description at an RTL (Register Transfer Level) or a netlist level, and identifies a sequential circuit related to asynchronous transfer (step S1).

Specifically, the computer 2 creates the FF table 4 shown in FIG. 3 and stores it in the ROM. The FF table 4 is information in which an instance name 41 of a sequential circuit that is in a metastable state is associated with a clock cycle number Cmeta42 that represents a time during which the metastable state continues.
The computer 2 specifies a sequential circuit that is in a metastable state based on the metastable convergence time Tmc and the clock cycle Tdist. In other words, the computer 2 specifies the first sequential circuit of the asynchronous sequential circuit that operates on the other clock signal to which the signal output from the circuit that operates on the one clock signal is input. Then, the instance name of the identified sequential circuit is stored in the instance name 41 of the FF table 4.
Further, the computer 2 determines the clock cycle number Cmeta based on the metastable convergence time Tmc and the clock cycle Tdist, and stores it in the clock cycle number Cmeta42 of the FF table 4.
Further, the computer 2 newly adds the nth stage (n is an integer satisfying n ≧ 2) of the sequential circuit connected to the output side (the rear stage side) of the first stage sequential circuit specified above. Identify. Then, the newly identified instance name of the nth sequential circuit and the clock cycle number Cmeta are associated with each other and stored in the FF table 4.

Next, the computer 2 performs pre-simulation processing (step S2).
Specifically, the computer 2 assigns an operation flow for simulation to the sequential circuit specified in step S1. More specifically, an operation flow shown in the flowchart of FIG. 5 to be described later is assigned to circuits other than the sequential circuit specified in step S1. Further, the operation flow shown in the flowchart of FIG. 6 is assigned to the sequential circuit specified in step S1. For example, for a circuit other than the sequential circuit identified in step S1, the flag for assigning the operation flow shown in the flowchart of FIG. 5 is ON, and for the sequential circuit identified in step S1, the flowchart of FIG. A flow assignment flag is determined for each circuit so that the indicated operation flow assignment flag is ON (not shown).

  Next, the computer 2 performs a function simulation of each circuit according to the operation flow assigned in step S2 (step S3; function simulation control process). Here, the function simulation is a simulation performed to verify the function of the circuit. Specifically, the computer 2 executes a circuit design program described in RTL or a netlist to virtually operate the circuit represented by the circuit design program, and from the operation result obtained, Verify circuit functionality.

Next, the sequential circuit specifying method in step S1 of FIG. 2 will be described with reference to the flowchart shown in FIG.
First, the computer 2 calculates the generation stage number c of the metastable state value Dm using the following equation (1) (step S101; generation stage number calculation process).
c = int (Tmc / Tdist) +1 (1)

  Next, the computer 2 specifies a sequential circuit that is in a metastable state. In other words, the computer 2 specifies the first sequential circuit of the asynchronous sequential circuit that operates on the other clock signal to which the signal output from the circuit that operates on the one clock signal is input (step S102). ; Sequential circuit identification processing).

  Next, the computer 2 associates the instance name of the sequential circuit in the first stage identified in step S102 with the generation stage number c (number of clock cycles) obtained from the expression (1) and stores it in the FF table 4. (Step S103; FF table storage control process). Here, the generation stage number c is stored in the FF table 4 as the number of clock cycles.

Next, the computer 2 determines whether or not the number of generation stages c obtained in step S101 is 1 or less (step S104).
In step S104, when the number of generation stages c is 1 or less (step S104; Yes), this process ends.
In step S104, when the generation stage number c is larger than 1 (step S104; No), n−1 (n is an integer satisfying n ≧ 2) is subtracted from the generation stage number c (step S105).

  Next, the computer 2 selects the n-th sequential circuit (n is an integer satisfying n ≧ 2) connected to the output side (rear-stage side) of the first sequential circuit identified in step S102. New identification (step S106; sequential circuit identification process).

  Next, the computer 2 associates the instance name of the n-th sequential circuit identified in step S106 with the number of generation stages (c− (n−1)) calculated in step S105, and stores them in the FF table 4. Store (step S107; FF table storage control process), and return to step S104. In other words, the computer 2 stores the number of generation stages (c− (n−1)) calculated in step S105 in the FF table 4 as the number of clock cycles of the nth sequential circuit specified in step S106. .

  Next, an operation flow assigned to a circuit other than the sequential circuit specified in the process of step S1 of FIG. 2, that is, the process shown in FIG. In other words, the function simulation performed in step S3 of FIG. 2 for a circuit other than the sequential circuit specified in step S1 of FIG. 2 will be described with reference to the flowchart shown in FIG. Here, a flip-flop circuit will be described as an example of a circuit other than the sequential circuit specified in step S1 of FIG.

First, the flip-flop circuit determines whether or not an active edge of the input clock signal has been detected (step S201).
In step S201, when the flip-flop circuit does not detect the active edge of the input clock signal (step S201; No), the process proceeds to step S203.
In step S201, when the flip-flop circuit detects an active edge of the input clock signal (step S201; Yes), the flip-flop circuit holds the input signal (step S202).

  Next, the flip-flop circuit outputs the held signal (step S203).

Next, the operation flow assigned to the sequential circuit specified in step S1 of FIG. 2, that is, the process shown in FIG. 4, will be described with reference to the flowchart shown in FIG. In other words, the function simulation performed in step S3 of FIG. 2 for the sequential circuit specified in step S1 of FIG. 2 will be described with reference to the flowchart shown in FIG.
Note that the processing of each step shown in FIG. 6 does not exceed the period of the clock signal input to all the sequential circuits, and within a predetermined time (between simulation cycles 1 and 2,... (M is a natural number)). Further, the number of generation stages c, the values held by each sequential circuit, and various flags are unique values for each sequential circuit, and are stored in a local hard disk or memory such as a ROM of the computer 2 and retained at least during function simulation. It is what is done.

First, the sequential circuit determines whether or not an active edge of the input clock signal has been detected (step S301).
In step S301, when the sequential circuit detects an active edge of the input clock signal (step S301; Yes), the computer 2 refers to the FF table 4 and the number of clock cycles corresponding to the instance name of the sequential circuit. It is determined whether (generation stage number c) is greater than 0 (step S302).

In step S302, when the number of clock cycles (number of generation stages c) is greater than 0 (step S302; Yes), the computer 2 subtracts 1 from the number of clock cycles (number of generation stages c) (step S303).
In step S302, when the number of clock cycles (number of generation stages c) is 0 or less (step S302; No), the computer 2 determines whether there is a change in the value of the signal input to the sequential circuit (step S302). S304).

If there is no change in the value of the signal input to the sequential circuit in step S304 (step S304; No), the computer 2 determines whether or not the number of clock cycles (number of generation stages c) is zero. Then, it is determined whether or not the sequential circuit is in a metastable state (step S305).
If the number of clock cycles (number of generation stages c) is not 0 in step S305, that is, if the sequential circuit is in a metastable state (step S305; No), the process proceeds to step S308.
If the number of clock cycles (number of generation stages c) is 0 in step S305, that is, if the sequential circuit is not in the metastable state (step S305; Yes), the process proceeds to step S312.

  In step S304, when there is a change in the value of the signal input to the sequential circuit (step S304; Yes), the computer 2 refers to the FF table 4 and generates the number of clock cycles corresponding to the instance name of the sequential circuit (generation The number of stages c) is set as the value of the metastable counter (step S306). The CPU of the computer 2 functions as a metastable counter by executing a metastable counter program stored in the ROM.

  Next, the sequential circuit holds the value of the input signal (step S307).

  Next, the computer 2 generates the metastable state value Dm of the sequential circuit and stores it in the ROM, and the sequential circuit holds the metastable state value Dm (step S308). Here, the metastable state value Dm is a random value and is different from the value held in step S307.

  Next, the sequential circuit outputs the metastable state value Dm held in step S308 (step S309).

  On the other hand, when the sequential circuit does not detect the active edge of the input clock signal in step S301 (step S301; No), the computer 2 refers to the FF table 4 and corresponds to the instance name of the sequential circuit. It is determined whether or not the sequential circuit is in a metastable state by determining whether or not the number of clock cycles to be performed (number of generation stages c) is 0 (step S310).

In step S310, when the number of clock cycles (number of generation stages c) is 0, that is, when the sequential circuit is not in a metastable state (step S310; Yes), the sequential circuit outputs a held signal. (Step S312).
In step S310, when the number of clock cycles (number of generation stages c) is not 0, that is, when the sequential circuit is in the metastable state (step S310; No), the computer 2 sets the metastable state value Dm of the sequential circuit. While generating and storing in ROM, the said sequential circuit hold | maintains the said metastable state value Dm. Next, the sequential circuit outputs the held metastable state value Dm (step S311).

Next, taking the asynchronous circuit 200 shown in FIG. 7 as an example, a circuit verification method in the computer 2 according to the first embodiment of the present invention will be described.
The asynchronous circuit 200 shown in FIG. 7 includes a flip-flop circuit FF01 that operates by one clock signal CLK1, an asynchronous sequential circuit 201 that operates by another clock signal CLK2, and a combinational circuit CC2.
The asynchronous sequential circuit 201 includes three flip-flop circuits FF02, FF03, and FF04. The signal Q01 output from the flip-flop circuit FF01 is input to the input terminal of the flip-flop circuit FF02. The signal Q02 output from the flip-flop circuit FF02 is input to the input terminal of the flip-flop circuit FF03. The signal Q03 output from the flip-flop circuit FF03 is input to the input terminal of the flip-flop circuit FF04. The signal Q04 output from the flip-flop circuit FF04 is input to the combinational circuit CC2. The input signal DIN1 is input to the input terminal of the flip-flop circuit FF01.

FIG. 8 is a timing chart when the asynchronous circuit 200 shown in FIG. 7 is verified by the computer 2 according to the first embodiment of the present invention.
In FIG. 8, the clock cycle Tdist of the asynchronous sequential circuit 201 is 10 ns, the metastable convergence time Tmc is 6 ns, and the instance names of the flip-flop circuits FF01, FF02, FF03, and FF04 are “FF01”, “FF02”, “FF03”, respectively. It is assumed that “FF04”. Assume that nothing is registered in the FF table 4 in the initial state.

  First, in step SS101 of FIG. 4, the computer 2 calculates the generation stage number c of the metastable state value Dm by the equation (1). Since c = int (6/10) + 1 = 2, the value of the generation stage number c is 2.

  Next, in step S102, the computer 2 receives a signal output from a circuit that operates with one clock signal, and receives a flip-flop as a first-stage sequential circuit of an asynchronous sequential circuit that operates with another clock signal. Specify the circuit FF02.

  Next, in step S103, the computer 2 associates the identified instance name “FF02” of the flip-flop circuit FF02 with the value “2” of the generation stage number c (number of clock cycles) and stores it in the FF table 4. .

  Next, in step S104, the computer 2 determines that the generation stage number c is 1 or more (step S104; No), and in step S105, the computer 2 subtracts 1 from the generation stage number c.

  Next, in step S106, the computer 2 newly specifies the flip-flop circuit FF03 connected to the output side (rear stage side) of the flip-flop circuit FF02 specified in step S102 as the second-stage sequential circuit.

  Next, in step S107, the computer 2 associates the instance name “FF03” of the flip-flop circuit FF03 identified in step S106 with the value “1” of the generation stage number (c−1) calculated in step S105. , Stored in the FF table 4, and the process returns to step S104.

  Next, in step S104, the computer 2 determines that the number of generation stages (c-1) is 1 (step S104; Yes), and ends this process.

Next, in step S2 of FIG. 2, the computer 2 performs a pre-simulation process.
Specifically, the operation flow shown in the flowchart of FIG. 5 is assigned to the flip-flop circuits FF01 and FF04 whose instance names are not registered in the FF table 4. Also, the operation flow shown in the flowchart of FIG. 6 is assigned to the flip-flop circuits FF02 and FF03 whose instance names are registered in the FF table 4.

Next, in step S3 of FIG. 2, the computer 2 performs a function simulation of each circuit according to the operation flow assigned in step S2.
Hereinafter, the function simulation in step S3 in FIG. 2 will be specifically described with reference to the timing chart shown in FIG.
Numbers “1” to “26” described in the upper part of FIG. 8 indicate simulation cycles. In the simulation cycle 0 in the initial state, the values of the clock signals CLK1 and CLK2 are “0”, the value of the input signal DIN is “0”, and the values held by the flip-flop circuits FF01, FF02, FF03, and FF04 are It is assumed that “0” and the value of the generation stage number c is “0”. The function simulation is performed in the order of the flip-flop circuit FF04, the flip-flop circuit FF03, the flip-flop circuit FF02, and the flip-flop circuit FF01.

<About simulation cycles 0 to 1>
(About flip-flop circuit FF04)
In the simulation cycles 0 to 1, the clock signal CLK2 becomes an active edge (Step S201; Yes, Step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “0” of the signal Q03 in step S202 of FIG. 5, and outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), in step S304, the computer 2 sets the value “0” of the signal Q02 input to the flip-flop circuit FF03. The stored value “0” is compared, and it is determined that there is no change in the value of the signal input to the flip-flop circuit FF03 (step S304; No).
Next, in step S305, the computer 2 determines whether or not the flip-flop circuit FF03 is in a metastable state by determining whether or not the number of clock cycles (number of generation stages c) is 0. . Since the number of clock cycles of the flip-flop circuit FF03 is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “0” as the signal Q03, and holds the value “0” of the signal Q02.

(About the flip-flop circuit FF02)
Also in the case of the flip-flop circuit FF02, as in the flip-flop circuit FF03, the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), and the signal input to the flip-flop circuit FF02 Since there is no change in the value of (No at step S304), the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “0” as the signal Q02 and also holds the value “0” of the signal Q01.

(About flip-flop circuit FF01)
Further, in the simulation cycles 0 to 1, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “0” as the signal Q01.

<About simulation cycles 2-3>
(About flip-flop circuit FF04)
In the simulation cycles 2 to 3, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (the number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “0” as the signal Q03.

(About the flip-flop circuit FF02)
Also in the case of the flip-flop circuit FF02, the value of the number of clock cycles (number of generation stages c) is “0” as in the flip-flop circuit FF03, and therefore the computer 2 indicates that the flip-flop circuit FF02 is not in the metastable state. (Step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “0” as the signal Q02.

(About flip-flop circuit FF01)
Further, in the simulation cycles 2 to 3, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “0” as the signal Q01.

<About simulation cycle 4>
(About flip-flop circuit FF04)
In the simulation cycle 4, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (the number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “0” as the signal Q03.

(About the flip-flop circuit FF02)
Also in the case of the flip-flop circuit FF02, the value of the number of clock cycles (number of generation stages c) is “0” as in the flip-flop circuit FF03, and therefore the computer 2 indicates that the flip-flop circuit FF02 is not in the metastable state. (Step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “0” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 4, the clock signal CLK1 becomes an active edge (step S201; Yes).
Therefore, the flip-flop circuit FF01 holds the value “7” of the input signal DIN in step S202 of FIG. 5 and outputs the value “7” held in step S203 of FIG. 5 as the signal Q01.

<About simulation cycle 5>
(About flip-flop circuit FF04)
In the simulation cycle 5, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “0” of the signal Q03 in step S202 of FIG. 5, and outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Since the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No) and the value of the signal input to the flip-flop circuit FF03 is not changed (step S304; No), the clock cycle Since the number (the number of generation stages c) is 0, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “0” as the signal Q03, and holds the value “0” of the signal Q02.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), in step S304, the computer 2 sets the value “7” of the signal Q01 input to the flip-flop circuit FF02. The stored value “0” is compared, and it is determined that there is a change in the value of the signal input to the flip-flop circuit FF03 (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “2” of the number of clock cycles (number of generated stages c) corresponding to the instance name “FF02” of the FF table 4 as the value of the metastable counter.
In step 307 in FIG. 6, the flip-flop circuit FF02 holds the value “7” of the input signal Q01.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF02 and stores it in the ROM, and the flip-flop circuit FF02 holds the metastable state value Dm. Here, the metastable state value Dm is a random value and is different from the value “7” held in step S307. Here, it is assumed that the computer 2 has generated “5” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF02 outputs the value “5” that is the metastable state value Dm held in step S308 as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 5, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycles 6-8>
(About flip-flop circuit FF04)
In simulation cycles 6 to 8, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (the number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “0” as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “2”, the computer 2 determines that the flip-flop circuit FF02 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF02 outputs the value “5” that is the metastable state value Dm as the signal Q02.

(About flip-flop circuit FF01)
In simulation cycles 6 to 8, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycle 9>
(About flip-flop circuit FF04)
In the simulation cycle 9, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “0” of the signal Q03 in step S202 of FIG. 5, and outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), in step S304, the computer 2 sets the value “5” of the signal Q02 input to the flip-flop circuit FF03. The stored value “0” is compared, and it is determined that there is a change in the value of the signal input to the flip-flop circuit FF03 (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “1” of the number of clock cycles (number of generation stages (c−1)) corresponding to the instance name “FF03” of the FF table 4 as the value of the metastable counter. To do.
In step 307 in FIG. 6, the flip-flop circuit FF03 holds the value “5” of the input signal Q02.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF03 and stores it in the ROM, and the flip-flop circuit FF03 holds the metastable state value Dm. Here, the metastable state value Dm is a random value and is different from the value “5” held in step S307. Here, it is assumed that the computer 2 has generated “2” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF03 outputs the value “2” that is the metastable state value Dm held in step S308 as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “2” (step S302; Yes), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles is “1”.
Next, since the value of the signal Q01 input to the flip-flop circuit FF02 is “7” and the value held by the flip-flop circuit FF02 is also “7”, the computer 2 inputs to the flip-flop circuit FF02. It is determined that there is no change in the value of the signal Q01 (step S304; No).
Next, since the number of clock cycles (the number of generation stages c) of the flip-flop circuit FF02 is “1”, the computer 2 determines that the flip-flop circuit FF02 is in the metastable state (step S305; No).
Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF02 and stores it in the ROM, and the flip-flop circuit FF02 holds the metastable state value Dm. Here, it is assumed that the computer 2 has generated “1” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF02 outputs the value “1” that is the metastable state value Dm held in step S308 as a signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 9, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycles 10-12>
(About flip-flop circuit FF04)
In the simulation cycles 10 to 12, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “0” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF03 outputs the value “2” that is the metastable state value Dm as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF02 is in a metastable state (step S310; No).
In step S311 of FIG. 6, the flip-flop circuit FF02 outputs the value “1” that is the metastable state value Dm as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycles 10 to 12, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycle 13>
(About flip-flop circuit FF04)
In the simulation cycle 13, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “2” of the signal Q03 in step S202 of FIG. 5, and outputs the value “2” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1” (step S302; Yes), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles becomes “0”.
Next, since the value of the signal Q02 input to the flip-flop circuit FF03 is “1” and the value held by the flip-flop circuit FF03 is “5”, the computer 2 inputs to the flip-flop circuit FF03. It is determined that there is a change in the value of the signal Q02 to be performed (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “1” of the number of clock cycles (number of generation stages (c−1)) corresponding to the instance name “FF03” of the FF table 4 as the value of the metastable counter. To do.
In step 307 in FIG. 6, the flip-flop circuit FF03 holds the value “1” of the input signal Q02.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF03 and stores it in the ROM, and the flip-flop circuit FF03 holds the metastable state value Dm. Here, it is assumed that the computer 2 generates “4” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF03 outputs the value “4”, which is the metastable state value Dm held in step S308, as a signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “1” (step S302; Yes), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles becomes “0”.
Next, since the value of the signal Q01 input to the flip-flop circuit FF02 is “7” and the value held by the flip-flop circuit FF02 is also “7”, the computer 2 inputs to the flip-flop circuit FF02. It is determined that there is no change in the value of the signal Q01 (step S304; No).
Next, since the number of clock cycles (number of generation stages c) of the flip-flop circuit FF02 is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 13, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycles 14 to 16>
(About flip-flop circuit FF04)
In simulation cycles 14 to 16, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “2” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF03 outputs the value “4” that is the metastable state value Dm as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycles 10 to 12, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycle 17>
(About flip-flop circuit FF04)
In the simulation cycle 17, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “4” of the signal Q03 in step S202 of FIG. 5, and outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1” (step S302; Yes), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles becomes “0”.
Next, since the value of the signal Q02 input to the flip-flop circuit FF03 is “7” and the value held by the flip-flop circuit FF03 is “4”, the computer 2 inputs to the flip-flop circuit FF03. It is determined that there is a change in the value of the signal Q02 to be performed (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “1” of the number of clock cycles (number of generation stages (c−1)) corresponding to the instance name “FF03” of the FF table 4 as the value of the metastable counter. To do.
In step 307 in FIG. 6, the flip-flop circuit FF03 holds the value “7” of the input signal Q02.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF03 and stores it in the ROM, and the flip-flop circuit FF03 holds the metastable state value Dm. Here, it is assumed that the computer 2 generates “6” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF03 outputs the value “6” that is the metastable state value Dm held in step S308 as the signal Q03.

(About the flip-flop circuit FF02)
Further, the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), the value of the signal Q01 input to the flip-flop circuit FF02 is “7”, and the flip-flop circuit FF02 holds the value. Since the value being “7” is also “7”, the computer 2 determines that there is no change in the value of the signal Q01 input to the flip-flop circuit FF02 (step S304; No).
Next, since the number of clock cycles (number of generation stages c) of the flip-flop circuit FF02 is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 17, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycle 18>
(About flip-flop circuit FF04)
In the simulation cycle 18, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF03 outputs the value “6” that is the metastable state value Dm as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 18, the clock signal CLK1 becomes an active edge (step S201; Yes).
Therefore, the flip-flop circuit FF01 holds the value “3” of the input signal DIN in step S202 of FIG. 5 and outputs the value “3” held in step S203 of FIG. 5 as the signal Q01.

<About simulation cycles 19-20>
(About flip-flop circuit FF04)
In the simulation cycles 19 to 20, the clock signal CLK2 does not become an active edge (Step S201; No, Step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF03 outputs the value “6” that is the metastable state value Dm as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycles 19 to 20, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

<About simulation cycle 21>
(About flip-flop circuit FF04)
In the simulation cycle 21, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “6” of the signal Q03 in step S202 of FIG. 5, and outputs the value “6” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1” (step S302; Yes), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles becomes “0”.
Next, since the value of the signal Q02 input to the flip-flop circuit FF03 is “7” and the value held by the flip-flop circuit FF03 is also “7”, the computer 2 inputs to the flip-flop circuit FF03. It is determined that there is no change in the value of the signal Q02 to be performed (step S304; No).
Next, since the number of clock cycles (number of generation stages c) of the flip-flop circuit FF03 is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S305; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.

(About the flip-flop circuit FF02)
In addition, the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), the value of the signal Q01 input to the flip-flop circuit FF02 is “3”, and the flip-flop circuit FF02 holds the value. Since the current value is “7”, the computer 2 determines that there is a change in the value of the signal Q01 input to the flip-flop circuit FF02 (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “2” of the number of clock cycles (number of generated stages c) corresponding to the instance name “FF02” of the FF table 4 as the value of the metastable counter.
In step 307 in FIG. 6, the flip-flop circuit FF02 holds the value “3” of the input signal Q01.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF02 and stores it in the ROM, and the flip-flop circuit FF02 holds the metastable state value Dm. Here, it is assumed that the computer 2 generates “6” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF02 outputs the value “6” that is the metastable state value Dm held in step S308 as the signal Q01.

(About flip-flop circuit FF01)
In the simulation cycle 21, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

<About simulation cycles 22 to 24>
(About flip-flop circuit FF04)
In the simulation cycles 22 to 24, the clock signal CLK2 does not become an active edge (Step S201; No, Step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “6” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (the number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S310; Yes).
In step S312 of FIG. 6, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “2”, the computer 2 determines that the flip-flop circuit FF02 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF02 outputs the value “6” that is the metastable state value Dm as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycles 22 to 24, the clock signal CLK1 does not become an active edge (Step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

<About simulation cycle 25>
(About flip-flop circuit FF04)
In the simulation cycle 25, the clock signal CLK2 becomes an active edge (step S201; Yes, step S301; Yes).
Therefore, the flip-flop circuit FF04 holds the value “7” of the signal Q03 in step S202 of FIG. 5, and outputs the value “7” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, the value of the number of clock cycles (number of generation stages c) is “0” (step S302; No), the value of the signal Q02 input to the flip-flop circuit FF03 is “1”, and the flip-flop circuit FF03 holds the value. Since the current value is “5”, the computer 2 determines that there is a change in the value of the signal Q02 input to the flip-flop circuit FF03 (step S304; Yes).
Next, in step S306, the computer 2 newly sets the value “1” of the number of clock cycles (number of generation stages (c−1)) corresponding to the instance name “FF03” of the FF table 4 as the value of the metastable counter. To do.
In step 307 in FIG. 6, the flip-flop circuit FF03 holds the value “1” of the input signal Q02.

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF03 and stores it in the ROM, and the flip-flop circuit FF02 holds the metastable state value Dm. Here, it is assumed that the computer 2 has generated “5” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF03 outputs the value “5” that is the metastable state value Dm held in step S308 as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “2” (step S302; No), in step S303, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles is “1”.
Next, since the value of the signal Q01 input to the flip-flop circuit FF02 is “3” and the value held by the flip-flop circuit FF02 is “3”, the computer 2 inputs the signal to the flip-flop circuit FF02. It is determined that there is no change in the value of the signal Q01 (step S304; No).
Next, since the number of clock cycles (the number of generation stages c) of the flip-flop circuit FF02 is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (step S305; No).

Next, in step S308, the computer 2 generates the metastable state value Dm of the flip-flop circuit FF02 and stores it in the ROM, and the flip-flop circuit FF02 holds the metastable state value Dm. Here, it is assumed that the computer 2 has generated “1” as the metastable state value Dm.
Next, in step S309, the flip-flop circuit FF02 outputs the value “1” that is the metastable state value Dm held in step S308 as a signal Q02.

(About flip-flop circuit FF01)
In the simulation cycle 25, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

<About the simulation cycle 26>
(About flip-flop circuit FF04)
In the simulation cycle 26, the clock signal CLK2 does not become an active edge (step S201; No, step S301; No).
Therefore, the flip-flop circuit FF04 outputs the value “7” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF03 is in a metastable state (No in step S310).
In step S311 of FIG. 6, the flip-flop circuit FF03 outputs the value “5” that is the metastable state value Dm as the signal Q03.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “1”, the computer 2 determines that the flip-flop circuit FF02 is in a metastable state (step S310; No).
In step S311 of FIG. 6, the flip-flop circuit FF02 outputs the value “1” that is the metastable state value Dm as the signal Q02.

(About flip-flop circuit FF01)
In the simulation cycles 22 to 24, the clock signal CLK1 does not become an active edge (Step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

  As described above, in the functional simulation of the flip-flop circuit FF04, the metastable state output by the flip-flop circuit FF03 is held during the simulation cycles 13 to 16, 17 to 20, and 21 to 24, and the held metastable is held. The status values are all different values. In the function simulation of the flip-flop circuit FF03, the metastable state output by the flip-flop circuit FF02 is held during the simulation cycles 9 to 12, 13 to 16, 17 to 20, and 21 to 24, and the held metastable state is retained. All values are different.

  Specifically, in the asynchronous sequential circuit 201 to which a signal is input from the flip-flop circuit FF01 operating with the clock signal CLK1, the first-stage flip-flop circuit FF02 has a second-stage flip-flop circuit for two clock cycles. For FF03, during one clock cycle, the number of clock cycles (number of generation stages c) stored in the FF table 4 is set as the value of the metastable counter. As a result, the flip-flop circuit FF02 outputs the metastable state value Dm for two clock cycles and the flip-flop circuit FF03 for one clock cycle.

  Therefore, according to the circuit verification method according to the first embodiment of the present invention, in the asynchronous sequential circuit 201 operated with another clock signal to which a signal output from a circuit operating with one clock signal is input, 2 The metastable state generated in the flip-flop circuit FF03 after the stage can also be reliably simulated. Therefore, according to the circuit verification method according to the first embodiment of the present invention, it is possible to verify the function of the logic circuit including the asynchronous sequential circuit by more reliably assuming the metastable state.

Embodiment 2. FIG.
Since the configuration of the circuit verification system according to the second embodiment is substantially the same as that of the circuit verification system 100 according to the first embodiment, the same components are denoted by the same reference numerals and the description thereof is omitted. FIG. 9 shows an operation flow assigned to the sequential circuit specified in the process of step S1 of FIG. 2, that is, the process shown in FIG. 4, in the circuit verification system according to the second embodiment.
With reference to the flowchart shown in FIG. 9, the functional simulation performed in step S3 in FIG. 2 for the sequential circuit specified in step S1 in FIG. 2 will be described. As shown in FIG. 9, the processes in steps S401 to S407, steps S409 to S410, and steps S411 to S413 are respectively performed in steps S310 to S307, steps S308 to S309, and S310 in FIG. Since it is the same as the processing in step S311, its description is omitted.

  Next, the computer 2 determines whether or not the preceding sequential circuit is in a metastable state by determining whether or not the number of clock cycles (the number of generation stages c) of the preceding sequential circuit is 0 (step S408). ).

  In step S408, when the number of clock cycles (number of generation stages c) of the preceding sequential circuit is not 0 (step S408; No), the computer 2 determines that the preceding sequential circuit is in the metastable state, and step S409 is performed. Proceed to

  In step S408, when the number of clock cycles (number of generation stages c) of the sequential circuit in the previous stage is 0 (step S408; Yes), the computer 2 determines that the sequential circuit in the previous stage is not in the metastable state. The circuit outputs the held signal (step S413).

  Next, the computer 2 sets the number of clock cycles (number of generation stages c) of the sequential circuit to 0 (step S414).

Hereinafter, the function simulation in step S3 in FIG. 2 will be specifically described with reference to the timing chart shown in FIG.
Since the simulation cycles 1 to 16 are the same as the simulation cycles 1 to 16 shown in FIG.

<About simulation cycle 17>
(About flip-flop circuit FF04)
In the simulation cycle 17, the clock signal CLK2 becomes an active edge (step S201; Yes, step S401; Yes).
Therefore, the flip-flop circuit FF04 holds the value “4” of the signal Q03 in step S202 of FIG. 5, and outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Since the value of the number of clock cycles (number of generation stages c) is “1” (step S402; Yes), in step S403, the computer 2 subtracts 1 from the number of clock cycles. As a result, the value of the number of clock cycles becomes “0”.
Next, since the value of the signal Q02 input to the flip-flop circuit FF03 is “7” and the value held by the flip-flop circuit FF03 is “4”, the computer 2 inputs to the flip-flop circuit FF03. It is determined that there is a change in the value of the signal Q02 to be executed (step S404; Yes).
Next, in step S406, the computer 2 newly sets the value “1” of the number of clock cycles (number of generation stages (c−1)) corresponding to the instance name “FF03” of the FF table 4 as the value of the metastable counter. To do.
In step 407 in FIG. 9, the flip-flop circuit FF03 holds the value “7” of the input signal Q02.

  Next, in step S408, the computer 2 determines whether or not the value of the number of clock cycles (number of generation stages c) of the flip-flop circuit FF02 in the previous stage of the flip-flop circuit FF03 is 0, and the number of clock cycles of the flip-flop circuit FF02. Is “0” (step S408; Yes), the computer 2 determines that the preceding flip-flop circuit FF02 is not in the metastable state.

Next, in step S413, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF03 to “0” and ends the metastable state of the flip-flop circuit FF03.

(About the flip-flop circuit FF02)
Further, the value of the number of clock cycles (number of generation stages c) is “0” (step S402; No), the value of the signal Q01 input to the flip-flop circuit FF02 is “7”, and the flip-flop circuit FF02 holds the value. Since the value of “7” is also “7”, the computer 2 determines that there is no change in the value of the signal Q01 input to the flip-flop circuit FF02 (step S404; No).
Next, since the number of clock cycles (number of generation stages c) of the flip-flop circuit FF02 is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S405; Yes).
In step S413 of FIG. 9, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF02 to “0”.

(About flip-flop circuit FF01)
In the simulation cycle 17, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 in FIG. 5, the flip-flop circuit FF01 outputs the held value “7” as the signal Q01.

<About simulation cycle 18>
(About flip-flop circuit FF04)
In the simulation cycle 18, the clock signal CLK2 does not become an active edge (step S201; No, step S401; No).
Therefore, the flip-flop circuit FF04 outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S411; Yes).
In step S413 in FIG. 9, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF03 to “0”.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S411; Yes).
In step S413 of FIG. 9, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF02 to “0”.

(About flip-flop circuit FF01)
In the simulation cycle 18, the clock signal CLK1 becomes an active edge (step S201; Yes).
Therefore, the flip-flop circuit FF01 holds the value “3” of the input signal DIN in step S202 of FIG. 5 and outputs the value “3” held in step S203 of FIG. 5 as the signal Q01.

<About simulation cycles 19-20>
(About flip-flop circuit FF04)
In the simulation cycles 19 to 20, the clock signal CLK2 does not become an active edge (Step S201; No, Step S401; No).
Therefore, the flip-flop circuit FF04 outputs the value “4” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S411; Yes).
In step S413 in FIG. 9, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF03 to “0”.

(About the flip-flop circuit FF02)
Further, since the value of the number of clock cycles (number of generation stages c) is “0”, the computer 2 determines that the flip-flop circuit FF02 is not in the metastable state (step S411; Yes).
In step S413 of FIG. 9, the flip-flop circuit FF02 outputs the held value “7” as the signal Q02.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF02 to “0”.

(About flip-flop circuit FF01)
In the simulation cycles 19 to 20, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

<About simulation cycle 21>
(About flip-flop circuit FF04)
In the simulation cycle 21, the clock signal CLK2 becomes an active edge (step S201; Yes, step S401; Yes).
Therefore, the flip-flop circuit FF04 holds the value “7” of the signal Q03 in step S202 of FIG. 5, and outputs the value “7” held in step S203 of FIG. 5 as the signal Q04.

(About flip-flop circuit FF03)
Further, the value of the number of clock cycles (number of generation stages c) is “0” (step S402; Yes), the value of the signal Q02 input to the flip-flop circuit FF03 is “7”, and the flip-flop circuit FF03 holds the value. Since the value of “7” is also “7”, the computer 2 determines that there is no change in the value of the signal Q02 input to the flip-flop circuit FF03 (step S404; No).
Next, since the number of clock cycles (number of generation stages c) of the flip-flop circuit FF03 is “0”, the computer 2 determines that the flip-flop circuit FF03 is not in the metastable state (step S405; Yes).
In step S413 in FIG. 9, the flip-flop circuit FF03 outputs the held value “7” as the signal Q03.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF03 to “0”.

(About the flip-flop circuit FF02)
The value of the number of clock cycles (number of generation stages c) is “0” (step S402; No), the value of the signal Q01 input to the flip-flop circuit FF02 is “3”, and the flip-flop circuit FF02 holds the value. Since the current value is “6”, the computer 2 determines that there is a change in the value of the signal Q01 input to the flip-flop circuit FF02 (step S404; Yes).
Next, in step S406, the computer 2 newly sets the value “2” of the number of clock cycles (number of generated stages c) corresponding to the instance name “FF02” of the FF table 4 as the value of the metastable counter.
In step 407 in FIG. 9, the flip-flop circuit FF02 holds the value “3” of the input signal Q01.

  Next, in step S408, the computer 2 determines whether or not the value of the number of clock cycles (number of generation stages c) of the flip-flop circuit FF01 in the previous stage of the flip-flop circuit FF02 is 0, and the number of clock cycles of the flip-flop circuit FF01. Is “0” (step S408; Yes), the computer 2 determines that the preceding flip-flop circuit FF01 is not in the metastable state.

Next, in step S413, the flip-flop circuit FF02 outputs the held value “6” as the signal Q02.
In step S414, the computer 2 sets the number of clock cycles of the flip-flop circuit FF02 to “0” and ends the metastable state of the flip-flop circuit FF02.

(About flip-flop circuit FF01)
In the simulation cycle 21, the clock signal CLK1 does not become an active edge (step S201; No).
Therefore, in step S203 of FIG. 5, the flip-flop circuit FF01 outputs the held value “3” as the signal Q01.

  The simulation cycles 22 to 26 are substantially the same as the simulation cycle shown in FIG.

As described above, in the functional simulation of the flip-flop circuit FF04, the metastable state output from the flip-flop circuit FF03 is held during the simulation cycles 13 to 16 and 17 to 20, and all the held metastable state values are stored. It is a different value. In the function simulation of the flip-flop circuit FF03, the metastable state output by the flip-flop circuit FF02 is held during the simulation cycles 9 to 12 and 13 to 16, and the held metastable state values are all different values. Yes.
When the flip-flop circuit FF03 is not in the metastable state, the value held by the flip-flop circuit FF04 in the simulation cycle 21 is the value “of the signal DIN input to the flip-flop circuit FF01 in the simulation cycles 2 to 15”. 7 ”.

  Specifically, in the asynchronous sequential circuit 201 to which a signal is input from the flip-flop circuit FF01 operating with the clock signal CLK1, the first-stage flip-flop circuit FF02 has a second-stage flip-flop circuit for two clock cycles. For FF03, during one clock cycle, the number of clock cycles (number of generation stages c) stored in the FF table 4 is set as the value of the metastable counter. As a result, the flip-flop circuit FF02 outputs the metastable state value Dm for two clock cycles and the flip-flop circuit FF03 for one clock cycle.

  Therefore, according to the circuit verification method according to the second embodiment of the present invention, the same effect as the circuit verification method according to the first embodiment can be obtained, and the flip-flop circuit in the previous stage is in the metastable state. If the previous flip-flop circuit is not in the metastable state, the computer 2 sets the number of clock cycles (the number of generation stages c) to “0”, so that the metastable state may be terminated. it can. Therefore, a state closer to the metastable state in the actual logic circuit can be simulated.

It should be noted that the present invention is not limited to the above-described embodiment, and the design is appropriately changed without departing from the spirit of the present invention.
For example, the sequential circuit included in the asynchronous sequential circuit is not limited to the flip-flop circuit.

1 server 2 computer (circuit verification device)
3 Network 4 FF table 41 Instance name 42 Number of clock cycles 100 Circuit verification system 201 Asynchronous sequential circuit FF01 Flip-flop circuit (first-stage sequential circuit)
FF02 Flip-flop circuit (second-stage sequential circuit)
FF03 Flip-flop circuit (third-stage sequential circuit)
FF04 Flip-flop circuit (fourth sequential circuit)
CC2 combination circuit CLK1 clock signal CLK2 clock signal

Claims (8)

A circuit verification device for verifying the function of a logic circuit,
Based on the clock cycle Tdist of the asynchronous sequential circuit included in the logic circuit and the metastable convergence time Tmc of the sequential circuit of the first stage of the asynchronous sequential circuit, the metastable state is expressed by the following equation (1). A generation stage number calculation unit for calculating a value generation stage number c;
By analyzing a circuit design program of the logic circuit described in a predetermined program language, the nth stage connected from the first stage sequential circuit to the output side of the first stage sequential circuit A sequential circuit specifying unit that specifies up to a sequential circuit (n is an integer satisfying n ≧ 2);
In the functional simulation of the logic circuit, the metas is supplied to the sequential circuit from the first stage to the n-th stage by the number of clock cycles equal to the number of generated stages c to the number of generated stages c- (n-1). A function simulation controller that outputs table state values;
A circuit verification apparatus comprising:
c = int (Tmc / Tdist) +1 (1) The simulation control unit
It is determined whether or not the value of the input signal of the sequential circuit specified by the sequential circuit specifying unit has changed, and when the value of the input signal of the sequential circuit specified by the sequential circuit specifying unit has changed, The circuit verification apparatus according to claim 1, wherein the metastable state value is output from the sequential circuit. The function simulation control unit
It is determined whether or not the value of the input signal of the sequential circuit specified by the sequential circuit specifying unit has changed, and when the value of the input signal of the sequential circuit specified by the sequential circuit specifying unit has changed, It is determined whether the previous circuit of the sequential circuit is in a metastable state, and when the previous circuit is in a metastable state, from the time when the value of the input signal of the sequential circuit changes, the sequential circuit The circuit verification device according to claim 1, wherein the metastable state value is output.   An instance name of the sequential circuit from the first stage to the n-th sequential circuit is associated with the number of clock cycles equal to (the generation stage number c- (n-1)) from the generation stage number c. The circuit verification apparatus according to claim 1, further comprising an FF table storage control unit that stores the FF table in the storage unit. A circuit verification method for verifying the function of a logic circuit,
Computer
Based on the clock cycle Tdist of the asynchronous sequential circuit included in the logic circuit and the metastable convergence time Tmc of the sequential circuit of the first stage of the asynchronous sequential circuit, the metastable state is expressed by the following equation (1). A generation stage number calculation process for calculating a value generation stage number c;
By analyzing a circuit design program of the logic circuit described in a predetermined program language, the nth stage connected from the first stage sequential circuit to the output side of the first stage sequential circuit A sequential circuit specifying process for specifying up to a sequential circuit (n is an integer satisfying n ≧ 2);
In the functional simulation of the logic circuit, the metas is supplied to the sequential circuit from the first stage to the n-th stage by the number of clock cycles equal to the number of generated stages c to the number of generated stages c- (n-1). A function simulation control process for outputting a table state value;
A circuit verification method for executing
c = int (Tmc / Tdist) +1 (1) In the simulation control process, the computer
It is determined whether or not the value of the input signal of the sequential circuit specified in the sequential circuit specifying process has changed, and when the value of the input signal of the sequential circuit specified in the sequential circuit specifying process has changed, the order The circuit verification method according to claim 5, wherein the metastable state value is output from a circuit. In the function simulation control process, the computer
It is determined whether or not the value of the input signal of the sequential circuit specified in the sequential circuit specifying process has changed, and when the value of the input signal of the sequential circuit specified in the sequential circuit specifying process has changed, the order It is determined whether or not the previous stage circuit is in a metastable state, and when the previous stage circuit is in a metastable state, when the value of the input signal of the sequential circuit changes, the metastable is output from the sequential circuit. The circuit verification method according to claim 5, wherein the state value is output. The computer
An instance name of the sequential circuit from the first stage to the n-th sequential circuit is associated with the number of clock cycles equal to (the generation stage number c- (n-1)) from the generation stage number c. The circuit verification method according to claim 5, wherein an FF table storage control process for storing the FF table in the storage unit is executed.

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