JP2011211608A - Impedance adjustment circuit, and method of controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a reduction in accuracy of adjusting impedance.SOLUTION: The impedance adjustment circuit includes: first and second external terminals to be connected to external resistors; a first dummy buffer part having output impedance adjusted in accordance with a first switch connected between the first external terminal and a first power line, and a first control signal; a second dummy buffer part having output impedance adjusted in accordance with a second switch connected between the second external terminal and a second power line, and a second control signal; and a control part for setting the output impedance of the first dummy buffer part by the first control signal in accordance with the voltage of the first external terminal by closing the first switch and opening the second switch, and setting the output impedance of the second dummy buffer part by the second control signal in accordance with the voltage of the second externa terminal by opening the first switch and closing the second switch.

Description

  The present invention relates to an impedance adjustment circuit and a control method thereof.

  FIG. 9 is a schematic diagram of the output buffer OB1 included in the semiconductor integrated circuit and the transmission line TL1 connected thereto. The output buffer OB1 has an output impedance of ZA. The transmission line TL1 has a characteristic impedance of ZB. Here, if the output impedance ZA and the characteristic impedance ZB of the transmission line are not matched, reflection of the output signal from the output buffer OB1 occurs.

  And the quality of the signal which should be transmitted by the interference of the reflected wave produced by the reflection and an output signal deteriorates. For this reason, it is necessary to match the output impedance ZA of the output buffer OB1 of the semiconductor integrated circuit with the characteristic impedance ZB of the transmission line. However, the characteristic impedance ZB of the transmission line TL1 is usually fixed. Therefore, it is necessary to adjust the output impedance ZA of the output buffer OB1 to a value close to ZB. For this reason, the semiconductor integrated circuit includes an output impedance adjustment circuit that adjusts the output impedance ZA.

  FIG. 10 shows a configuration of a conventional output impedance adjustment circuit 1. As shown in FIG. 10, the output impedance adjustment circuit 1 includes an output buffer unit 10 and an impedance adjustment unit 20.

  The output buffer unit 10 includes a pull-up buffer unit 11, a pull-down buffer unit 12, NAND circuits NAND11 to NAND13, NOR circuits NOR11 to NOR13, and inverter circuits IV11 to IV13. The pull-up buffer unit 11 includes PMOS transistors MP11 to MP13. The pull-down buffer unit 12 includes NMOS transistors MN11 to MN13.

  The outputs of the NAND circuits NAND11 to NAND13 are connected to the gates of the PMOS transistors MP11 to MP13, respectively. The PMOS transistors MP11 to MP13 are connected in parallel between the power supply terminal VDD and the output terminal TOB1, respectively.

  The outputs of the NOR circuits NOR11 to NOR13 are connected to the gates of the NMOS transistors MN11 to MN13, respectively. The NMOS transistors MN11 to MN13 are connected in parallel between the output terminal TOB1 and the ground terminal GND, respectively.

  The buffer input signal S1 is applied to one input terminal of the NAND circuits NAND11 to NAND13 and the input of the inverter circuits IV11 to IV13, respectively. Outputs of the inverter circuits IV11 to IV13 are connected to one input terminals of the NOR circuits NOR11 to NOR13, respectively.

  The impedance adjustment unit 20 includes a dummy pull-up buffer unit 21, a dummy pull-down buffer unit 22, a reference voltage generation circuit 23, counters 24 and 25, comparators CMP21 and CMP22, inverter circuits IV21 to IV23, and an external terminal TP1. , TP2.

  The dummy pull-up buffer unit 21 includes PMOS transistors MP21 to MP23. The dummy pull-down buffer unit 22 includes NMOS transistors MN21 to MN23. The PMOS transistors MP21 to MP23 are connected in parallel between the power supply terminal VDD and the external terminal TP1, respectively. The NMOS transistors MN21 to MN23 are connected in parallel between the external terminal TP2 and the ground terminal GND, respectively.

  The reference voltage generation circuit 23 includes resistors R21 to R23. The resistor R21 is connected between the power supply terminal VDD and the node N21. The resistor R22 is connected between the node N21 and the node N22. The resistor R23 is connected between the node N22 and the ground terminal GND. Then, the voltage at the node N21 is output as the reference voltage VREF1, and the voltage at the node N22 is output as the reference voltage VREF2.

  The comparator CMP21 has a non-inverting input terminal connected to the external terminal TP1, and an inverting input terminal connected to the node N21. Therefore, the comparator CMP21 compares the voltage VTP1 of the external terminal TP1 with the reference voltage VREF1 of the node N21 and outputs the comparison result to the counter 24. For example, a high level is output when VTP1> VREF1, and a low level is output when VTP1 <VREF1.

  The comparator CMP22 has a non-inverting input terminal connected to the external terminal TP2, and an inverting input terminal connected to the node N22. Therefore, the comparator CMP22 compares the voltage VTP2 of the external terminal TP2 with the reference voltage VREF2 of the node N22 and outputs the comparison result to the counter 25. For example, a high level is output when VTP2> VREF2, and a low level is output when VTP2 <VREF2.

  When the low level signal is input from the comparator CMP21, the counter 24 counts up according to the clock CLK. Conversely, when a high level signal is input, the countdown is performed according to the clock CLK. For example, the counter 24 outputs 3-bit count output signals P1 to P3 as shown in FIG. The count output signal P1 is input to the input terminal of the inverter circuit IV21 and the other input terminal of the NAND circuit NAND11. The count output signal P2 is input to the input terminal of the inverter circuit IV22 and the other input terminal of the NAND circuit NAND12. The count output signal P3 is input to the input terminal of the inverter circuit IV23 and the other input terminal of the NAND circuit NAND13.

  Inverter circuits IV21 to IV23 receive count output signals P1 to P3 from counter 24, respectively. The inverted signal is output to the gates of the PMOS transistors MP21 to MP23 of the dummy pull-up buffer unit 21.

  When a high level signal is input from the comparator CMP22, the counter 25 counts up according to the clock CLK. Conversely, when a low level signal is input, the countdown is performed in accordance with the clock CLK. The counter 25 outputs 3-bit count output signals N1 to N3, for example, as shown in FIG. The count output signal N1 is input to the gate of the NMOS transistor MN21 and the other input terminal of the NOR circuit NOR11. The count output signal N2 is input to the gate of the NMOS transistor MN22 and the other input terminal of the NOR circuit NOR12. The count output signal N3 is input to the gate of the NMOS transistor MN23 and the other input terminal of the NOR circuit NOR13.

  An external calibration resistor R1 is connected to the external terminal TP1. The calibration resistor R1 is connected between the external terminal TP1 and the ground terminal GND. An external calibration resistor R2 is connected to the external terminal TP2. The calibration resistor R2 is connected between the power supply terminal VDD and the external terminal TP1. The calibration resistors R1 and R2 have resistance values corresponding to the characteristic impedance of the transmission line connected to the output terminal TOB1.

  An operation example of the output impedance adjustment circuit 1 of FIG. 10 will be described based on the timing charts of FIGS. 11 and 12. As an initial state, it is assumed that the PMOS transistors MP21 to MP23 included in the dummy pull-up buffer unit 21 and the NMOS transistors MN21 to MN23 included in the dummy pull-down buffer unit 22 are all off.

  The PMOS transistors MP21 to MP23 are weighted with on-resistance according to the bit digit of the signal output from the counter 24. For example, if the on-resistances of the PMOS transistors MP21 to MP23 are RonP21 to RonP23, respectively, RonP21> RonP22> RonP23. The resistor RonP23 is assumed to be smaller than the combined resistance of RonP21 and RonP22 connected in parallel.

  Similarly, the on-resistances of the NMOS transistors MN21 to MN23 are weighted according to the bit digit of the signal output from the counter 25. For example, when the on-resistances of the NMOS transistors MN21 to MN23 are RonN21 to RonN23, respectively, RonN21> RonN22> RonN23. The resistor RonN23 is assumed to be smaller than the combined resistance of RonN21 and RonN22 connected in parallel.

  First, as shown in FIG. 11, at time t1, the voltage VTP1 of the external terminal TP1 becomes the ground voltage GND because all the PMOS transistors included in the dummy pull-up buffer unit 21 are in the off state. Thereby, the comparator CMP21 outputs a low level signal, the counter 24 counts up in synchronization with the rising of the clock CLK at time t2, and the count output signal P1 becomes high level. Therefore, the PMOS transistor MP21 is turned on at time t2, and the voltage VTP1 rises to a voltage divided by the resistors RonP21 and R1.

  Since the voltage VTP1 at time t2 is higher than the reference voltage VREF1, the comparator CMP21 continuously outputs a low level signal. Therefore, the counter 24 counts up in synchronization with the rise of the clock CLK at time t3, the count output signal P1 becomes low level, and the count output signal P2 becomes high level. Therefore, the PMOS transistor MP22 is turned on at time t3, and the voltage VTP1 rises to a voltage divided by the resistors RonP22 and R1.

  Since the voltage VTP1 at time t3 is lower than the reference voltage VREF1, the comparator CMP21 continuously outputs a low level signal. Therefore, the counter 24 counts up in synchronization with the rising of the clock CLK at time t4, and the count output signals P1 and P2 become high level. Therefore, the PMOS transistors MP21 and MP22 are turned on at time t4, and the voltage VTP1 rises to a voltage divided by the combined resistance of the resistors RonP21 and RonP22 connected in parallel and R1.

  The voltage VTP1 at time t4 becomes higher than the reference voltage VREF1, and the comparator CMP21 outputs a high level signal. Therefore, the counter 24 counts down in synchronization with the rising of the clock CLK at time t5, and the count output signal P2 becomes low level. Therefore, the PMOS transistor MP22 is turned off at time t5, and the voltage VTP1 is reduced to a voltage divided by the resistors RonP21 and R1.

  The voltage VTP1 at time t5 becomes lower than the reference voltage VREF1 again, and the comparator CMP21 outputs a low level signal. Therefore, the counter 24 counts up in synchronization with the rise of the clock CLK at time t6, and the count output signal P2 becomes high level again. Therefore, the PMOS transistor MP22 is turned on at time t6, and the voltage VTP1 rises to a voltage divided by the combined resistance of the resistors RonP21 and RonP22 connected in parallel and R1.

  Then, after time t6, the same operation is repeated, and the count output signals P1 to P3 are determined after a predetermined period.

  The determined count output signals P1 to P3 are simultaneously input to the other input terminals of the NAND11 to NAND13. Therefore, when the buffer input signal S1 is at a high level, the PMOS transistor of the pull-up buffer unit 11 corresponding to the PMOS transistor of the dummy pull-up buffer unit 21 is turned on, and the impedance of the pull-up buffer unit 11 is set to the calibration resistor R1. The value is consistent with

  In this example, to simplify the description, the counter 24 and its output signal are set to 3 bits, but may be configured to have N bits (N> 3). In this case, of course, N PMOS transistors of the pull-up buffer unit 21 and the dummy pull-up buffer unit 21 are required.

  Next, as shown in FIG. 12, at time t1, the voltage VTP2 of the external terminal TP2 becomes the power supply voltage VDD because all the NMOS transistors included in the dummy pull-down buffer unit 22 are off. Accordingly, the comparator CMP22 outputs a high level signal, the counter 25 counts up in synchronization with the rising of the clock CLK at time t2, and the count output signal N1 becomes high level. For this reason, the NMOS transistor MN21 is turned on at time t2, and the voltage VTP2 drops to a voltage divided by the resistors RonN21 and R2.

  Since the voltage VTP2 at time t2 is higher than the reference voltage VREF2, the comparator CMP22 continues to output a high level signal. Therefore, the counter 25 counts up in synchronization with the rise of the clock CLK at time t3, the count output signal N1 becomes low level, and the count output signal N2 becomes high level. Therefore, the NMOS transistor MN22 is turned on at time t3, and the voltage VTP2 is reduced to a voltage divided by the resistors RonN22 and R2.

  Since the voltage VTP2 at time t3 is higher than the reference voltage VREF2, the comparator CMP22 continues to output a high level signal. Therefore, the counter 25 counts up in synchronization with the rising of the clock CLK at time t4, and the count output signals N1 and N2 become high level. Therefore, at time t4, the NMOS transistors MN21 and MN22 are turned on, and the voltage VTP2 decreases to a voltage divided by the combined resistance of the resistors RonN21 and RonN22 connected in parallel and R2.

  The voltage VTP2 at time t4 becomes lower than the reference voltage VREF2, and the comparator CMP22 outputs a low level signal. Therefore, the counter 25 counts down in synchronization with the rise of the clock CLK at time t5, and the count output signal N2 becomes low level. Therefore, the NMOS transistor MN22 is turned off at time t5, and the voltage VTP2 rises to a voltage divided by the resistors RonN21 and R2.

  The voltage VTP2 at time t5 becomes higher than the reference voltage VREF2, and the comparator CMP22 outputs a high level signal. Therefore, the counter 25 counts up in synchronization with the rise of the clock CLK at time t6, and the count output signal N2 becomes high level again. Therefore, at time t6, the NMOS transistor MN22 is turned on, and the voltage VTP2 decreases to a voltage divided by the combined resistance of the resistors RonN21 and RonN22 connected in parallel and R2.

  Then, after time t6, the same operation is repeated, and the count output signals N1 to N3 are determined after a predetermined period.

  The determined count output signals N1 to N3 are simultaneously input to the other input terminals of the NOR circuits NOR11 to NOR13. For this reason, when the buffer input signal S1 is at a high level, the NMOS transistor of the pull-down buffer unit 12 corresponding to the NMOS transistor of the dummy pull-down buffer unit 22 is turned on, and the impedance of the pull-down buffer unit 12 matches the calibration resistor R2. Value.

  In this example, to simplify the description, the counter 25 and its output signal are set to 3 bits, but may be configured to have N bits (N> 3). In this case, of course, N NMOS transistors of the pull-down buffer unit 22 and the dummy pull-down buffer unit 22 are also required.

  Here, in the field of semiconductor integrated circuits, there is a demand for reduction in the number of mounted components as equipment is reduced in size and cost. For this reason, Patent Document 1 discloses a technique capable of reducing the number of external resistors used for calibration. The configuration of the output impedance adjustment circuit 2 disclosed in Patent Document 1 is shown in FIG.

  As shown in FIG. 13, the output impedance adjustment circuit 2 includes dummy pull-up units 11A and 11B, a dummy pull-down unit 21, control circuits 12 and 22, comparators CMP11 and CMP21, and an external terminal T1. An external reference resistor R_REP for calibration is connected to the external terminal T1.

  An operation example of the output impedance adjustment circuit 2 of FIG. 13 will be briefly described below. In the initial state, it is assumed that the PMOS transistors included in the dummy pull-up buffer units 11A and 11B and the NMOS transistor included in the dummy pull-down buffer unit 21 are all in an off state.

  First, due to the operations of the comparator CMP11 and the control circuit 22, the impedance of the dummy pull-up buffer unit 11A is lowered until the reference voltage VREF1 and the voltage VT1 of the external terminal T1 are balanced. This is realized by the PMOS transistor of the dummy pull-up buffer unit 11A being turned on by the control signal CP output from the control circuit 12.

  Since the control signal CP is also output to the dummy pull-up buffer unit 11B, the voltage level of the node N1 changes. The impedance of the dummy pull-down buffer unit 21 is controlled by the control signal CN so that the potential of the node N1 and the reference voltage VREF2 is balanced by the comparator CMP21 and the control circuit 22.

  Then, the control signals CN and CP when the potentials of the external terminal T1 and the node N1 are stabilized are sent from the output impedance adjustment circuit 2 to the output buffer, and the output buffer generates an output impedance corresponding to the control signals CN and CP. Can do. As a result, the number of external reference resistors can be reduced.

JP 2000-59202 A

  However, the output impedance adjustment circuit 2 cannot use the reference resistance on the dummy pull-down buffer unit 21 side. For this reason, there is a possibility that the impedance of the dummy pull-down buffer unit 21 cannot be accurately adjusted due to manufacturing variations of the PMOS transistors of the dummy pull-up buffer units 11A and 11B.

  Therefore, the output impedance adjustment circuit 2 has a problem that the impedance adjustment accuracy of the output buffer is lowered and a problem that the quality of the signal to be transmitted from the output buffer to the transmission path is deteriorated. Therefore, there is a need for an output impedance adjustment circuit that prevents the impedance adjustment accuracy of the output buffer from degrading while suppressing an increase in the number of mounted components.

  In one embodiment of the present invention, a first buffer portion connected between an output terminal and a first power supply line and having an output impedance set according to a first control signal, the output terminal and the second power supply line A second buffer unit connected in between and having an output impedance set according to a second control signal; an external resistor; a first external terminal to which one end of the external resistor is connected; A second external terminal to which the other end of the attached resistor is connected; a first switch connected between the first external terminal and the first power supply line; the second external terminal; and the second external terminal. A second switch connected between the first power supply line, a first switch connected between the first external terminal and the first power supply line, and an output impedance is adjusted in accordance with the first control signal. A dummy buffer unit is connected between the second external terminal and the second power line. , A second dummy buffer unit whose output impedance is adjusted according to the second control signal, and in the first mode, the first switch is turned on, the second switch is turned off, The first control signal is set so that the output impedance of the first dummy buffer unit is adjusted to a desired value according to the voltage of the first external terminal. In the second mode, the first switch is turned on. Non-conductive, the second switch is turned on, and the second control signal is set so that the output impedance of the second dummy buffer unit is adjusted to a desired value according to the voltage of the second external terminal. And an impedance adjustment circuit having a control unit.

  According to another aspect of the present invention, a first buffer unit connected between an output terminal and a first power supply line and having an output impedance set according to a first control signal, the output terminal and a second power supply is provided. A second buffer unit connected between the lines and whose output impedance is set according to a second control signal; an external resistor; and a first external terminal to which one end of the external resistor is connected; A second external terminal to which the other end of the external resistor is connected; a first switch connected between the first external terminal and the first power supply line; the second external terminal; A second switch connected between the two power lines, a first switch connected between the first external terminal and the first power line, and an output impedance adjusted in accordance with the first control signal. Connected between the dummy buffer section and the second external terminal and the second power supply line And a second dummy buffer unit that adjusts an output impedance in accordance with the second control signal. In the first mode, in the first mode, the first switch is turned on. The first control signal is set so that the output impedance of the first dummy buffer unit is adjusted to a desired value according to the voltage of the first external terminal. In the second mode, the first switch is made non-conductive and the second switch is made conductive, and the output impedance of the second dummy buffer unit is set to a desired value according to the voltage of the second external terminal. This is a control method of the impedance adjustment circuit for setting the second control signal to be adjusted to a value.

  In the output impedance adjusting circuit according to the present invention, when the first control signal is set, the first switch is turned on, the second switch is turned off, the first dummy buffer unit, the first external terminal, A current path is formed by the attached resistor, the second external terminal, and the second switch, and the impedance is adjusted according to the voltage of the first external terminal. Further, when setting the second control signal, the first switch is made non-conductive and the second switch is made conductive, the second dummy buffer section, the first external terminal, the external resistor, the second external A current path is formed by the terminal and the first switch, and the impedance is adjusted according to the voltage of the second external terminal. Thus, the impedance of the first dummy buffer unit and the second dummy buffer unit can be adjusted with a common external resistor.

  The output impedance adjustment circuit according to the present invention can suppress the increase in the number of mounted components, improve the impedance adjustment accuracy of the output buffer, and ensure the quality of the signal to be transmitted from the output buffer to the transmission path.

It is an example of the structure of the output impedance adjustment circuit concerning embodiment. 4 is a timing chart showing a relationship between a select control signal and each mode according to the embodiment. It is a schematic diagram explaining the operation | movement at the time of the 1st mode of the output impedance adjustment circuit concerning embodiment. It is a schematic diagram explaining the operation | movement at the time of the 1st mode of the output impedance adjustment circuit concerning embodiment. It is a schematic diagram explaining the buffer specification (corresponding to the first mode) of the output impedance adjustment circuit according to the embodiment. It is a schematic diagram explaining the operation | movement at the time of the 2nd mode of the output impedance adjustment circuit concerning embodiment. It is a schematic diagram explaining the operation | movement at the time of the 2nd mode of the output impedance adjustment circuit concerning embodiment. It is a schematic diagram explaining the buffer specification (corresponding to the second mode) of the output impedance adjustment circuit according to the embodiment. It is a figure explaining the structure of a general output buffer and a transmission path. This is a configuration of a conventional output impedance adjustment circuit. It is a timing chart which shows operation | movement of a dummy pull-up buffer part. It is a timing chart which shows operation | movement of a dummy pull-down buffer part. This is a configuration of a conventional output impedance adjustment circuit.

  BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows an example of the configuration of the output impedance adjustment circuit 100 according to the present embodiment.

  As shown in FIG. 1, the output impedance adjustment circuit 100 includes an output buffer unit 110 and an impedance adjustment unit 120.

  The output buffer unit 110 includes a pull-up buffer unit 111, a pull-down buffer unit 112, NAND circuits NAND111 to NAND113, and NOR circuits NOR111 to NOR113. The pull-up buffer unit 111 includes PMOS transistors MP111 to MP113. The pull-down buffer unit 112 includes NMOS transistors MN111 to MN113.

  The buffer input signal S1 is input to one input terminal of each of the NAND circuits NAND111 to NAND113. Pull-up side count signals P1 to P3 described later are input to the other input terminals of the NAND circuits NAND111 to NAND113. Output terminals of the NAND circuits NAND111 to NAND113 are connected to the gates of the PMOS transistors MP111 to MP113, respectively. The PMOS transistors MP111 to MP113 are connected in parallel between the power supply terminal VDD and the output terminal TOB1. Note that a transmission path having a predetermined characteristic impedance as described in FIG. 9 is connected to the output terminal TOB1.

  The buffer input signal S1 is input to one input terminal of each of the NOR circuits NOR111 to NOR113. Pull-down count signals N1 to N3 (described later) are input to the other input terminals of the NOR circuits NOR111 to NOR113 via inverter circuits IV124 to IV126 (described later), respectively. The output terminals of the NOR circuits NOR111 to NOR113 are connected to the gates of the NMOS transistors MN111 to MN113, respectively. The NMOS transistors MN111 to MN113 are connected in parallel between the output terminal TOB1 and the ground terminal GND, respectively.

  The impedance adjustment unit 120 includes a dummy pull-up buffer unit 121, a dummy pull-down buffer unit 122, a reference voltage generation circuit 123, a counter 124, switching control circuits 125 to 127, a comparator CMP 121, and switch circuits SW131 and SW132. Inverter circuits IV121 to IV126 and external terminals TP1 and TP2.

  The dummy pull-up buffer unit 121 includes PMOS transistors MP121 to MP123. The PMOS transistors MP121 to MP123 are connected in parallel between the power supply terminal VDD and the external terminal TP1, respectively. Also, pull-up side count signals P1 to P3 described later are input to the gates of the PMOS transistors MP121 to MP123.

  Further, the PMOS transistors MP121 to MP123 are weighted with on-resistance according to the bit digits of the pull-up side count signals P1 to P3. For example, if the on-resistances of the PMOS transistors MP121 to MP123 are RonP121 to RonP123, respectively, RonP121> RonP122> RonP123. The resistor RonP123 is assumed to be smaller than the combined resistance of RonP121 and RonP122 connected in parallel.

  The dummy pull-down buffer unit 122 includes NMOS transistors MN121 to MN123. The NMOS transistors MN121 to MN123 are connected in parallel between the external terminal TP2 and the ground terminal GND, respectively. In addition, pull-down count signals N1 to N3 described later are input to the gates of the NMOS transistors MN121 to MN123.

  Further, the NMOS transistors MN121 to MN123 are weighted with on-resistance according to the bit digits of the pull-down count signals N1 to N3. For example, assuming that the on-resistances of the NMOS transistors MN121 to MN123 are RonN121 to RonN123, respectively, RonN121> RonN122> RonN123. The resistor RonN123 is assumed to be smaller than the combined resistance of RonN121 and RonN122 connected in parallel.

  The switch circuit SW131 includes a PMOS transistor MP131. The PMOS transistor MP131 is connected between the power supply terminal VDD and the external terminal TP1.

  The dummy pull-down buffer unit 122 includes NMOS transistors MN121 to MN123. The NMOS transistors MN121 to MN123 are connected in parallel between the external terminal TP2 and the ground terminal GND, respectively.

  The switch circuit SW132 includes an NMOS transistor MN132. The NMOS transistor MN132 is connected between the external terminal TP2 and the ground terminal GND. The mode control signal SEL is input to the gate.

  The reference voltage generation circuit 123 includes resistors R121 to R123. The resistor R121 is connected between the power supply terminal VDD and the node N121. The resistor R122 is connected between the node N121 and the node N22. The resistor R123 is connected between the node N22 and the ground terminal GND. Then, the voltage at the node N121 is output as the reference voltage VREF1, and the voltage at the node N122 is output as the reference voltage VREF2.

  The switching control circuit 125 connects the external terminal TP1 or the external terminal TP2 to the node N123 according to the mode control signal SEL.

  The switching control circuit 126 connects the node N121 or the node N122 to the node N124 according to the mode control signal SEL.

  The comparator CMP121 has a non-inverting input terminal connected to the node N123 and an inverting input terminal connected to the node N124. Therefore, the comparator CMP121 compares the voltages of the nodes N123 and N124 and outputs the comparison result to the counter 124.

  In response to the mode control signal SEL, for example, when the mode control signal SEL is at a low level, the counter 124 counts up according to the clock CLK when a low level signal is input from the comparator CMP121, and receives a high level signal when the high level signal is input. Countdown is performed according to CLK. Conversely, for example, when the mode control signal SEL is at a high level, when a high level signal is input from the comparator CMP121, the count is increased according to the clock CLK, and when a low level signal is input, the count down is performed according to the clock CLK.

  In this example, the counter 124 and its count output signal are set to 3 bits to simplify the description, but may be configured to have N bits (N> 3). In addition, when the count output signal is N bits, naturally, the dummy pull-up buffer unit 121, the PMOS transistors of the pull-up buffer unit 111, and the NMOS transistors of the dummy pull-down buffer unit 122 and the pull-down buffer unit 112 are also required. It becomes.

  The switching control circuit 127 receives the count output signal from the counter 124, and outputs the count output signal as the pull-up side count signals P1 to P3 or the pull-down side count signals N1 to N3 according to the mode control signal SEL. .

  When the switching control circuit 127 outputs the count output signal from the counter 124 as the pull-up side count signals P1 to P3, the pull-down side count signals N1 to N3 are set to the low level, and conversely, the count output signal from the counter 124 is output. Are output as the pull-down count signals N1 to N3, the pull-up count signals P1 to P3 are set to the low level. However, the count output signal from the counter 124 is stored immediately before the pull-up side count signals P1 to P3 are switched from the pull-up side count signals P1 to P3 to the pull-down side count signals N1 to N3, or the count output signal from the counter 124 is stored. Has a storage circuit for storing the pull-down count signals N1 to N3 immediately before switching from the pull-down count signals N1 to N3 to the pull-up count signals P1 to P3.

  The pull-up side count signals P1 to P3 output from the switching control circuit 127 are input to the other input terminals of the NAND circuits NAND111 to NAND113 and the input terminals of the inverter circuits IV121 to IV123. The pull-down count signals N1 to N3 output from the switching control circuit 127 are input to the input terminals of the inverter circuits IV124 to IV126 and the gates of the NMOS transistors MN121 to MN123. Outputs of the inverter circuits IV124 to IV126 are connected to the other input terminals of the NOR circuits NOR111 to NOR113, respectively.

  An external reference resistor Rref is connected between the external terminals TP1 and TP2. It can be considered that the reference voltage generation circuit 123, the counter 124, the switching control circuits 125 to 127, and the comparator CMP121 constitute a control circuit that adjusts the impedance of the dummy pull-up buffer unit 121 and the dummy pull-down buffer unit 122, respectively.

  Next, the operation of the output impedance adjustment circuit 100 according to this exemplary embodiment will be described. First, as shown in FIG. 2, for example, the mode control signal SEL is at a high level during a period from time t1 to t2, and is at a low level during a period from time t2 to t3. As will be described below, during the period from time t1 to t2, the dummy pull-up buffer unit 121 is in the adjustment mode, and the dummy pull-down buffer unit 122 is in the non-adjustment mode. The same applies to the period from time t3 to t4.

  In the period from time t2 to t3, the dummy pull-up buffer unit 121 is in the non-adjustment mode, and the dummy pull-down buffer unit 122 is in the adjustment mode. The same applies to the period from time t4 to t5. Hereinafter, a period in which the mode control signal SEL is at a high level is referred to as a first mode, and a period in which the mode control signal SEL is at a low level is referred to as a second mode.

  In the first mode from time t1 to time t2, since the mode control signal SEL is at a high level, the PMOS transistor MP131 of the switch circuit SW131 is turned off and the NMOS transistor MN132 of the switch circuit SW132 is turned on. In addition, the switching control circuit 125 electrically connects the external terminal TP1 and the node N123.

  Further, the switching control circuit 126 electrically connects the nodes N121 and N124. The switching control circuit 127 outputs the output count signal from the counter 124 as the pull-up side count signals P1 to P3, and outputs all the pull-down side count signals N1 to N3 as the low level. Further, the counter 124 counts up with a low level input and counts down with a high level input.

  FIG. 3 shows a configuration of the impedance adjustment unit 120 in which the switching control circuits 125 to 127 in the first mode are omitted. Hereinafter, the operation of the output impedance adjustment circuit 100 in the first mode will be described with reference to FIG. First, since the mode control signal SEL is at a high level, the PMOS transistor MP131 of the switch circuit SW131 is turned off, and the power supply terminal VDD and the external terminal TP1 are cut off.

  Further, the NMOS transistor MN132 of the switch circuit SW132 is turned on, and the external terminal TP2 and the ground terminal GND are brought into conduction. Further, since all the pull-down count signals N1 to N3 are at the low level, all the NMOS transistors MN121 to MN123 of the dummy pull-down buffer unit 122 are turned off, and the external terminal TP2 and the ground terminal GND are cut off.

  Therefore, a current constituted by the power supply terminal VDD, the dummy pull-up buffer unit 121, the external terminal TP1, the reference resistor Rref, the external terminal TP2, the switch circuit SW132 (NMOS transistor MN132), and the ground terminal GND. A current flows through the path A.

  Further, the voltage VTP1 of the external terminal TP1 is input to the non-inverting input terminal of the comparator CMP121, and the reference voltage VREF1 is input to the inverting input terminal.

  In the initial state of the first mode, since the count value of the counter 124 is “0”, all count output signals are also at a low level. Therefore, all the pull-up side count signals P1 to P3 are also at a low level, and as a result, all the PMOS transistors MP121 to MP123 of the dummy pull-up buffer unit 121 are turned off. For this reason, the voltage VTP1 of the external terminal TP1 becomes the ground voltage GND. Since the comparator CMP121 compares the voltage VTP1 with the reference voltage VREF1, the comparator CMP121 outputs a low level signal.

  Thereafter, an operation similar to the operation described with reference to FIG. That is, when the voltage VTP1 of the external terminal TP1 is lower than the reference voltage VREF1, the comparator CMP121 outputs a low level, and the counter 124 counts up according to the clock CLK. By this count-up operation, the operation is the same as that described with reference to FIG. The counter 124 counts up until the voltage VTP1 of the external terminal TP1 rises above the reference voltage VREF1.

  Conversely, when the voltage VTP1 of the external terminal TP1 is higher than the reference voltage VREF1, the comparator CMP121 outputs a high level, and the counter 124 counts down according to the clock CLK. By this countdown operation, the operation is the same as that described with reference to FIG. 11, and the off state is set according to the pull-up side count signals P1 to P3.

  By repeating the above operation, the voltage VTP1 of the external terminal TP1 becomes a value close to the reference voltage VREF1, the pull-up side count signals P1 to P3 are determined after a predetermined period, and the impedance of the dummy pull-up buffer unit 121 is determined. To do. The values of the pull-up side count signals P1 to P3 are stored in the storage circuit of the switching control circuit 127.

  Here, FIG. 4 is a schematic diagram focusing on the current path A after the impedance of the dummy pull-up buffer unit 121 is determined. However, as an example, consider a case where a standard as shown in FIG. The example of FIG. 5 is a buffer standard that allows a drive current of 8 mA to flow when the power supply voltage VDD = 1.8 V and Vds = 0.4 V (as described in FIG. 9), the output impedance of this buffer is the same as that of the transmission line. (Assuming that the characteristic impedance is 50Ω, 0.4V / 8 mA = 50Ω). In order to meet the conditions of this standard, as shown in FIG. 5, it can be seen that it is appropriate to add an external resistor equivalent to 175Ω to the buffer output. Impedance adjustment is performed using the dummy pull buffer unit 121 so that the impedance of the pull-up buffer unit 111 of FIG. 1 in this environment becomes 50Ω. Further, when setting the on-resistances of the PMOS transistors MP121 to MP123 of the dummy pull-up buffer unit 121, the set values of the on-resistances of the PMOS transistors MP111 to MP113 of the pull-up buffer unit 111 are ten times higher in order to increase the accuracy of impedance adjustment. Shall be set to

  As shown in FIG. 4, the on-resistance of the NMOS transistor MN132 of the switch circuit SW132 is 10Ω, and the value of the reference resistor Rref is 1740Ω (= 175Ω × 10 times−10Ω) in consideration of the on-resistance. Furthermore, the voltage of the reference voltage VREF1 is set to 1.4V. In this case, since the on resistance of the NMOS transistor MN132 is sufficiently lower than the impedance of the reference resistor Rref and the dummy pull-up buffer unit 121, it is considered that the reference resistor Rref and the ground terminal GND are substantially short-circuited. Can do.

  By setting such values, even if the on-resistance of the NMOS transistor MN132 fluctuates by ± 5Ω due to manufacturing variations, the influence of the dummy pull-up buffer unit 121 on the impedance of 500Ω is only about ± 1%. Absent. Therefore, the impedance adjustment accuracy of the dummy pull-up buffer unit 121 is hardly affected. Further, it can be considered that the influence of the NMOS transistor MN132 is sufficiently small with respect to the variation with respect to the reference resistance Rref. The above numerical value is merely an example, and the numerical value is not limited to this value as long as the on-resistance of the NMOS transistor MN132 can be considered to be sufficiently smaller than other resistance values.

  Next, in the second mode from time t2 to t3, since the mode control signal SEL is at a low level, the PMOS transistor MP131 of the switch circuit SW131 is turned on and the NMOS transistor MN132 of the switch circuit SW132 is turned off. In addition, the switching control circuit 125 electrically connects the external terminal TP2 and the node N123. Further, the switching control circuit 126 electrically connects the nodes N122 and N124. The switching control circuit 127 outputs the count output signal from the counter 124 as the pull-down side count signals N1 to N3, and outputs all the pull-up side count signals P1 to P3 as the low level. Further, the counter 124 counts up by high level input and counts down by low level input.

  FIG. 6 shows a configuration of the impedance adjustment unit 120 in which the switching control circuits 125 to 127 in the second mode are omitted. Hereinafter, the operation of the output impedance adjustment circuit 100 in the second mode will be described with reference to FIG.

  First, since the mode control signal SEL is at a low level, the PMOS transistor MP131 of the switch circuit SW131 is turned on, and the power supply terminal VDD and the external terminal TP1 are brought into conduction. Further, the NMOS transistor MN132 of the switch circuit SW132 is turned off, and the external terminal TP2 and the ground terminal GND are cut off. Further, since all the pull-up side count signals P1 to P3 are at the low level, all the PMOS transistors MP121 to MP123 of the dummy pull-up buffer unit 121 are turned off, and the power supply terminal VDD and the external terminal TP1 are cut off.

  Therefore, a current path including the power supply terminal VDD, the switch circuit SW131 (PMOS transistor MP131), the external terminal TP1, the reference resistor Rref, the external terminal TP2, the dummy pull-down buffer unit 122, and the ground terminal GND. A current flows through B.

  Further, the voltage VTP2 of the external terminal TP2 is input to the non-inverting input terminal of the comparator CMP121, and the reference voltage VREF2 is input to the inverting input terminal.

  In the initial state of the second mode, since the count value of the counter 124 is “0”, all count output signals are also at a low level. Accordingly, the pull-down count signals N1 to N3 are all at a low level, and as a result, all the NMOS transistors MN121 to MN123 of the dummy pull-down buffer unit 122 are turned off. For this reason, the voltage VTP2 of the external terminal TP2 becomes the power supply voltage VDD. Since the comparator CMP121 compares the voltage VTP2 with the reference voltage VREF2, the comparator CMP121 outputs a high level signal.

  Thereafter, an operation similar to the operation described with reference to FIG. That is, when the voltage VTP2 of the external terminal TP2 is higher than the reference voltage VREF2, the comparator CMP121 outputs a high level, and the counter 124 counts up according to the clock CLK. By this count-up operation, the same operation as described with reference to FIG. 12 is performed, and the on-state is turned on according to the pull-down count signals N1 to N3. Then, the counter 124 counts up until the voltage VTP2 of the external terminal TP2 falls below the reference voltage VREF2.

  Conversely, when the voltage VTP2 of the external terminal TP2 is lower than the reference voltage VREF2, the comparator CMP121 outputs a low level, and the counter 124 counts down according to the clock CLK. By this countdown operation, the operation is the same as that described with reference to FIG. 12, and the off state is set according to the pull-down count signals N1 to N3.

  By repeating the above operation, the voltage VTP2 of the external terminal TP2 becomes a value close to the reference voltage VREF2, and the pull-down count signals N1 to N3 are determined after a predetermined period, and the impedance of the dummy pull-down buffer unit 121 is determined. Note that the values of the pull-down count signals N1 to N3 are stored in the storage circuit of the switching control circuit 127.

  Here, FIG. 7 is a schematic diagram focusing on the current path B after the impedance of the dummy pull-down buffer unit 122 is determined. However, as an example, consider a case where a standard as shown in FIG. The example of FIG. 8 is a buffer standard that allows a drive current of 8 mA to flow when the power supply voltage VDD = 1.8 V and Vds = 0.4 V, as in FIG. In order to meet the conditions of this standard, it can be seen that it is appropriate to add an external resistor equivalent to 175Ω to the buffer output as shown in FIG. Impedance adjustment is performed using the dummy pull buffer unit 122 so that the impedance of the pull-up buffer unit 112 of FIG. 1 in this environment becomes 50Ω. Further, when setting the on-resistances of the NMOS transistors MN121 to MN123 of the dummy pull-down buffer unit 122, the on-resistances of the NMOS transistors MN111 to MN113 of the pull-down buffer unit 112 are set to 10 times the set value in order to increase the accuracy of impedance adjustment. It shall be.

  Further, as shown in FIG. 6, the on-resistance of the PMOS transistor MP131 of the switch circuit SW131 is 10Ω, and the value of the reference resistor Rref is 1740Ω (= 175Ω × 10 times−10Ω) in consideration of the on-resistance. Further, the voltage of the reference voltage VREF2 is set to 0.4V. In this case, since the ON resistance of the PMOS transistor MP131 is sufficiently lower than the impedance of the reference resistor Rref and the dummy pull-down buffer unit 122, it can be considered that the reference resistor Rref and the power supply terminal VDD are substantially short-circuited. it can.

  By setting such values, even if the on-resistance of the PMOS transistor MP131 fluctuates by ± 5Ω due to manufacturing variations, the dummy pull-down buffer unit 122 has only an influence of ± 1% on the impedance of 500Ω. . Therefore, the impedance adjustment accuracy of the dummy pull-down buffer unit 122 is hardly affected. Further, it can be considered that the influence of the PMOS transistor MP132 is sufficiently small with respect to the variation with respect to the reference resistance Rref. The above numerical value is an example, and the present invention is not limited to this numerical value as long as the on-resistance of the PMOS transistor MP131 can be considered to be sufficiently smaller than other resistance values.

  At times t1 to t3, the pull-up side count signals P1 to P3 and the pull-down side count signals N1 to N3 determined in the first and second modes are sent to the output buffer unit 110, respectively. Therefore, the impedances of the pull-up buffer unit 111 and the pull-down buffer unit 112 of the output buffer unit 110 are determined. As shown in FIG. 2, the first and second modes may be repeated after time t3. In this case, it is expected that the impedances of the pull-up buffer unit 111 and the pull-down buffer unit 112 of the output buffer unit 110 can be set more accurately.

  Here, the conventional output impedance adjustment circuit 1 has to use two external reference resistors, and cannot meet the demand for reduction in the number of mounted parts due to downsizing and cost reduction of the device. Further, in the output impedance adjustment circuit 2 disclosed in Patent Document 1, it is possible to reduce the number of external reference resistors, which is a problem in the output impedance adjustment circuit 1, but the reference resistance of the dummy pull-down buffer unit is reduced. The output impedance cannot be accurately adjusted due to manufacturing variations of PMOS transistors. For this reason, there is a possibility that the impedance adjustment accuracy of the output buffer is lowered and the quality of the signal to be transmitted from the output buffer to the transmission path is deteriorated.

  However, in the output impedance adjustment circuit 100 according to the present embodiment, the reference resistor is used as a calibration resistor when adjusting the impedance of the dummy pull-up buffer unit 121 and when adjusting the impedance of the dummy pull-down buffer unit 122. There is only one of Rref. For this reason, it is possible to reduce the number of mounted components, which has been a problem with the conventional output impedance adjustment circuit 1.

  Further, since the impedance adjustment of the dummy pull-up buffer unit 121 and the dummy pull-down buffer unit 122 can be performed based on the reference resistance Rref, the impedance that has been a problem in the output impedance adjustment circuit 2 disclosed in Patent Document 1 There is no problem that the adjustment accuracy decreases. As described above, the output impedance adjustment circuit 100 according to the present embodiment can solve the problems of both the conventional output impedance adjustment circuits 1 and 2 at the same time.

  Further, in the output impedance adjustment circuit 1, two comparators and counters have to be prepared on the dummy pull-up buffer side and the dummy pull-down buffer side. However, in the output impedance adjustment circuit 100 according to the present embodiment, the dummy pull-up buffer unit 121 and the dummy pull-down are controlled by a common comparator or counter by performing a control to switch the transmission path of each switching control circuit by the selector control signal SEL. The impedance of the buffer unit 122 can be adjusted. For this reason, the number of comparators and counters can be reduced, and the circuit scale can be reduced.

  Further, in the output impedance adjustment circuit 100, the impedance adjustment is performed by a method in which the dummy pull-up buffer unit 121 is turned off and the dummy pull-down buffer unit 122 is started in the initial state, and the impedance is sequentially decreased. As a result, the current consumption consumed in each mode can be minimized, and the power consumption can be reduced.

  Further, the PMOS transistor MP131 and the NMOS transistor MN132 of the switch circuits SW131 and SW132 can be used as an ESD protection element included in the device. Accordingly, it is not necessary to add a new transistor for the switch circuits SW131 and SW132, and an increase in circuit scale can be suppressed. Furthermore, by making each of the PMOS transistors MP131 and NMOS transistors MN132 of the switch circuits SW131 and SW132 open drains, there is a possibility that the size of the ESD protection element can be reduced as compared with the push-pull configuration.

  In addition, since it is possible to adjust the impedance of the dummy pull-up buffer unit 121 and the dummy pull-down buffer unit 122 using a common reference resistor, comparator, and counter, the adjustment is performed separately as in the output impedance adjustment circuit 1. Compared to the above, it is not affected by the manufacturing variation of each component (reference resistor, comparator, counter). For this reason, the impedance adjustment accuracy of the dummy pull-up buffer unit 121 and the dummy pull-down buffer unit 122 can be made equal.

  4 and 7, the final target impedance and the reference resistance Rref of the dummy pull-up buffer unit 121 and the dummy pull-down buffer unit 122 are used as the pull-up buffer unit 111 and the pull-down buffer of the output buffer unit 110, respectively. The final target impedance of the unit 112 is 10 times or more. As a result, the impedance of the output buffer unit 110 can be adjusted with high accuracy.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the reference voltage generation circuit 123 may generate one reference voltage and input the reference voltage to the inverting input terminal of the comparator CMP121. The counter 124 may be a shift register.

DESCRIPTION OF SYMBOLS 100 Output impedance adjustment circuit 110 Output buffer part 111 Pull-up buffer part 112 Pull-down buffer part 120 Impedance adjustment part 121 Dummy pull-up buffer part 122 Dummy pull-down buffer part 124 Counter 125-127 Switching control circuit SW131, SW132 Switch circuit CMP121
NAND circuit 111 to NAND113 NAND circuit OR111 to OR113 OR circuit IV121 to IV123 Inverter circuit MP111 to MP113 PMOS transistor MP121 to MP123 PMOS transistor MP131 PMOS transistor MN111 to MN113 NMOS transistor MN121 to MN123 NMOS transistor MN132 NMOS transistor R121 to R123 Resistor Rref Reference resistor TOB1 Output Terminals TP1, TP2 External terminals SEL Select control signals VREF1, VREF Reference voltage CLK Clock signal S1 Input buffer signals P1-P3 Pull-up side count signals N1-N3 Pull-down side count signals N121-N124 Nodes

Claims (8)

A first buffer connected between the output terminal and the first power supply line, the output impedance of which is set according to the first control signal;
A second buffer unit connected between the output terminal and a second power supply line, the output impedance of which is set according to a second control signal;
An external resistor,
A first external terminal to which one end of the external resistor is connected;
A second external terminal to which the other end of the external resistor is connected;
A first switch connected between the first external terminal and the first power supply line;
A second switch connected between the second external terminal and the second power supply line;
A first dummy buffer unit connected between the first external terminal and the first power supply line, the output impedance of which is adjusted according to the first control signal;
A second dummy buffer unit connected between the second external terminal and the second power supply line, the output impedance of which is adjusted according to the second control signal;
In the first mode, the first switch is turned on and the second switch is turned off, and the output impedance of the first dummy buffer section is set to a desired value according to the voltage of the first external terminal. Setting the first control signal to be adjusted;
In the second mode, the first switch is turned off and the second switch is turned on, and the output impedance of the second dummy buffer section is set to a desired value according to the voltage of the second external terminal. A control unit that sets the second control signal to be adjusted. The control unit includes a reference voltage generation circuit, a comparator, and a counter.
The reference voltage generation circuit outputs a reference voltage,
The comparator inputs the reference voltage to one input terminal, and outputs a comparison result with the voltage input to the other input terminal,
The counter counts up or down according to the comparison result of the comparator, and outputs the count signal.
In the first mode,
Connecting the first external terminal and the other input terminal of the comparator;
Using the count signal as the first control signal, adjusting the output impedance of the first dummy buffer unit,
In the second mode,
Connecting the second external terminal and the other input terminal of the comparator;
The impedance adjustment circuit according to claim 1, wherein the output impedance of the second dummy buffer unit is adjusted using the count signal as the second control signal. In the first mode, the control unit has a value of a count signal that is the first control signal adjusted in output impedance of the first dummy buffer unit, and in the second mode, the second signal The impedance adjustment circuit according to claim 2, further comprising a storage circuit that stores a value of a count signal that is the second control signal in which an output impedance of the dummy buffer unit is adjusted. The reference voltage generation circuit generates a first reference voltage and a second reference voltage,
In the first mode, the first reference voltage is input to one input terminal of the comparator,
4. The impedance adjustment circuit according to claim 2, wherein, in the second mode, the second reference voltage is input to one input terminal of the comparator. 5. An output impedance of a transistor constituting the first output buffer unit, an output impedance of a transistor constituting the first dummy buffer unit, and
5. The output impedance of a transistor constituting the second output buffer unit and an output impedance of a transistor constituting the second dummy buffer unit are each 10 times or more, 5. The impedance adjustment circuit according to the item. The first switch includes a first transistor of a first conductivity type,
The second switch includes a second transistor of a second conductivity type;
The impedance adjustment circuit according to claim 1, wherein each of the first and second transistors functions as an ESD element. A first buffer connected between the output terminal and the first power supply line, the output impedance of which is set according to the first control signal;
A second buffer unit connected between the output terminal and a second power supply line, the output impedance of which is set according to a second control signal;
An external resistor,
A first external terminal to which one end of the external resistor is connected;
A second external terminal to which the other end of the external resistor is connected;
A first switch connected between the first external terminal and the first power supply line;
A second switch connected between the second external terminal and the second power supply line;
A first dummy buffer unit connected between the first external terminal and the first power supply line, the output impedance of which is adjusted according to the first control signal;
A control method for an impedance adjustment circuit, comprising: a second dummy buffer unit connected between the second external terminal and the second power supply line and having an output impedance adjusted in accordance with the second control signal. Because
In the first mode, the first switch is turned on and the second switch is turned off, and the output impedance of the first dummy buffer section is set to a desired value according to the voltage of the first external terminal. Setting the first control signal to be adjusted;
In the second mode, the first switch is turned off and the second switch is turned on, and the output impedance of the second dummy buffer section is set to a desired value according to the voltage of the second external terminal. A method for controlling an impedance adjustment circuit, wherein the second control signal is set so as to be adjusted. The first switch is turned on, the second switch is turned off, the first control signal is set according to the voltage of the first external terminal, and the first switch is turned off. The control of the impedance adjustment circuit according to claim 7, wherein the second switch is turned on, and the period for setting the second control signal is different from each other according to the voltage of the second external terminal. Method.

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