JP2011210817A - Method of manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem of a thin film transistor where a contact layer consisting of microcrystalline semiconductor is provided between the source/drain electrode and an active layer that irregularities are formed on the surface of the contact layer which is formed by the direct deposit method, an off-leak current is generated because the film thickness of a recess becomes thin, and thereby the electrical properties degrade, meantime, an area where the irregularities on the surface of the contact layer cannot be covered with the active layer 5 occurs when deposition is carried out until a film thickness required for the recess in the contact layer to suppress the off-leak current is attained, and that area becomes the resistance when an on-current flows.SOLUTION: After deposition is carried out until a film thickness sufficient for the recess in the contact layer 4 to suppress the off-leak current is attained, its surface is planarized to form an active layer. Consequently, the surface of the contact layer 4 can be covered with the active layer 5 substantially uniformly, and since the off-leak current is reduced, a TFT having the characteristics of large on-current can be obtained.

Description

  The present invention relates to a method for manufacturing a thin film transistor.

  Thin film transistors (hereinafter referred to as TFTs) are widely used as drive elements and switching elements of display devices, and have been devised to obtain electrical characteristics according to applications. In Patent Document 1, a contact layer made of a microcrystalline semiconductor containing an impurity is provided between a source electrode and a drain electrode (hereinafter referred to as a source / drain electrode) and an active layer in order to increase an on-current. Provided TFTs are disclosed. Compared with an amorphous semiconductor conventionally used as a contact layer, a microcrystalline semiconductor has a higher electric conductivity, and therefore the resistance between the active layer and the source / drain electrodes can be further reduced. As a result, in the on state of the TFT, carriers easily move between the source / drain electrodes and the channel region, so that the leakage current flowing outside the channel region is reduced and the on-current can be increased. In Patent Document 1, an n + type microcrystalline silicon film having a thickness of 70 nm is formed as a contact layer by a plasma CVD method (plasma chemical vapor deposition method).

JP-A-9-153621

  When a microcrystalline film such as silicon is formed by a direct deposition method such as a plasma CVD method, a columnar crystal grows in a direction perpendicular to the substrate (film thickness direction) as the film thickness increases, and the direction parallel to the substrate ( It is known that it does not grow very large in the plane direction). Although depending on the film formation conditions, for example, when a microcrystalline silicon film having a thickness of 10 nm or more which is preferable as a contact layer is formed, irregularities having an average surface roughness (Ra) larger than 1.6 nm are formed on the surface. These irregularities are related to the crystal grains of microcrystalline silicon, the convex part corresponds to the position of the maximum grain size in the film thickness direction of each crystal grain, and the concave part corresponds to the position of each crystal grain boundary. It is done. The crystal grain boundary is less likely to be thicker than other portions. This is presumably because the crystal grains collide with each other at the crystal grain boundary and are in a high energy state, and it is difficult to form a film. Therefore, as the film thickness increases, crystal grains grow in the film thickness direction and the convex part becomes high, but the film is difficult to form in the concave part, and the height difference (average roughness) between the concave part and the convex part increases. .

  If the contact layer recess is thin, when the off-voltage is applied to the gate electrode of the TFT, carriers flowing from the active layer to the source electrode / drain electrode cannot be blocked by the recess of the contact layer. An electric current is generated. When the film is formed until the film thickness of the recess becomes sufficient to suppress the occurrence of off-leakage current, the unevenness increases as described above. Therefore, the active layer formed over the contact layer (microcrystalline semiconductor layer) cannot cover the unevenness of the microcrystalline semiconductor layer, and there is no active layer or a thin portion is formed. A portion where the active layer is not present or thin becomes a resistance when an on-current flows in the plane direction in the active layer, and the on-current is reduced to deteriorate the electrical characteristics of the TFT.

The present invention has been made to solve the above problems, and a method for manufacturing a top-gate thin film transistor according to the present invention includes:
Forming a source electrode and a drain electrode on the substrate;
Forming a contact layer made of a microcrystalline semiconductor containing impurities on each of the source electrode and the drain electrode;
Forming an active layer on the contact layer;
Forming an insulating layer on the active layer;
Forming a gate electrode on the insulating layer;
A method of manufacturing a thin film transistor having
A step of planarizing the surface of the contact layer is provided between the step of forming the contact layer and the step of forming the active layer.

  According to the present invention, the unevenness of the contact layer can be reduced by planarizing the surface of the contact layer made of a microcrystalline semiconductor before forming the active layer. Thereby, the contact layer can secure a film thickness sufficient to suppress the off-leakage current, and the unevenness on the surface of the contact layer can be suppressed to a range in which the active layer can cover the contact layer. As a result, it is possible to provide a top gate TFT having excellent characteristics.

Schematic which shows the cross section of TFT which concerns on this invention. Sectional drawing which shows schematically the manufacturing method of TFT which concerns on embodiment of this invention. The graph which shows the relationship between Ra of TFT formed in the Example, and an off-leakage current.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same or corresponding members are denoted by the same reference numerals, and redundant description of members once described is omitted.

  FIG. 1 is a schematic sectional view of a TFT formed by the manufacturing method according to the present invention. In FIG. 1, 1 is a substrate, 2 is a protective layer, 3 is a source / drain electrode, 4 is a contact layer (microcrystalline semiconductor layer), 5 is an active layer, 6 is a gate insulating film, and 7 is a gate electrode. A indicates the surface subjected to the flattening process.

  The off-leakage current is considered to be generated when carriers flow from the active layer to the source / drain electrodes when a voltage for turning off the TFT is applied to the gate electrode 7. Therefore, in order to suppress off-leakage current, a contact layer made of a semiconductor layer containing impurities is provided between the active layer 5 and the source / drain electrode 3 to suppress carrier flow from the active layer 5 to the source / drain electrode 3. To do. However, if the contact layer 4 has an insufficient thickness, some carriers flow into the source / drain electrode 3 due to the tunnel effect, and an off-leakage current is generated.

  Even if the contact layer 4 is formed with a film thickness sufficient to suppress the off-leakage current, the off-leakage current can be reduced. However, as the film thickness of the contact layer 4 increases, the grain size of the microcrystalline semiconductor increases and the irregularities on the surface of the contact layer 4 increase, so that it becomes difficult to cover the contact layer 4 with the active layer 5. In the case of a plasma CVD method used for forming an active layer, it is difficult to form a film on a steep portion, and it is difficult to form a film with a uniform thickness on a surface with large irregularities. Therefore, the thickness of the active layer 5 is reduced at the steep portion of the surface of the contact layer 4, and the thin portion of the active layer 5 becomes a resistance when the on-current flows in the plane direction, and the electrical characteristics of the TFT are deteriorated. .

  Therefore, in the present invention, the active layer is formed by flattening the surface of the contact layer 4 until the thickness of the concave portion is sufficient to suppress the flow of carriers when the contact layer 4 is turned off. Thereby, the surface of the contact layer 4 can be almost uniformly covered with the active layer 5. As a result, off-leakage current is reduced, and a TFT having a large on-current characteristic can be obtained.

  Next, a manufacturing method of a TFT according to the present invention will be described with reference to FIG. 2, taking as an example a film mainly composed of silicon as a contact layer and an active layer. The contact layer and the active layer are not limited to films containing silicon as a main component, and known semiconductor materials can be used. The crystalline silicon film in the present invention refers to a silicon film in which a Raman shift is observed at 520 cm −1 by Raman spectroscopy, and the volume fraction of crystals obtained from the Raman spectrum is 20% or more. A crystalline silicon having a crystal grain size of about 1 to 100 nm is called microcrystalline silicon. Even if a Raman shift is observed at 520 cm −1, amorphous silicon is used when the crystal volume fraction is 20% or less, and amorphous silicon is used when no Raman shift is observed at 520 cm −1. The volume fraction is Jpn. J. et al. Appl. Phys. Vol. 32 (1993) p. It can be calculated based on the equation (1) described in 4908.

  First, it is made of silicon oxide (SiO2), silicon nitride (SiNx), or the like on an insulating substrate 1 such as refractory glass, quartz, or ceramic, or a conductive substrate 1 such as silicon or SUS by plasma CVD or sputtering. An insulating protective layer 2 is formed (FIG. 2A). When a protective film is formed by plasma CVD, a mixed gas of tetraethoxysilane (TEOS) and oxygen (O2) is used as a material gas for SiO2, and silane (SiH4) and ammonia (NH3) are used as a material gas for SiNx. A mixed gas of nitrogen (N2) can be preferably used. The film forming conditions of SiNx are generally 0.1 to 10 W / cm 2 as RF power density, more preferably 0.5 to 5 W / cm 2, and pressure is generally 0.5 to 5 Torr. Desirably, it is 0.7-2 Torr.

  Next, a conductive layer to be the source / drain electrode 3 is formed to have a thickness of 10 to 300 nm by sputtering or vacuum deposition. The material of the conductive layer includes molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), tantalum (Ta), copper (Cu), aluminum (Al), or those An alloy or a laminated film thereof is preferable. After a desired shape pattern is formed on the conductive layer with a resist, an unnecessary conductive layer is removed by a dry etching method or a wet etching method to form a pair of source / drain electrodes 3 having a desired shape (see FIG. 2 (b)).

  Next, an n + type microcrystalline silicon film to be the contact layer 4 is formed on the source / drain electrode 3 by a plasma CVD method (FIG. 2C). Since the preferable film thickness of the contact layer 4 is 10-300 nm, More preferably, it is 20-100 nm, Therefore It forms until the film thickness of the recessed part of the contact layer 4 becomes more than this. The deposition conditions suitable for forming the microcrystalline silicon film are an RF power density of 0.05 to 1 W / cm 2, more preferably 0.1 to 0.8 W / cm 2. The pressure is 1.0 to 10 Torr, more preferably 1.5 to 9 Torr. A silicon-containing gas such as SiH 4, disilane (Si 2 H 6), SiH 2 Cl 2, tetrafluorosilane (SiF 4), or SiH 2 F 2 can be used as a material gas, and hydrogen (H 2) gas or an inert gas can be used as a dilution gas. For film formation of microcrystalline silicon, the hydrogen dilution rate of the silicon-containing gas, that is, (H2 flow rate) / (silicon-containing material gas flow rate) is an important parameter, and the hydrogen dilution rate is 100 to 10,000, preferably 300. ~ 3000. As the impurity-added gas, PH3, phosphorus fluoride (PF3), arsine (AsH3), arsenic fluoride (AsF5), or the like can be used. The doping amount of n + type microcrystalline silicon preferable as the contact layer is about 1%.

  Since the surface of the formed contact layer 4 has an uneven shape, a flattening process is performed. In the planarization step, chemical polishing, mechanical polishing, chemical mechanical polishing (CMP) combining them, plasma treatment, or the like can be used. The surface A after the flattening step preferably has an average surface roughness Ra ≦ 1 nm in a 5 μm square when observed with an atomic force microscope (AFM). After the planarization treatment, the contact layer 4 is patterned into a desired shape covering the source / drain electrode 3 by using the same method as that for the source / drain electrode 3 (FIG. 2D).

  Next, the active layer 5 is formed using a plasma CVD method. Any silicon film of amorphous silicon, amorphous silicon, or crystalline silicon can be applied to the active layer 5. The film thickness of the active layer 5 is 20 to 300 nm, more preferably 50 to 200 nm. The film forming conditions suitable for forming the amorphous silicon to be the active layer 5 are RF power density of 0.01-1 W / cm 2, more preferably 0.01-0.3 W / cm 2, pressure 0.5-5 Torr, and more. Preferably, it is 0.7 to 2.0 Torr. A silicon-containing gas such as SiH 4, Si 2 H 6, SiH 2 Cl 2, SiF 4, or SiH 2 F 2 can be suitably used as the material gas, and H 2 gas or an inert gas can be suitably used as the dilution gas. The hydrogen dilution rate of the silicon-containing gas is 1 to 20, more preferably 1 to 15. The film formation conditions for forming crystalline silicon as the active layer 5 are the same as the film formation conditions for the microcrystalline silicon film of the contact layer 4 except that no impurity-added gas flows. The active layer 5 is also patterned by the same method as the source / drain electrode 3 so as to cover a part of each of the pair of contact layers 4 and between the pair of source / drain electrodes 3 (FIG. 2E). .

  Subsequently, a gate insulating film 6 that covers the active layer 5 to the end is formed by plasma CVD or sputtering. The film thickness is preferably 50 to 300 nm. As a material of the gate insulating film 6, SiO2 or SiNx is preferably used. When forming the SiO2 film or SiNx film by the plasma CVD method, the same conditions as those for the protective layer 2 can be used. A gate electrode 7 having a film thickness of 100 to 600 nm is formed on the gate insulating film 6 by Al, Cr, Ti, Mo, Ta, an alloy thereof, or a laminated film thereof by sputtering or vacuum deposition. Is deposited. Thereafter, the gate electrode 7 is patterned by the same method as that for the source / drain electrode 3 (FIG. 2G).

  Finally, contact holes for electrical connection with the source / drain electrodes 3 are formed in the gate insulating film 6 and the contact layer 4 by the same etching method as that for the source / drain electrodes 3 to complete the TFT.

(Experimental example)
A top gate type TFT was formed by the manufacturing method according to the present invention and evaluated. First, as shown in FIG. 2A, an SiNx film serving as a protective layer 2 was formed on a glass substrate 1 as an insulating substrate by a plasma CVD method to a thickness of about 200 nm. The film formation conditions were as follows: SiH4 as a material gas, 160 sccm of N2, 2000 sccm of N2, and 1000 sccm of NH3, a pressure of 1.6 Torr, an RF power of 2000 W, and a set temperature of 395 ° C.

  Next, as shown in FIG. 2B, about 30 nm of Mo was formed on the protective layer 2 by sputtering, and then patterned into island shapes to form the source / drain electrodes 3. Subsequently, as shown in FIG. 2C, an n + type microcrystalline silicon film to be the contact layer 4 was formed on the source / drain electrode 3 by a plasma CVD method to a thickness of about 50 nm. The film forming conditions were a pressure of 9 Torr, an RF power of 300 W, and a set temperature of 200 ° C. Further, SiH4, PH3, and H2 are used as the material gas, and the flow rate ratio is set to SiH4: PH3: H2 = 100: 1: 100000 so that it is included in the range of the hydrogen dilution rate for obtaining a film of high-quality microcrystalline silicon. (The hydrogen dilution rate was 1000). The film thickness of the obtained n + type microcrystalline silicon film was 48.9 nm at the concave portions, 54.2 nm at the convex portions, and the average roughness of the surface was Ra = 1.8 nm.

  Subsequently, the surface of the n + type microcrystalline silicon film was polished and planarized using CMP. As a polishing material, a general silicon final slurry was used, and polishing was performed at a rotation speed of 90 rpm and a pressure of 4 psi to form a contact layer 4. The average roughness of the surface A of the contact layer 4 after polishing was Ra = 0.9 nm, and the average film thickness was 30 nm. Subsequently, as shown in FIG. 2D, the contact layer 4 was patterned with a resist in an island shape covering the source / drain electrodes 3 up to the ends, and was patterned using dry etching.

  Next, as shown in FIG. 2E, an amorphous silicon layer was formed as the active layer 5 by plasma CVD. After forming an amorphous silicon layer to a thickness of about 50 nm by plasma CVD so as to cover the protective layer 2 and the contact layer 4, a part of each of the pair of contact layers 4 is formed in the same manner as the source / drain electrode 3. And patterning so as to cover between the pair of source / drain electrodes 3. The amorphous silicon layer was formed under the conditions of a pressure of 1 Torr, an RF power of 150 W, a set temperature of 395 ° C., and material gases of SiH4 of 225 sccm and H2 of 1000 sccm.

  Subsequently, as shown in FIG. 2F, a gate insulating film 6 was formed to a thickness of about 200 nm by plasma CVD. The film formation conditions were a pressure of 1.3 Torr, an RF power of 1100 W, a set temperature of 395 ° C., and material gases of SiH 4 of 100 sccm, N 2 of 3500 sccm, and NH 3 of 500 sccm.

  Finally, about 100 nm of Mo was formed on the gate insulating film 6 by sputtering, and patterned into an island shape to form the gate electrode 7. Thereafter, as shown in FIG. 2G, the gate insulating film 6 was etched to form contact holes for electrical connection to the source / drain electrodes, thereby completing the TFT.

  The electrical characteristics of the TFT manufactured by the above method were measured. For the measurement, a 4155C semiconductor parameter analyzer manufactured by Agilent was used, and the TFT was placed on a stage maintained at 25 ° C. Measurement conditions were such that the gate voltage was swept from −10 V to +15 V with 0 V applied to the source electrode and 0.1 V, 1 V, and 10 V applied to the drain electrode, respectively. The characteristic obtained in this manner was used as the VG-ID characteristic of the TFT.

(Comparative example)
A TFT was formed in the same manner as in the experimental example except that the step of planarizing the surface of the semiconductor layer containing impurities was omitted, and the VG-ID characteristics were similarly evaluated. The average roughness of the surface is Ra = 1.8 nm.

  In the above VG-ID characteristics, when the drain voltage is 10 V and the gate voltage is −10 V, the TFT of the experimental example subjected to the planarization process has a drain current of about 2 compared to the TFT of the comparative example not subjected to the planarization process. Decreased by orders of magnitude. FIG. 3 shows the relationship between Ra and off-leakage current for each of the experimental example and the comparative example. As can be seen from FIG. 3, the off-leakage current was significantly reduced in the flattened sample, and it was found that the TFT showed good characteristics.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Protective layer 3 Source / drain electrode 4 Contact layer 5 Active layer 6 Gate insulating layer 7 Gate electrode A Planarized surface

Claims (2)

Forming a source electrode and a drain electrode on the substrate;
Forming a contact layer made of a microcrystalline semiconductor containing impurities on each of the source electrode and the drain electrode;
Forming an active layer on the contact layer;
Forming an insulating layer on the active layer;
Forming a gate electrode on the insulating layer;
A method of manufacturing a thin film transistor having
A method of manufacturing a thin film transistor, comprising a step of planarizing a surface of the contact layer between the step of forming the contact layer and the step of forming the active layer.   2. The thin film transistor according to claim 1, wherein the step of forming the contact layer and the step of forming the active layer are steps of forming a layer mainly composed of silicon using a plasma CVD method. Manufacturing method.