JP2011209902A - Instruction fetch device, instruction packet generation device, processor, and instruction fetch method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control instruction pre-fetch by using information relating to a branch instruction.SOLUTION: A program is managed by an instruction packet divided into command payloads with fixed length to each of which an instruction header is added. The instruction packet includes a branch prediction flag, and when this branch prediction flag indicates "1", the instruction pre-fetch of a next line from a next line pre-fetch part 150 to a system memory 140 is suppressed. The branch prediction flag is a field indicating that such possibility that the branch instruction may exist in the corresponding instruction payload, and that the branch destination may be other than the instruction payload or the next instruction payload is high. Also, the arrangement of the branch instruction can be changed by performing compression using an instruction dictionary table 192 in order to prevent the branch prediction flag from being set to "1" in the continuous instruction packets.

Description

  The present invention relates to an instruction fetch device, and more particularly to an instruction fetch device for prefetching an instruction sequence including a branch instruction, an instruction packet generation device, a processor, a processing method therefor, and a program for causing a computer to execute the method.

  In order to maximize the processing capability of a pipelined CPU (Central Processing Unit), it is ideal that instructions in the pipeline continue to flow without delay. In order to maintain this ideal state, it is necessary to fetch an instruction from a memory storing an instruction to be processed next to a CPU or an instruction cache in advance. However, when a branch instruction is included in the program, the address of the instruction to be executed next to the branch instruction is not fixed until the branch instruction is executed. For this reason, instruction install is awaited, pipeline installation occurs, and instruction execution throughput decreases. For this reason, many CPUs have been devised to perform prefetching and suppress the occurrence of pipeline installation while there are uncertain elements due to branching.

  A typical prefetch that can be realized by simple hardware is next-implement fetch (see, for example, Patent Document 1). This is a method of prefetching instructions in the order of the program. In the instruction fetch of the processor, the basic memory access pattern is to access the memory in a direction in which the addresses continuously increase. For this reason, the prefetch by hardware is a method in which after the instruction at a certain address is stored in the cache, the next cache line is automatically stored with the expectation that the next cache line will also be used.

Japanese Patent No. 4327237 (FIG. 1)

  Although the above-described next-implementation fetch can be realized with a simple hardware configuration, prefetching is performed on the premise that no branching occurs, and in many cases, useless prefetching, that is, prefetch miss occurs. When such a prefetch miss occurs, the prefetched instruction is discarded, and the correct branch destination instruction is fetched again. Therefore, there is a time disadvantage that the CPU waits. In addition, since extra data is read and written, memory access increases and power loss occurs. Furthermore, frequent prefetching and useless prefetching also cause a problem of congesting data path traffic.

  Another attempt to reduce prefetch misses uses branch prediction. In the next-implement fetch, the next line is prefetched by predicting that the branch will not always be branched, but the branch direction is predicted from the past history, and the predicted address is prefetched. Branch prediction is complicated and requires hardware with a large circuit area such as a history table. However, the performance benefit achieved by branch prediction depends on the efficiency of the prediction algorithm, and many of the prediction algorithms need to be implemented with relatively large storage devices and complex hardware. If the branch prediction is also unpredictable, a penalty similar to the next implicit fetch occurs. In most actual programs, the branch ratio to each branch destination, such as loop processing and exception processing, is highly biased, and the benefits of branch prediction often outweigh the disadvantages. However, depending on the application, no matter what prediction algorithm is used, it is difficult to improve the prediction performance. In particular, the codec tends to be difficult to predict other than the loop. Although the prediction hit rate must be improved, the mechanism for this is complicated and large-scale, but the performance improvement corresponding to the circuit scale is not always obtained.

  Unlike the above-described method in which prefetching is performed in only one direction, a method is also considered in which prefetching is eliminated by prefetching both directions at the branch destination without performing prediction. In this case, compared to the branch prediction method, the pipeline installation can be eliminated with a small hardware configuration addition. However, not only does the amount of stored data for prefetching simply double, but it also means that unnecessary data is always read, and the adverse effects of increased data path congestion, the complexity of adding redundant circuits, Loss cannot be ignored.

  As described above, how prefetching is performed has its demerits (CPU mounting cost, branch prediction processing overhead) and merits (expected throughput improvement), and there is a trade-off between cost and performance.

  The present invention has been made in view of such a situation, and an object of the present invention is to control instruction prefetch using information related to a branch instruction.

  The present invention has been made to solve the above problems, and a first aspect of the present invention is that the instruction payload includes an instruction payload obtained by dividing an instruction sequence of a program for each predetermined size and a branch instruction included in the instruction payload. Or an instruction packet holding unit for holding an instruction packet including an instruction header including branch prediction information indicating a high possibility of branching to an instruction not included in any of the next instruction payloads; and the instruction packet holding unit An instruction packet separator for separating the instruction packet held in the instruction payload and the instruction header, and a branch included in the instruction payload corresponding to the instruction header based on the branch prediction information included in the instruction header An instruction can branch to an instruction that is not included in either the instruction payload or the next instruction payload. A branch prediction information determination unit for instructing prefetch suppression of the next instruction packet when it is determined that the prefetch is high, and an instruction prefetch unit for executing prefetch of the next instruction packet unless the prefetch suppression is instructed. An instruction fetch method comprising an instruction fetch device or a processing procedure corresponding to the instruction fetch device. This brings about the effect of controlling whether or not to prefetch the next instruction packet based on the branch prediction information.

  Further, in this first aspect, based on an instruction dictionary reference instruction included in the instruction payload separated by the instruction packet separation unit, an instruction sequence corresponding to the instruction dictionary reference instruction is read from the instruction dictionary table and decompressed. An instruction execution unit may be further provided. As a result, the command sequence table is expanded using the command dictionary table.

  In addition, in the first aspect, an instruction expansion unit that expands an instruction sequence from an instruction payload corresponding to the instruction header based on an instruction payload compression flag included in the instruction header may be further provided. As a result, the instruction payload compressed based on the instruction payload compression flag is expanded.

  The second aspect of the present invention provides an instruction payload that is not included in either the instruction payload or the next instruction payload by a branch instruction included in the instruction payload obtained by dividing a program instruction sequence for each predetermined size and the instruction payload. An instruction packet holding unit that holds an instruction packet including an instruction header including branch prediction information indicating a high possibility of branching to the instruction packet, and the instruction packet held in the instruction packet holding unit Based on the instruction packet separation unit that separates into the instruction header, the instruction execution unit that executes the instruction sequence included in the instruction payload separated by the instruction packet separation unit, and the branch prediction information included in the instruction header Depending on the branch instruction included in the instruction payload corresponding to the instruction header, the instruction payload or If it is determined that there is a high possibility of branching to an instruction that is not included in any of the instruction payloads, a branch prediction information determination unit that instructs prefetch suppression of the next instruction packet; And an instruction prefetch unit that executes prefetching of the instruction packet and supplies the next instruction packet to the instruction packet separation unit. This brings about the effect of controlling whether or not to prefetch the next instruction packet based on the branch prediction information in the processor having the instruction execution unit.

  According to a third aspect of the present invention, there is provided an instruction packet generation unit that generates an instruction packet including an instruction payload obtained by dividing a command sequence of a program into predetermined sizes and an instruction header, and the instruction payload for each instruction payload. Branch prediction information that sets branch prediction information indicating the likelihood of branching to an instruction not included in either the instruction payload or the next instruction payload by the branch instruction included in the instruction header corresponding to the instruction payload An instruction packet generation device comprising: an information setting unit; and an instruction packet holding unit that holds an instruction packet including an instruction header in which the branch prediction information is set. This brings about the effect that branch prediction information for determining whether or not to prefetch the next instruction payload is included in the instruction header.

  Further, in the third aspect, the fact that the branch prediction information in two consecutive instruction packets is likely to branch to an instruction that is not included in either the instruction payload of the instruction packet or the next instruction payload. In the case shown, an instruction compression unit may be further included that compresses the instruction between the two branch instructions so that the two branch instructions included in the two instruction packets respectively fit in the same instruction payload. This brings about the effect of reducing the case where it is determined that the next instruction payload is not prefetched and improving the instruction issue rate.

  According to the present invention, it is possible to obtain an excellent effect that instruction prefetch can be controlled by using information related to a branch instruction.

It is a figure which shows the example of a pipeline structure of the processor in the 1st Embodiment of this invention. It is a figure which shows the block structural example of the processor in the 1st Embodiment of this invention. It is a figure which shows the structural example of the instruction packet 300 in the 1st Embodiment of this invention. It is a figure which shows the example of a field structure of the instruction header 310 in the 1st Embodiment of this invention. It is a figure which shows the example of a setting of the branch prediction flag 311 used in the 1st Embodiment of this invention. It is a figure which shows the example of application of the instruction dictionary table reference type compression used in the 1st Embodiment of this invention. It is a figure which shows the example of a change of the branch prediction flag 311 by the instruction dictionary table reference compression in the 1st Embodiment of this invention. It is a figure which shows the function structural example for the instruction | indication packet generation in the 1st Embodiment of this invention. It is a figure which shows the example of a process sequence for the command packet production | generation in the 1st Embodiment of this invention. It is a figure which shows the function structural example for the instruction execution in the 1st Embodiment of this invention. It is a figure which shows the example of a process sequence for the instruction execution in the 1st Embodiment of this invention. It is a figure which shows the modification of the field structure of the instruction header 310 in the 1st Embodiment of this invention. It is a figure which shows the example of a relationship between arrangement | positioning of the branch instruction and instruction prefetch start position in the 2nd Embodiment of this invention. It is a figure which shows the structural example using the prefetch start address setting register in the 2nd Embodiment of this invention. It is a figure which shows the structural example using the instruction prefetch timing field 312 of the instruction header 310 in the 2nd Embodiment of this invention. It is a figure which shows the structural example which utilizes the instruction execution of the predetermined number of times for the prefetch timing in the 2nd Embodiment of this invention. It is a figure which shows the example which set the instruction type and the frequency | count of execution to the instruction header 310 in the 2nd Embodiment of this invention. It is a figure which shows the function structural example for the instruction execution in the 2nd Embodiment of this invention. It is a figure which shows the example of a process sequence for the instruction execution in the 2nd Embodiment of this invention. It is a figure which shows the function structural example of the addition control process of the program counter in the 3rd Embodiment of this invention. It is a figure which shows the structural example of the addition control register 640 in the 3rd Embodiment of this invention. It is a figure which shows the example of a processing mode of the instruction | indication by the two-way branch in the 3rd Embodiment of this invention. It is a figure which shows the example of a processing mode of the instruction | indication by the multiway branch in the 3rd Embodiment of this invention. It is a figure which shows an example of the instruction set for setting a value to the addition control register 640 in the 3rd Embodiment of this invention. It is a figure which shows the example at the time of setting a value to the addition control register 640 by the conditional branch instruction in the 3rd Embodiment of this invention. It is a figure which shows the example at the time of setting a value to the addition control register 640 by the control register change instruction PCINCMODE in the 3rd Embodiment of this invention. It is a figure which shows the example of a process sequence for the instruction execution in the 3rd Embodiment of this invention. It is a figure which shows the pipeline structural example of the processor in the 4th Embodiment of this invention. It is a figure which shows the block structural example of the processor in the 4th Embodiment of this invention. It is a figure which shows the relationship between the branch instruction and cache line in the 4th Embodiment of this invention. It is a figure which shows one aspect | mode of the change of the instruction arrangement in the 4th Embodiment of this invention. It is a figure which shows the function structural example for the instruction | indication arrangement | positioning in the 4th Embodiment of this invention. It is a figure which shows the example of a process sequence for the instruction arrangement | positioning in the 4th Embodiment of this invention. It is a figure which shows the example of a setting of the prefetch address register in the 4th Embodiment of this invention. It is a figure which shows the function structural example for the instruction execution in the 4th Embodiment of this invention. It is a figure which shows the example of a process sequence for the instruction execution in the 4th Embodiment of this invention.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (instruction prefetch suppression control using branch prediction information)
2. Second Embodiment (Instruction Prefetch Timing Control)
3. Third embodiment (instruction prefetch penalty averaging by mixing instructions)
4). Fourth Embodiment (Avoiding cache line collision by fixing the arrangement of branch destination cache lines)
5. Combination of each embodiment

<1. First Embodiment>
[Processor configuration]
FIG. 1 is a diagram illustrating a pipeline configuration example of a processor according to the first embodiment of the present invention. In this example, an instruction fetch stage (IF) 11, an instruction decode stage (ID) 21, a register fetch stage (RF) 31, an execution stage (EX) 41, and a memory access stage (MEM) 51 are included. A pipeline is assumed. Each pipeline is delimited by latches 19, 29, 39 and 49, and pipeline processing is performed in synchronization with the clock.

  In an instruction fetch stage (IF) 11, instruction fetch processing is performed. In the instruction fetch stage 11, the program counter (PC) 18 is sequentially added by the adder 12, and the instruction indicated by the program counter 18 is supplied to the next instruction decode stage 21. The instruction fetch stage 11 includes an instruction cache described later, and performs instruction prefetching to the instruction cache. The next-implement fetch unit 13 is for prefetching the next line, which is the cache line next to the cache line including the instruction currently being executed.

  In the instruction decode stage (ID: Instruction Decode) 21, the instruction supplied from the instruction fetch stage 11 is decoded. The result decoded in the instruction decode stage 21 is supplied to a register fetch stage (RF) 31. In the case of a branch instruction, the branch destination address is supplied to a program counter (PC) 18.

  In a register fetch stage (RF: Register Fetch) 31, an operand fetch process necessary for instruction execution is performed. In a pipeline type processor, the operand access target is often limited to a register file. Operand data acquired in the register fetch stage 31 is supplied to an execution stage (EX) 41.

  In the execution stage (EX: EXecute) 41, instruction execution is performed using operand data. For example, arithmetic logic operations and branch determination processing are performed. The execution result data obtained in the execution stage (EX) 41 is stored in a register file. In the case of a store instruction, the memory access stage (MEM) 51 writes to the memory.

  In a memory access stage (MEM: Memory) 51, access to the memory is performed. In the case of a load instruction, read access from the memory is performed, and in the case of a store instruction, write access to the memory is performed.

  FIG. 2 is a diagram illustrating a block configuration example of the processor according to the first embodiment of the present invention. This processor includes a processor core 110, an instruction cache 120, a data cache 130, a next implementation fetch unit 150, and a packet demultiplexer 160. The processor further includes a prefetch queue 170, an instruction queue 180, an instruction dictionary index 191, and an instruction dictionary table 192. A system memory 140 is connected to this processor.

  The processor core 110 has a main mechanism as a processor excluding the instruction fetch function, and includes a program counter 111, an instruction register 112, an instruction decoder 113, an execution unit 114, and a register file 115. The program counter 111 is a counter that sequentially counts the addresses of instructions to be executed. The instruction register 112 is a register that holds an instruction to be executed by the instruction indicated by the program counter 111. The instruction decoder 113 is a decoder that decodes an instruction held in the instruction register 112. The execution unit 114 executes the instruction decoded by the instruction decoder 113. The register file 115 is a storage area that holds operands and the like necessary for instruction execution in the execution unit 114.

  The instruction cache 120 is a cache memory that holds a copy of instructions stored in the system memory 140. When accessing an instruction from the processor core 110, the instruction cache 120 can be accessed at a higher speed than the system memory 140. Therefore, it is desirable to hold the instruction in the instruction cache 120 as much as possible. When a necessary instruction is held in the instruction cache 120, it is called a hit, and when it is not held, it is called a miss.

  The data cache 130 is a cache memory that holds a copy of data stored in the system memory 140. When accessing data from the processor core 110, the data cache 130 can be accessed at a higher speed than the system memory 140. Therefore, it is desirable to store instructions in the data cache 130 in advance as much as possible. As in the case of the instruction cache 120, when the necessary data is held in the data cache 130, it is called a hit, and when it is not held, it is called a miss. Unlike the instruction cache 120, the data cache 130 is also used for write access.

  The next implement fetch unit 150 is for prefetching the next cache line, which is the next cache line, from the system memory 140 to the instruction cache 120 as an instruction expected to be required in advance. The next implement fetch unit 150 corresponds to the next implement fetch unit 13 in the pipeline configuration, and belongs to the instruction fetch stage (IF) 11. The next-implement fetch unit 150 monitors the state of the program counter 111 and issues a prefetch request for the cache line of the instruction cache 120 to the system memory 140 at an appropriate timing.

  The packet demultiplexer 160 separates the instruction packet read from the system memory 140 into an instruction header and an instruction payload. Although the structure of the instruction packet will be described later, the instruction cache line is included in the instruction payload.

  The prefetch queue 170 is a queue that holds a cache line of instructions included in the instruction payload. The cache lines held in the prefetch queue 170 are held in the instruction cache 120 in order from the top.

  The instruction queue 180 is a queue that holds a cache line of instructions read from the instruction cache 120 according to the program counter 111.

  The instruction dictionary index 191 and the instruction dictionary table 192 are for implementing an instruction dictionary table reference type compression instruction. When a series of instruction macros having a high appearance frequency first appears, the instruction macro is registered by an instruction dictionary registration instruction, and when the next occurrence occurs, a series of instruction macros is assigned to the instruction dictionary reference instruction by one instruction. I will replace it. The instruction dictionary table 192 holds a series of instruction macros, and the instruction dictionary index 191 has a function as an index for accessing the instruction dictionary table 192. The method of using this instruction dictionary table reference type compression instruction will be described later.

  The system memory 140 is a memory that stores an instruction to be executed, and data necessary for executing the instruction. A read or write access is requested from the processor core 110 to the system memory 140, but no request is actually generated as long as the instruction cache 120 or the data cache 130 is hit. The system memory 140 is an example of an instruction packet holding unit described in the claims.

  In this block configuration example, a program counter 111, an instruction cache 120, a next-implement fetch unit 150, a packet demultiplexer 160, a prefetch queue 170, and an instruction queue 180 belong to the instruction fetch stage (IF) 11 in FIG. The instruction register 112, the instruction dictionary index 191 and the instruction dictionary table 192 can also be considered as a part of the instruction fetch stage (IF) 11. Similarly, the instruction decoder belongs to the instruction decode stage (ID) 21. The register file 115 belongs to the register fetch stage (RF) 31. The execution unit 114 belongs to the execution stage (EX) 41. The data cache 130 and the system memory 140 belong to the memory access stage (MEM) 51.

[Instruction packet structure]
FIG. 3 is a diagram illustrating a structure example of the instruction packet 300 according to the first embodiment of this invention. The instruction packet 300 includes an instruction header 310 and an instruction payload 320. The instruction payload 320 is an area for storing one or more instruction cache lines. In this example, n 128-byte instruction cache lines are stored (n is an integer of 1 or more). The instruction header 310 is a header given to the instruction payload 320 and holds information regarding the instruction payload 320.

  FIG. 4 is a diagram showing a field configuration example of the instruction header 310 according to the first embodiment of the present invention. The first configuration example of the instruction header 310 includes fields of a branch prediction flag 311, an instruction prefetch timing 312, an instruction payload compression flag 313, an instruction payload length 314, and a prefetch setting 315. In this example, 32 bits are assumed as the instruction header 310, and the branch prediction flag 311 is assigned to the 0th bit from the LSB side, the instruction prefetch timing 312 is assigned to the 1st and 2nd bits, and the instruction payload compression flag 313 is assigned to the 3rd bit. Yes. Also, an instruction payload length 314 is assigned to the fourth to seventh bits, and a prefetch setting 315 is assigned to the eighth to eleventh bits, respectively. The remaining 20-bit unused area 316 of the 12th to 31st bits can be used for other purposes as will be described later.

  The branch prediction flag 311 is a field that indicates that a branch instruction exists in the instruction payload 320 and that there is a high possibility of branching in the instruction payload 320 or other than the next instruction payload as a branch destination. In other words, the branch prediction flag 311 indicates, for example, “1” when there is a high possibility that the next implicit fetch is executed as it is, and indicates “0” in other cases. The branch prediction flag 311 is an example of branch prediction information described in the claims.

  The instruction prefetch timing 312 is a field indicating the timing for executing the instruction prefetch. This instruction prefetch timing 312 will be described in the second embodiment. The instruction prefetch timing 312 is an example of prefetch timing information described in the claims.

  The instruction payload compression flag 313 is a field indicating whether or not the instruction payload 320 is subjected to lossless compression. Lossless compression is lossless compression that does not cause data loss, and compresses the entire bit string of the instruction payload 320. As the lossless compression method, Huffman code, arithmetic code, LZ code, and the like are widely known. When lossless compression is applied to the instruction payload 320, instruction decoding cannot be executed unless the instruction payload 320 is decompressed. Therefore, when the instruction payload compression flag 313 indicates “1”, the instruction decoding is performed after the decompression process is performed once. Even if lossless compression is performed on one instruction cache line, the amount of data fetched is not reduced, so there is no effect, and the coding efficiency cannot be increased unless the bit string is somewhat long. If a branch instruction is included, it is necessary to divide and separate the instruction packet for each basic block.

  The instruction payload length 314 is a field indicating the size of the instruction payload 320. For example, the size of the instruction payload 320 can be indicated with the number of instruction cache lines as a unit. In the above example, it is assumed that n 128-byte instruction cache lines are stored in the instruction payload 320. In this case, the value n is set to the instruction payload length 314.

  The prefetch setting 315 is a field for presetting an address to be prefetched. This prefetch setting 315 will be described in the fourth embodiment.

[Branch prediction flag]
FIG. 5 is a diagram illustrating a setting example of the branch prediction flag 311 used in the first embodiment of the present invention. In this example, it is assumed that the branch instruction $ 1 is included in the instruction payload of the instruction packet # 1, and the branch instructions are not included in the instruction packets # 2 and # 3. The branch destination of the branch instruction $ 1 is the instruction address in the instruction payload of the instruction packet # 3, and the branch probability is predicted to be high. Therefore, in this case, the branch prediction flag 311 in the instruction header of the instruction packet # 1 is set to “1”. On the other hand, since branch instructions are not included in the instruction packets # 2 and # 3, the branch prediction flag 311 in the instruction headers of the instruction packets # 2 and # 3 is set to “0”. As will be described later, this branch prediction flag 311 is assumed to be set statically at the time of compilation based on a profile or the like. Here, when viewed from the instruction packet # 1, the next line is included in the instruction packet # 2, and the branch destination line is included in the instruction packet # 3.

  The branch prediction flag 311 set in this manner is referred to at the time of instruction prefetching, and when it is set to “1”, prefetching of the next cache line is stopped. Thereby, it is possible to avoid an instruction prefetch that is expected to be wasted.

  On the other hand, if the case where the branch prediction flag 311 is set to “1” continues, instruction prefetch may not be performed and the instruction prefetch mechanism may not be effectively used. Therefore, it is considered that instructions between branch instructions are compressed by an instruction dictionary table reference type compression process so that cases where the branch prediction flag 311 is set to “1” do not continue. The instruction dictionary table reference compression process is separate from the lossless compression related to the instruction payload compression flag 313.

[Instruction dictionary table reference compression]
FIG. 6 is a diagram illustrating an application example of the instruction dictionary table reference compression used in the first embodiment of the present invention. In the uncompressed code on the left side of the figure, uncompressed instruction sequences 331 to 335 are arranged. Here, it is assumed that the instruction sequences 331, 332, and 335 are the same code. Similarly, it is assumed that the instruction sequences 333 and 334 are the same code.

  In the compressed code in the center of the figure, the instruction dictionary registration instruction% 1 is arranged immediately after the instruction string 331. As a result, the contents of the instruction string 331 are registered in the area% 1 (351) of the instruction dictionary table 192. Thereafter, when the instruction dictionary reference instruction% 1 (342) is executed, the area% 1 (351) of the instruction dictionary table 192 is referred to, and the content corresponding to the instruction string 332 is expanded and supplied to the instruction queue 180. .

  In the compressed code, the instruction dictionary registration instruction% 2 is arranged immediately after the instruction sequence 333. As a result, the contents of the instruction sequence 333 are registered in the area% 2 (352) of the instruction dictionary table 192. Thereafter, when the instruction dictionary reference instruction% 2 (344) is executed, the area% 2 (352) of the instruction dictionary table 192 is referred to, and the content corresponding to the instruction string 334 is expanded and supplied to the instruction queue 180. .

  When the instruction dictionary reference instruction% 1 (345) is further executed, the area% 1 (351) of the instruction dictionary table 192 is referred to, and the content corresponding to the instruction string 335 is expanded and supplied to the instruction queue 180. The

  In this way, by using the instruction dictionary table 192, instruction string compression processing is realized. Therefore, by using this, the setting of the branch prediction flag 311 can be changed as follows.

  FIG. 7 is a diagram illustrating a modification example of the branch prediction flag 311 by the instruction dictionary table reference compression according to the first embodiment of this invention. If the branch prediction flag 311 is set to “1” in the instruction packets # 1 and # 2 as shown on the left side of the figure, the instruction prefetch is not continuously performed. Therefore, an attempt is made to eliminate the fact that the branch prediction flag 311 is continuously set to “1” by performing instruction compression using the instruction dictionary table 192 described above.

  That is, as shown on the right side of the figure, the instruction between the branch instructions $ 1 and $ 2 is compressed using the instruction dictionary table 192, so that the branch instruction $ 2 included in the instruction packet # 2 is changed to the instruction packet. Move to # 1 '. As a result, the branch instruction $ 2 does not exist in the instruction packet # 2, so that the branch prediction flag 311 of the instruction packet # 2 ′ can be set to “0”.

  In general, an instruction dictionary table reference type compression instruction may require a larger number of cycles for decoding than a normal instruction. Therefore, if it is applied to all instructions, the processing performance may be deteriorated. is there. However, in the case where an instruction macro having a high appearance frequency exists, high compression efficiency is obtained and the effect is exhibited.

[Instruction packet generation processing]
FIG. 8 is a diagram illustrating a functional configuration example for generating an instruction packet according to the first embodiment of the present invention. This example includes a program holding unit 411, a branch profile holding unit 412, an instruction packet generation unit 420, a branch prediction flag setting unit 430, an instruction compression unit 440, and an instruction packet holding unit 413. It is suitable to generate the instruction packet at the time of compiling or linking. When dynamic linking is performed in a relocatable OS, it is possible even at the time of execution.

  The program holding unit 411 holds a program that is a target for generating an instruction packet. The branch profile holding unit 412 holds a branch profile of a branch instruction included in the program held in the program holding unit 411. This branch profile is obtained by analyzing or executing a program in advance. In the case of an unconditional branch instruction, it is often possible to determine whether or not to branch by analyzing a program. Even for a conditional branch instruction, the probability of statistical branching can be determined by executing a program.

  The instruction packet generation unit 420 generates an instruction payload 320 by dividing the program held in the program holding unit 411 by a fixed size, and generates an instruction packet 300 by attaching an instruction header 310 to each. As the size of the instruction payload 320, it can be assumed that n 128-byte instruction cache lines are stored as described above.

  The branch prediction flag setting unit 430 sets the branch prediction flag 311 in the instruction header 310 generated by the instruction packet generation unit 420. The branch prediction flag setting unit 430 refers to the branch profile held in the branch profile holding unit 412 to predict the branch destination of the branch instruction included in the instruction payload 320 and its branch probability, and the branch prediction flag 311. Set. If there is a branch instruction in the instruction payload 320 and there is a high possibility of branching in the instruction payload 320 or other than the next instruction payload as the branch destination, “1” is set in the branch prediction flag 311, In other cases, “0” is set. The branch prediction flag setting unit 430 is an example of a branch prediction information setting unit described in the claims.

  The instruction compression unit 440 compresses instructions included in the instruction payload 320. When instruction compression using the instruction dictionary table 192 is performed, an instruction macro having a high appearance frequency is detected, and when the instruction macro first appears, the instruction macro is registered by an instruction dictionary registration instruction. Then, when it appears next time, a series of instruction macros is replaced with one instruction for the instruction dictionary reference instruction. As a result, when the arrangement of the branch instruction is changed, the branch prediction flag 311 is set again. When lossless compression is performed on the entire instruction payload 320, the instruction payload compression flag 313 in the instruction header 310 is set to “1”.

  The instruction packet holding unit 413 holds the instruction packet 300 output from the instruction compression unit 440.

  FIG. 9 is a diagram illustrating an example of a processing procedure for generating an instruction packet according to the first embodiment of this invention.

  First, the instruction packet generator 420 generates the instruction payload 320 by dividing the program held in the program holder 411 into a fixed size, and the instruction packet 310 is generated by adding the instruction header 310 to each. (Step S911). Then, the branch prediction flag setting unit 430 determines whether or not there is a branch instruction in the instruction payload 320 and there is a high possibility of branching in the instruction payload 320 or other than the next instruction payload as the branch destination. (Step S912). As a result, when it is determined that such a branch is highly likely to occur, “1” is set to the branch prediction flag 311 (step S913), and “0” is set otherwise. .

  If “1” is set in the branch prediction flag 311 in the consecutive instruction packets 300 (step S914), the instruction compression unit 440 compresses the instructions in the instruction payload 320 using the instruction dictionary table 192. (Step S915). Note that it is possible to perform lossless compression on the entire instruction payload 320. In this case, the instruction payload compression flag 313 in the instruction header 310 is set to “1”.

[Instruction execution processing]
FIG. 10 is a diagram illustrating an example of a functional configuration for instruction execution in the first embodiment of the present invention. This example includes an instruction packet holding unit 413, an instruction packet separation unit 450, a branch prediction flag determination unit 460, an instruction prefetch unit 470, an instruction expansion unit 480, and an instruction execution unit 490.

  The instruction packet separation unit 450 separates the instruction packet 300 held in the instruction packet holding unit 413 into an instruction header 310 and an instruction payload 320.

  The branch prediction flag determination unit 460 refers to the branch prediction flag 311 of the instruction header 310 to determine whether or not to prefetch the next cache line for the instruction cache 120. When it is determined that prefetching should be performed, the branch prediction flag determination unit 460 requests the instruction prefetch unit 470 to perform instruction prefetch. The branch prediction flag determination unit 460 is an example of the branch prediction information determination unit described in the claims.

  The instruction prefetch unit 470 issues a next cache line request to the system memory 140 when an instruction prefetch is requested from the branch prediction flag determination unit 460. The prefetched instruction is held in the instruction cache 120 and is supplied to the instruction execution unit 490 if there is no change in the instruction flow.

  When the instruction payload compression flag 313 of the instruction header 310 is set to “1”, the instruction decompression unit 480 decompresses the instruction payload 320 that is losslessly compressed to obtain a decodable instruction sequence. is there. If the instruction payload compression flag 313 is not set to “1”, the instruction decompression unit 480 outputs the instruction in the instruction payload 320 as it is.

  The instruction execution unit 490 executes the instruction sequence output from the instruction expansion unit 480. For the instruction string subjected to the instruction dictionary table reference type compression, each instruction is expanded by executing the instruction dictionary registration instruction and the instruction dictionary reference instruction. On the other hand, the lossless compression cannot be decoded as it is, so that the instruction expansion unit 480 performs instruction expansion.

  FIG. 11 is a diagram illustrating an example of a processing procedure for instruction execution according to the first embodiment of this invention.

  First, the instruction packet 300 held in the instruction packet holding unit 413 is separated into the instruction header 310 and the instruction payload 320 by the instruction packet separation unit 450 (step S921). Then, the branch prediction flag 311 of the instruction header 310 is determined by the branch prediction flag determination unit 460 (step S922). If “1” is set in the branch prediction flag 311, instruction prefetch is suppressed (step S 923), and if “0” is set, instruction prefetch is executed by the instruction prefetch unit 470 (step S 924).

  If the instruction payload compression flag 313 of the instruction header 310 is set to “1” (step S925), the instruction decompression unit 480 decompresses the instruction payload 320 that has been losslessly compressed (step S926).

  Then, the obtained instruction is executed by the instruction execution unit 490 (step S927). At this time, for the instruction string subjected to the instruction dictionary table reference type compression, the instruction execution unit 490 executes the instruction dictionary registration instruction and the instruction dictionary reference instruction, whereby each instruction is expanded.

  Step S921 is an example of the instruction packet separation procedure described in the claims. Step S922 is an example of the branch prediction information determination procedure described in the claims. Steps S923 and S924 are an example of an instruction prefetch procedure described in the claims.

  Thus, according to the first embodiment of the present invention, it is possible to suppress useless instruction prefetching by setting the branch prediction flag 311 in advance.

[Modification]
FIG. 12 is a diagram illustrating a modification of the field configuration of the instruction header 310 according to the first embodiment of this invention. In the field configuration example of FIG. 4, 20 bits of the 12th to 31st bits are used as the unused area 316, but in this modification, the head instruction of the instruction payload is held in the 20-bit area 317. In the first embodiment, an instruction set of a 32-bit instruction is assumed. However, a 20-bit shortened instruction is created by devising an unused part of the instruction field and operands, and the area 317 Embedded. In this case, since the head instruction is embedded in the area 317, the size of the instruction payload 320 can be reduced by one instruction, that is, 32 bits.

  Although the head instruction is shortened to 20 bits here, the bit width of the shortened instruction is not limited to this, and can be determined as appropriate from the relationship with other fields.

<2. Second Embodiment>
In the above-described first embodiment, it is assumed that the program is managed by the instruction packet. However, in the second embodiment, such management is not necessarily required. Therefore, instruction prefetch control not using an instruction packet will be described first, and then instruction prefetch control using the instruction packet will be described. In the second embodiment, the pipeline configuration and the block configuration are the same as those in the first embodiment described above, and a description thereof will be omitted.

[Branch instruction placement and instruction prefetch start position]
FIG. 13 is a diagram illustrating an example of the relationship between the arrangement of branch instructions and the instruction prefetch start position in the second embodiment of the present invention. The branch destination of the branch instruction $ 1 existing in the cache line # 1 is included in the cache line # 3. Therefore, if the branch instruction $ 1 is executed as a result of branching, even if the cache line # 2 is prefetched as the next line following the cache line # 1, it is useless.

  At this time, if the prefetch of the cache line # 2 is started from the prefetch start position A, the execution result of the branch instruction $ 1 is unknown at that time, and the prefetch of the cache line # 2 may be wasted. On the other hand, if the prefetch of the cache line # 2 is started from the prefetch start position B, the execution result of the branch instruction $ 1 is known at that time, and it is possible to suppress the useless prefetch of the cache line # 2. It is.

  Thus, the prefetch start position affects whether or not next-implicit fetching can be suppressed. From the above example, the later the prefetch start position is, the more the execution result of the branch instruction can be known, which is advantageous for prefetch suppression. On the other hand, if the prefetch start position is too late, prefetching may not be in time, and there is a possibility that an instruction wait may occur in the instruction pipeline. Therefore, in the second embodiment of the present invention, a mechanism for performing instruction prefetching at an arbitrary preset timing is provided.

[When setting the timing in the prefetch start address setting register]
FIG. 14 is a diagram illustrating a configuration example using a prefetch start address setting register according to the second embodiment of the present invention. As shown in FIG. 14A, this configuration example includes a prefetch start address setting register 153 and an address comparison unit 154 as a configuration in the next implementation fetch unit 150.

  The prefetch start address setting register 153 is a register for setting an address at which next implicit fetch is started in each cache line. A relative address in the cache line is sufficient for the address set in the prefetch start address setting register 153. This address setting is assumed to be determined at the time of compilation based on the frequency of branch instructions in the program. The prefetch start address setting register 153 is an example of an address setting register described in the claims.

  The address comparison unit 154 compares the address set in the prefetch start address setting register 153 with the contents of the program counter 111. When a match is detected for the relative address in the cache line, the address comparison unit 154 issues a next implement fetch request.

  According to this configuration example, the prefetch start address is set in the prefetch start address setting register 153 at an arbitrary position in the cache line, and the address comparison unit 154 can detect a match.

  FIG. 14B shows an example of a specific set address. Assume that about four prefetch start positions are provided in the cache line. Assuming that the cache line is 128 bytes, it is possible to set the positions of the top (0 byte), 32 bytes, 64 bytes (center), and 96 bytes by dividing into 32 bytes. Assuming a 4-byte (32-bit) long instruction set, the lower 2 bits representing the instruction address in binary can be ignored. Therefore, in this case, it is understood that 5 bits from the lower 3 bits to the lower 7 bits may be compared by the address comparison unit 154.

[Use of instruction header]
FIG. 15 is a diagram illustrating a configuration example using the instruction prefetch timing field 312 of the instruction header 310 according to the second embodiment of the present invention. In this configuration example, the field of the instruction prefetch timing 312 of the instruction header 310 is used on the premise of the instruction packet described in the first embodiment. The next-implement fetch unit 150 includes a setting step address register 151 and a multiplication unit 152 in addition to the prefetch start address setting register 153 and the address comparison unit 154 shown in FIG.

  The setting step address register 151 is a register that holds the granularity when setting the prefetch start address as a step value. For example, when 32 bytes are set as the step value and the position of the top (0 byte), 32 bytes, 64 bytes, or 96 bytes of the cache line is set as the prefetch start as in the above example, “32” is set. Is held in the setting step address register 151.

  The multiplier 152 multiplies the field value of the instruction prefetch timing 312 by the step value held in the set step address register 151. As described above, since the field of the instruction prefetch timing 312 is 2 bits wide, in order to compensate for this, the instruction prefetch timing 312 is configured to hold the step number and multiply by the step value indicated in the set step address register 151. is doing. Therefore, the instruction prefetch timing 312 of the instruction header 310 may be “00” if it is the beginning (0 byte) of the cache line, “01” if it is 32 bytes, “10” if it is 64 bytes, or 96 bytes. In this case, “11” is set. The multiplication result by the multiplication unit 152 is held in the prefetch start address setting register 153.

  The rest of the configuration is the same as in FIG. 14A, and the address held in the prefetch start address setting register 153 and the contents of the program counter 111 are compared by the address comparison unit 154. When a match is detected for the relative address in the cache line, the address comparison unit 154 issues a next implement fetch request.

  Note that the step value is preferably a power of 2 in order to facilitate multiplication in the multiplication unit 152 or address comparison in the address comparison unit 154.

  According to this configuration example, the prefetch start address can be set in the prefetch start address setting register 153 using the field of the instruction prefetch timing 312 of the instruction header 310.

[When a predetermined number of instruction executions are used for prefetch timing]
FIG. 16 is a diagram illustrating a configuration example in which execution of a predetermined number of instructions is used for prefetch timing in the second embodiment of the present invention. In the configuration examples of FIGS. 14 and 15, the fixed position in the cache line is set as the prefetch timing. However, in this configuration example, the time when an instruction of a specific instruction type is executed a predetermined number of times is set as the prefetch timing. This configuration example includes an instruction type setting register 155, an execution count setting register 156, an instruction type comparison section 157, an execution count counter 158, and an execution count comparison section 159 as a configuration in the next implement fetch section 150.

  The instruction type setting register 155 is a register that sets an instruction type of an instruction to be counted. As an instruction type in this case, for example, an instruction with a relatively long latency such as a division instruction or a load instruction, a branch instruction, or the like can be assumed. This is because an instruction with a long latency has no effect on the overall execution even if the subsequent instruction is delayed a little. As for the branch instruction, as described with reference to FIG. 13, it may be better to wait for the execution of the branch instruction in order to determine the subsequent instruction.

  The execution count setting register 156 is a register that sets the number of times the instruction corresponding to the instruction type set in the instruction type setting register 155 is executed. When the execution of the number of times set in the execution count setting register 156 is performed, a next implement fetch request is issued.

  The setting of the instruction type and the number of executions can be determined statically at the time of compilation or dynamically at the time of execution based on the appearance frequency included in the profile data.

  The instruction type comparison unit 157 compares the instruction type of the instruction held in the instruction register 112 with the instruction type set in the instruction type setting register 155 to detect a match. Each time a match is detected by the instruction type comparison unit 157, a count trigger is output to the execution number counter 158.

  The execution number counter 158 is a counter that counts the number of executions of an instruction corresponding to the instruction type set in the instruction type setting register 155. The execution number counter 158 includes an adder 1581 and a count value register 1582. The adding unit 1581 adds “1” to the value of the count value register 1582. The count value register 1582 is a register that holds a count value as the execution number counter 158. The count value register 1582 holds the output of the adder 1581 each time a count trigger is output from the instruction type comparator 157. Thereby, the number of executions is counted.

  The execution number comparison unit 159 compares the value of the count value register 1582 and the value of the execution number setting register 156 to detect a match. When the execution number comparing unit 159 detects a match, a next implement fetch request is issued.

  A plurality of sets of the instruction type setting register 155 and the execution count setting register 156 can be provided. In this case, it is necessary to provide the execution counter 158 separately. As a result, when a match is detected for any pair, a next implement fetch request is issued.

[Use of instruction header]
FIG. 17 is a diagram illustrating an example in which the instruction type and the execution count are set in the instruction header 310 according to the second embodiment of this invention. In the configuration example of FIG. 16, the instruction type and the execution count are set in the instruction type setting register 155 and the execution count setting register 156, respectively, but these values can be set in the instruction header 310.

  In this example, the instruction type is set in the 14-bit area 318 from the 12th bit to the 25th bit of the instruction header 310, and the execution count is set in the 6-bit area 319 from the 26th bit to the 31st bit. is doing. Therefore, by using the value of the area 318 as one input of the instruction type comparison unit 157 and the value of the area 319 as one input of the execution frequency comparison unit 159, a predetermined number of instructions can be obtained without providing a special setting register. Execution can be used for prefetch timing.

[Instruction execution processing]
FIG. 18 is a diagram illustrating an example of a functional configuration for instruction execution in the second embodiment of the present invention. This example includes a program execution state generation unit 510, a detection state setting unit 520, an instruction prefetch timing detection unit 530, an instruction prefetch unit 570, and an instruction execution unit 590.

  The program execution state generation unit 510 generates an execution state of the current program. The program execution state generation unit 510 can generate, for example, the value of the program counter 111 that holds the instruction address currently being executed as the execution state of the current program. For example, the current number of executions of a predetermined instruction type held in the execution number counter 158 can be generated.

  The detection state setting unit 520 sets the execution state of a program whose instruction prefetch timing should be detected. In the detection state setting unit 520, for example, at least a part of an instruction address whose instruction prefetch timing should be detected can be set in the prefetch start address setting register 153 as a program execution state. Further, for example, the execution count of a predetermined instruction type can be set in the execution count setting register 156.

  The instruction prefetch timing detection unit 530 compares the execution state of the current program with the execution state of the program set in the detection state setting unit 520, and detects the instruction prefetch timing when they match. As the instruction prefetch timing detection unit 530, the address comparison unit 154 or the execution frequency comparison unit 159 can be used.

  The instruction prefetch unit 570 executes next line instruction prefetch when the instruction prefetch timing detection unit 530 detects the instruction prefetch timing.

  The instruction execution unit 590 executes the instruction acquired by the instruction prefetch unit 570. As a result of execution by the instruction execution unit 590, the execution state of the current program generated by the program execution state generation unit 510 is affected. That is, the value of the program counter 111 and the value of the execution counter 158 can be updated.

  FIG. 19 is a diagram illustrating an example of a processing procedure for executing instructions in the second embodiment of the present invention.

  First, an execution state of a program whose instruction prefetch timing is to be detected is set in the detection state setting unit 520 (step S931). For example, the instruction address at which the instruction prefetch timing should be detected and the number of executions of a predetermined instruction type are set.

  Then, the instruction execution unit 590 executes the instruction (step S932), and the instruction prefetch timing detection unit 530 detects the instruction prefetch timing (step S933). For example, the instruction prefetch timing is detected when the set instruction address matches the program counter 111 or when the set number of executions of the predetermined instruction type matches the value of the execution counter 158. When the instruction prefetch timing is detected by the instruction prefetch timing detection unit 530, the instruction prefetch unit 570 performs instruction prefetch (step S934).

  As described above, according to the second embodiment of the present invention, it is possible to control the instruction prefetch timing by setting the timing for performing the instruction prefetch in advance.

<3. Third Embodiment>
The first and second embodiments described above relate to the suppression control of the next implementation fetch. However, in the following third and fourth embodiments, both the next line and the branch destination line are prefetched. Suppose. Note that in the third embodiment of the present invention, the pipeline configuration and the block configuration are the same as those in the first embodiment described above, and a description thereof will be omitted.

[Program counter addition control processing]
FIG. 20 is a diagram illustrating a functional configuration example of the addition control process of the program counter according to the third embodiment of the present invention. This configuration example includes an instruction fetch unit 610, an instruction decode unit 620, an instruction execution unit 630, an addition control register 640, an addition control unit 650, and a program counter 660.

  The instruction fetch unit 610 fetches an instruction to be executed according to the value of the program counter 660 and corresponds to the instruction fetch stage 11. The instruction fetched by the instruction fetch unit 610 is supplied to the instruction decode unit 620.

  The instruction decode unit 620 decodes the instruction fetched by the instruction fetch unit 610 and corresponds to the instruction decode stage 21.

  The instruction execution unit 630 executes the instruction decoded by the instruction decoding unit 620 and corresponds to the instruction execution stage 41. Note that operand access is omitted here.

  The addition control register 640 holds data for performing addition control of the program counter 660. A configuration example of the addition control register 640 will be described later.

  The addition control unit 650 performs addition control of the program counter 660 based on the data held in the addition control register 640.

  The program counter 660 counts the address of the instruction to be executed, and corresponds to the program counter (PC) 18. The program counter 660 includes a program counter value holding unit 661 and an adding unit 662. The program counter value holding unit 661 is a register that holds the value of the program counter. The adding unit 662 performs processing for adding the values of the program counter value holding unit 661.

  FIG. 21 is a diagram illustrating a configuration example of the addition control register 640 according to the third embodiment of the present invention. The addition control register 640 holds an increment word count (incr) 641 and an increment count (conti) 642.

  The increment word number 641 holds the increment word number when the value of the program counter value holding unit 661 is added by the adder 662. In the fourth embodiment, an instruction set of a 32-bit (4 byte) length instruction is assumed, so one word is 4 bytes. If the program counter 660 omits the lower 2 bits of the address and holds the address in units of words, an increment value “1” is added each time in the conventional method. On the other hand, in the fourth embodiment, the value of the increment word number 641 is added as the increment value. When “1” is set in the increment word number 641, the conventional operation is performed. However, when an integer value of “2” or more is set, the instruction can be executed while being thinned. Specific examples will be described later. The increment word number 641 is an example of an increment value register described in the claims.

  The number of increments 642 holds the number of times the addition unit 662 performs addition according to the number of incremented words 641. Normally, the increment value “1” is added in the same manner as in the conventional method, but when an integer value equal to or greater than “1” is set in the increment count 642, the increment according to the increment word number 641 is performed. The increment count 642 may be configured such that “1” is subtracted until it becomes “0” each time an instruction is executed by a subtracting unit (not shown). “1” may be subtracted until becomes “0”. In any case, after the number of times specified in the increment number 642 is added according to the increment word number 641, the process returns to the increment value “1” as usual. The increment count 642 is an example of a change instruction register described in the claims.

[Instruction execution mode]
FIG. 22 is a diagram illustrating an example of a processing mode of an instruction by a two-way branch according to the third embodiment of this invention. If the address of a branch instruction that performs a two-way branch is “A”, the instruction sequence when no branch occurs is “A + 4”, “A + 12”, “A + 20”, “A + 28”, “A + 36”, “A + 44”. , “A + 52”, “A + 60”... On the other hand, the instruction sequences when a branch occurs are arranged in “A + 8”, “A + 16”, “A + 24”, “A + 32”, “A + 40”, “A + 48”, “A + 56”, “A + 64”,. . That is, the instruction sequence when the branch does not occur and the instruction sequence when the branch occurs are alternately arranged.

  In the case of this two-way branch, when the first instruction of each instruction sequence is executed, “2” is set to the increment word number 641 and the instruction count of each instruction sequence is set to the increment count 642. Thereby, only one of the instruction sequences arranged alternately can be executed.

  FIG. 23 is a diagram illustrating an example of a processing mode of an instruction by multidirectional branching according to the third embodiment of this invention. Here, an example of a three-way branch will be described, but the same technique can be applied when branching in four or more directions. If the address of a branch instruction that performs a three-way branch is “A”, the first instruction sequence is “A + 4”, “A + 16”, “A + 28”, “A + 40”, “A + 52”, “A + 64”, “A + 76”. ... is arranged. The second instruction sequence is arranged in “A + 8”, “A + 20”, “A + 32”, “A + 44”, “A + 56”, “A + 68”, “A + 80”. Also, the third instruction sequence is arranged in “A + 12”, “A + 24”, “A + 36”, “A + 48”, “A + 60”, “A + 72”, “A + 84”. That is, the first to third instruction sequences are arranged one by one in order.

  In the case of this three-way branch, when the first instruction of each instruction sequence is executed, “3” is set to the increment word number 641 and the instruction count of each instruction sequence is set to the increment number 642. Thereby, it is possible to execute only one of the instruction sequences arranged one by one in order.

[Setting to addition control register]
FIG. 24 is a diagram illustrating an example of an instruction set for setting a value in the addition control register 640 according to the third embodiment of the present invention. FIG. 24A shows an example of an instruction format in the third embodiment of the present invention. This instruction format includes a 6-bit opcode (OPCODE), a 5-bit first source operand (rs), a 5-bit second source operand (rt), a 5-bit destination operand (rd), and an 11-bit immediate field. (Imm).

  FIG. 24B shows an example of an operation code list in the third embodiment of the present invention. The upper 3 bits of the operation code are arranged in the vertical direction, and the lower 3 bits of the operation code are arranged in the horizontal direction. The following description focuses on the conditional branch instruction at the lower right of the operation code list and the control register change instruction of the operation code “100111”.

  FIG. 24C shows an example of the instruction format of the conditional branch instruction. As this conditional branch instruction, BEQfp, BNEfp, BLEfp, BGTfp, BLTZfp, BGEZfp, BLTZALfp, BGEZALfp are listed here. “EQ” following “B” representing a branch (Branch) indicates that the value of both source operands is equal (EQual) (rs = rt) as a branch condition. “NE” represents that the branch condition is that the values of both source operands are not equal (Not Equal) (rs ≠ rt). “LE” indicates that the branch condition is that the first source operand is less than or equal to the second source operand (less than or equal) (rs ≦ rt). “GTZ” indicates that the branch condition is that the first source operand is greater than zero (rs> 0). “LTZ” represents that the first source operand is less than zero (Less Than Zero) (rs <0) as a branch condition. “GEZ” represents that the branch condition is that the first source operand is greater than or equal to zero (rs ≧ 0). Further, “AL” following them means that the return address is stored at the time of branching (branch and link). Further, “fp” following them means that the values of both source operands represent floating point numbers. The increment word number incr shown as the destination operand is the increment word number when the value of the program counter 660 is added. The increment count conti shown as an immediate field is the number of times the program counter 660 performs addition according to the increment word count incr. When these conditional branch instructions are executed, the increment word number incr is set in the increment word number 641 of the addition control register 640, and the increment number conti is set in the increment number 642.

  FIG. 24D shows an example of the instruction format of the control register change instruction PCINCMODE. This control register change instruction PCINCMODE is an instruction for setting the increment mode of the program counter 660 in the addition control register 640. When this control register change instruction PCINCMODE is executed, the increment word number incr of the increment control register 640 is set to the increment word count incr, and the increment count 642 is set to the increment count conti. This control register change instruction PCINCMODE is an instruction separate from the conditional branch instruction, and is actually used together with the conditional branch instruction.

  FIG. 25 is a diagram illustrating an example when a value is set in the addition control register 640 by a conditional branch instruction in the third embodiment of the present invention. In this example, the branch condition “rs = rt”, the increment word number “2”, and the increment count “L / 2” are specified in the conditional branch instruction BEQfp. Let m be the instruction word address of this conditional branch instruction BEQfp. At this time, if the branch condition “rs = rt” is satisfied, the instruction m + 2, the instruction m + 4, and the instruction m + 6 are executed in the order of the instruction m + L up to the instruction m + L with the incremented word number “2”. On the other hand, if the branch condition “rs = rt” is not satisfied, the instruction m + 1, the instruction m + 3, and the instruction m + 5 are executed in the order of the instruction m + (L−1) with the increment word number “2”.

  FIG. 26 is a diagram illustrating an example when a value is set in the addition control register 640 by the control register change instruction PCINCMODE in the third embodiment of the present invention. In this example, a control register change instruction PCINCMODE is arranged next to a normal conditional branch instruction that does not set the addition control register 640. In the control register change instruction PCINCMODE, the number of increment words “2” and the increment count “L / 2” are designated. Let m be the instruction word address of the control register change instruction PCINCMODE. At this time, if the branch condition is satisfied in the conditional branch instruction, the instruction m + 2, the instruction m + 4, and the instruction m + 6 are executed in the order of the instruction m + L up to the instruction m + L with the increment word number “2”. On the other hand, if the branch condition is not satisfied in the conditional branch instruction, the instruction m + 1, the instruction m + 3, and the instruction m + 5 are executed in the order of the instruction m + (L−1) and the incremented word number “2”.

[Instruction execution processing]
FIG. 27 is a diagram illustrating an example of a processing procedure for instruction execution according to the third embodiment of the present invention. Here, it is assumed that the setting of the number of increment words and the increment count in the addition control register 640 has been completed in advance by the above-described conditional branch instruction, control register change instruction, and the like.

  If the increment count 642 of the addition control register 640 is greater than zero (step S941), a value obtained by multiplying the increment word number 641 by “4” in the program counter 660 is added to the program counter value holding unit 661 by the adder 662 (step S941). S942). In this case, “1” is subtracted from the increment number 642 of the addition control register 640 (step S943). On the other hand, when the increment count 642 of the addition control register 640 is not greater than zero (step S941), the value “4” is added to the program counter value holding unit 661 by the adding unit 662 in the program counter 660 as usual (step S941). Step S944). These processes are repeated. Note that step S942 is an example of a change increment addition procedure described in the claims. Step S944 is an example of a normal incremental addition procedure described in the claims.

  As described above, according to the third embodiment of the present invention, a plurality of instruction sequences after branching are arranged in order and mixed in order, and the addition of the program counter is controlled in accordance with the branching condition. By doing so, an instruction of an appropriate instruction sequence can be executed. As a result, the next line and the branch destination line can be mixedly arranged, and the instruction prefetch penalty can be averaged.

<4. Fourth Embodiment>
[Processor configuration]
FIG. 28 is a diagram illustrating a pipeline configuration example of a processor according to the fourth embodiment of the present invention. The basic pipeline configuration assumes a five-stage pipeline similar to that described in the first embodiment.

  In the first embodiment, the next line prefetch unit 13 performs the next line prefetch. However, in the fourth embodiment, the next line branch destination line prefetch unit 14 prefetches the next line and the branch destination line. I do. In other words, not only the next line that is the next cache line after the cache line that includes the instruction that is currently being executed, but also the branch destination line that is the cache line that includes the branch destination instruction is prefetched. The branch destination line prefetched by the next line branch destination line prefetch unit 14 is held in the prefetch queue 17. The branch destination line held in the prefetch queue 17 is used when supplied to the next instruction decode stage (ID) 21. Since the next line is directly supplied from the instruction cache, it is not necessary to go through the prefetch queue 17.

  FIG. 29 is a diagram illustrating a block configuration example of a processor according to the fourth embodiment of the present invention. The basic block configuration is the same as that described in the first embodiment.

  In the first embodiment described above, the next line prefetch unit 150 performs the next line prefetch. In the fourth embodiment, the next line branch destination line prefetch unit 250 performs the next line and branch destination line prefetch. I do. Further, the prefetch queue 171 is arranged in parallel with the instruction cache 120 so that the branch destination line can be directly supplied from the prefetch queue 171 to the instruction register 112. That is, when a branch occurs, an instruction from the prefetch queue 171 is bypassed and supplied instead of the instruction supplied from the instruction cache 120. Thereby, it is possible to continue issuing instructions without stalling the pipeline. The next line branch destination line prefetch unit 250 is an example of a prefetch unit described in the claims. The prefetch queue 171 is an example of a prefetch queue described in the claims.

  In the fourth embodiment, since it is not essential to divide into instruction packets, it is excluded from this block configuration. Also, compression by the instruction dictionary table is not essential in the fourth embodiment, and is excluded from the block configuration. These can be implemented in combination as appropriate.

[Relationship between branch instruction and cache line]
FIG. 30 is a diagram showing a relationship between a branch instruction and a cache line in the fourth embodiment of the present invention.

  A cache line including an instruction that is currently being executed is referred to as a current line, and a subsequent cache line is referred to as a next line. A cache line including a branch destination instruction of a branch instruction included in the current line is referred to as a branch destination line. In this example, a branch instruction is arranged at the end of the current line. This is because by starting the prefetch of the next line and the branch destination line from the timing when the first instruction of the current line is executed, there is a margin until the prefetch of both lines is completed before the branch instruction is executed. . Therefore, it is not always necessary that the branch instruction is arranged at the end of the current line, and if it is arranged at least in the latter half of the current line, it may be possible to meet the prefetch completion in some cases.

  If a branch instruction is placed at the end of the current line, the next line is necessary if the branch condition in the branch instruction is not satisfied and a branch does not occur, and a branch occurs if the branch condition is satisfied and a branch occurs. A destination line is required. Therefore, it is desirable to prefetch both the next line and the branch destination line in order to succeed in prefetching regardless of whether or not the branch condition is satisfied. In the fourth embodiment of the present invention, by prefetching both lines by the next line branch destination line prefetch unit 250, instruction execution can be continued regardless of whether or not the branch condition is satisfied. In this case, in order to prefetch both lines, it is desirable that the throughput is twice the normal, but this is not necessarily an essential requirement.

  Considering the collision of each cache line on the instruction cache 120, it is desirable to provide a restriction on the arrangement of branch destination lines. For example, when the instruction cache 120 uses the direct mapping method, cache lines having the same line address cannot be stored at the same time, causing a collision. In this case, if a branch destination line having the same line address is prefetched immediately after the next line is prefetched, the next line is evicted from the instruction cache 120. In the case of the 2-way set associative method, the possibility of a collision is reduced, but depending on the storage state, it may occur when other cache lines are affected. Therefore, in the fourth embodiment, the direct mapping type instruction cache is assumed as the strictest condition, and the arrangement of the branch destination line is made by the compiler or the linker so that the next line and the branch destination line do not have the same line address. Adjust.

In order to change the instruction address arrangement in the compiler or linker, for example, the following technique can be used. First, the following instruction sequence is assumed. The number following “0x” represents a hexadecimal number.
0x0000: Instruction A
0x0004: Instruction B
0x0008: Instruction C
At this time, when it is desired to shift the instruction arrangement backward by 4 bytes as a whole, a method of inserting a NOP (No-OPeration) instruction as follows can be considered.
0x0000: NOP instruction 0x0004: Instruction A
0x0008: Instruction B
0x000C: Instruction C

Further, when the instruction A is an instruction for performing a plurality of operations, if the instruction A can be divided into two instructions, the instruction AA and the instruction AB as follows, the instruction arrangement is similarly shifted backward by 4 bytes. be able to.
0x0000: Instruction AA
0x0004: Instruction AB
0x0008: Instruction B
0x000C: Instruction C

  FIG. 31 is a diagram illustrating an aspect of changing the instruction arrangement according to the fourth embodiment of the present invention. Here, as shown in FIG. 31A, there is a branch instruction C behind the instruction sequence A and the instruction sequence B, and either the instruction sequence D or the instruction sequence E is processed, and then the instruction sequence F is processed. Assuming a program called At this time, if the result of the instruction sequence B does not affect the branch condition of the branch instruction C, the branch instruction C is moved immediately after the instruction sequence A as shown in FIG. By placing the instruction at the branch destination, the instruction arrangement can be changed without affecting the execution result.

[Instruction placement processing]
FIG. 32 is a diagram illustrating an example of a functional configuration for instruction arrangement according to the fourth embodiment of the present invention. In this configuration example, it is assumed that an object code is generated from a program held in the program holding unit 701 and held in the object code holding unit 702. This configuration example includes a branch instruction extraction unit 710, a branch instruction arrangement unit 720, a branch destination instruction arrangement unit 730, and an object code generation unit 740.

  The branch instruction extraction unit 710 extracts a branch instruction from the programs held in the program holding unit 701. The branch instruction extraction unit 710 grasps the address of the extracted branch instruction in the program and supplies it to the branch instruction arrangement unit 720. Further, the branch instruction extraction unit 710 grasps the branch destination address of the extracted branch instruction and supplies it to the branch destination instruction placement unit 730.

  The branch instruction placement unit 720 places the branch instruction extracted by the branch instruction extraction unit 710 in the latter half of the cache line (current line). The reason why it is arranged in the latter half part of the cache line is to provide a margin until the prefetch is completed as described above. Therefore, from this point of view, it is most desirable to place a branch instruction at the end of the cache line.

  The branch destination instruction placement unit 730 transfers the branch destination instruction of the branch instruction extracted by the branch instruction extraction unit 710 to another cache line (branch destination line) having a line address different from the next cache line (next line). Is to be placed. The reason why the next line and the branch destination line are arranged in cache lines having different line addresses is to avoid a collision in the instruction cache 120 as described above.

  The object code generation unit 740 generates an object code for an instruction sequence including a branch instruction and a branch destination instruction arranged by the branch instruction arrangement unit 720 and the branch destination instruction arrangement unit 730. The object code generated by the object code generation unit 740 is held in the object code holding unit 702. The object code generation unit 740 is an example of an instruction sequence output unit described in the claims.

  FIG. 33 is a diagram illustrating an example of a processing procedure for instruction arrangement according to the fourth embodiment of the present invention.

  First, the branch instruction extraction unit 710 extracts a branch instruction from the program held in the program holding unit 701 (step S951). Then, the branch instruction extracted by the branch instruction extraction unit 710 is arranged in the latter half portion of the cache line (current line) by the branch instruction arrangement unit 720 (step S952). Further, the branch destination instruction of the branch instruction extracted by the branch instruction extraction unit 710 is another cache line (branch destination line) having a line address different from that of the next cache line (next line) by the branch destination instruction placement unit 730. (Step S953). Then, the object code generation unit 740 generates an object code for the instruction sequence including the branch instruction and the branch destination instruction arranged by the branch instruction arrangement unit 720 and the branch destination instruction arrangement unit 730 (step S954).

  Note that step S951 is an example of a branch instruction extraction procedure described in the claims. Step S952 is an example of a branch instruction arrangement procedure described in the claims. Step S953 is an example of a branch destination instruction arrangement procedure described in the claims. Step S954 is an example of an instruction sequence output procedure described in the claims.

[Prefetch address setting]
FIG. 34 is a diagram showing a setting example of the prefetch address register in the fourth embodiment of the present invention. As described above, the branch destination line is arranged at a line address different from that of the next line. When prefetching a branch destination line, the prefetch may be always fixed according to the relative position from the current line. However, the branch destination address to be automatically prefetched is arbitrarily set as follows. You may do it.

  FIG. 34A is a diagram illustrating a configuration example of a prefetch address register (PRADDR: PRefetch ADDress Register) 790. The prefetch address register 790 is a register that sets a prefetch address to be prefetched to the instruction cache 120 as a branch destination line. This prefetch address is held in the lower 12 bits of the prefetch address register 790.

  FIG. 34B is a diagram showing an instruction format of an MTSI_PRADDR (Move To Special register Immediate-PRADDR) instruction for setting a value for the prefetch address register 790. This MTSI_PRADDR instruction is one of special (SPECIAL) instructions, and is an instruction for setting an immediate value in a specific register (here, prefetch address register 790). The 17th to 21st bits of this instruction represent the prefetch address register PRADDR. The 11th to 8th bits of this instruction are set to the 11th to 8th bits of the prefetch address register 790. Thereby, the address of the branch destination line to be prefetched is set. In this case, the specification of the instruction cache 120 is assumed to be a 4-Kbyte 2-way set associative method, a total of 16 lines of 8 lines per way, and an entry size of 256 bytes.

  As another example, it can be considered that the prefetch setting field 315 of the instruction header 310 is used by dividing the instruction packet 300 described in the first embodiment. In this case, the 11th to 8th bits of the prefetch setting field 315 of the instruction header 310 of FIG. 4 are set to the 11th to 8th bits of the prefetch address register. Thereby, the address of the branch destination line to be prefetched can be set without using a special instruction.

[Instruction execution processing]
FIG. 35 is a diagram illustrating a functional configuration example for instruction execution according to the fourth embodiment of the present invention. In this configuration example, it is assumed that the state of the program counter 111 is detected and prefetching is performed to the instruction cache 120 and the prefetch queue 171. This configuration example includes a prefetch timing detection unit 750, a next-implement fetch unit 760, and a branch destination line prefetch unit 770. These configurations correspond to the next-line branch destination line prefetch unit 250 having a block configuration.

  The prefetch timing detector 750 refers to the state of the program counter 111 and detects the instruction prefetch timing. In the fourth embodiment, since both the next line and the branch destination line are prefetched, it is desirable to start prefetching early. Therefore, for example, it is conceivable to detect the instruction prefetch timing at the start of execution of the instruction at the head of the cache line.

  The next implement fetch unit 760 prefetches the next line. The next line prefetched from the system memory 140 is stored in the instruction cache 120.

  The branch destination line prefetch unit 770 prefetches the branch destination line. As the branch destination line, the cache line relative to the current line may be used in a fixed manner, or the address set in the prefetch address register 790 may be used. The branch destination line prefetched from the system memory 140 is stored in the instruction cache 120 and the prefetch queue 171.

  FIG. 36 is a diagram illustrating an example of a processing procedure for instruction execution according to the fourth embodiment of the present invention.

  First, when it is detected by the prefetch timing detection unit 750 that the instruction at the head of the cache line has been started (step S961), the next line is prefetched by the next implementation fetch unit 760 (step S962). The branch destination line prefetch unit 770 prefetches the branch destination line (step S963). Thereafter, these processes are repeated. As a result, instruction sequences in both directions of the next line and the branch destination line are prefetched.

  As described above, according to the fourth embodiment of the present invention, the branch destination line is arranged to have a line address different from that of the next line, and instruction sequences in both directions of the next line and the branch destination line are prefetched. As a result, throughput can be improved.

<5. Combination of embodiments>
Up to this point, the first to fourth embodiments of the present invention have been described separately, but these embodiments can be implemented in appropriate combination.

[Combination of the first embodiment and the second embodiment]
In the first embodiment of the present invention, the presence / absence of prefetching is determined according to the branch prediction flag 311 of the instruction header 310, but in order to avoid the prediction being lost, the second embodiment of the present invention is used. It is effective to combine them. That is, by delaying the prefetch determination according to the second embodiment, the presence or absence of a branch can be determined first, and a correct cache line can be prefetched.

[Combination of the first or second embodiment and the third embodiment]
Since the third embodiment of the present invention performs prefetching in both directions, it may be difficult to apply in the case of a branch instruction to a branch destination with a remote address or an if statement without an else clause. For example, when all cases of multi-directional branch are not the same number of instructions, it is necessary to insert NOP instructions until the number of instructions becomes the same number. In addition, if an instruction example is long to some extent, instruction execution throughput and cache utilization efficiency are reduced. On the other hand, by using the branch prediction flag 311 of the first embodiment, the prefetching in both directions is not performed when there is a high possibility of branching to a distant address. The disadvantages of this form can be avoided. Further, as in the second embodiment, by delaying the instruction prefetch timing, the presence / absence of a branch is determined first, and unnecessary prefetch is not performed, thereby avoiding the disadvantages of the third embodiment. be able to.

[Combination of the first or second embodiment and the fourth embodiment]
In the fourth embodiment of the present invention, the next line and the branch destination line are always prefetched. However, if the current line does not include a branch instruction, the prefetch of the branch destination line is wasted. There is. Therefore, when the branch prediction flag 311 of the first embodiment is used and it is determined that there is a high possibility of executing the next line, only the next line is prefetched, thereby demerit of the fourth embodiment. Can be avoided. Further, as in the second embodiment, by delaying the instruction prefetch timing, the presence / absence of a branch is determined first, so that the unnecessary prefetch is not performed, thereby avoiding the disadvantages of the fourth embodiment. be able to.

[Combination of the third embodiment and the fourth embodiment]
In the fourth embodiment of the present invention, the prefetch in the two directions of the next line and the branch destination line is targeted. However, by applying the third embodiment, the present invention can also be applied to a multidirectional branch of three or more directions. Is possible. That is, it is possible to apply to a multi-directional branch by bi-directional prefetching a cache line in which a plurality of instruction sequences are mixed.

  At this time, the third embodiment is applied to small branches within the range of the line size, and the fourth embodiment is applied to branching to a wider range. Can be avoided. That is, the fourth embodiment has a demerit that the use efficiency of the instruction cache is always halved while the execution throughput does not decrease. Further, the third embodiment has a demerit that it is not very effective even when applied to a branch to a wide range. By combining both, the disadvantages of each other can be avoided.

[Other combinations]
Combinations other than those listed here are also possible, and the mutual effects can be further improved. For example, by combining the first or second embodiment, the third embodiment, and the fourth embodiment, the above-described effects can be further improved.

  The embodiment of the present invention shows an example for embodying the present invention. As clearly shown in the embodiment of the present invention, the matters in the embodiment of the present invention and the claims Each invention-specific matter in the scope has a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present invention having the same names as the claims have a corresponding relationship. However, the present invention is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute the series of procedures or a recording medium storing the program May be taken as As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

DESCRIPTION OF SYMBOLS 11 Instruction fetch stage 12 Adder 13 Next implement fetch part 14 Next line branch destination line prefetch part 17, 170, 171 Prefetch queue 18, 111 Program counter 21 Instruction decode stage 31 Register fetch stage 41 Instruction execution stage 110 Processor core 112 Instruction register 113 instruction decoder 114 execution unit 115 register file 120 instruction cache 130 data cache 140 system memory 150 next-implement fetch unit 151 setting step address register 152 multiplication unit 153 prefetch start address setting register 154 address comparison unit 155 instruction type setting register 156 execution number setting Register 157 Instruction type comparison unit 158 execution times Counter 159 Execution count comparison section 160 Packet demultiplexer 180 Instruction queue 191 Instruction dictionary index 192 Instruction dictionary table 250 Next line branch destination line prefetch section 320 Instruction payload 411 Program holding section 412 Branch profile holding section 413 Instruction packet holding section 420 Instruction packet generation Section 430 Branch prediction flag setting section 440 Instruction compression section 450 Instruction packet separation section 460 Branch prediction flag determination section 470 Instruction prefetch section 480 Instruction decompression section 490 Instruction execution section 510 Program execution state generation section 520 Detection state setting section 530 Instruction prefetch timing detection Section 570 Instruction prefetch section 590 Instruction execution section 610 Instruction fetch section 620 Instruction decode section 630 Instruction execution section 640 Addition Control register 650 Addition control unit 660 Program counter 701 Program holding unit 702 Object code holding unit 710 Branch instruction extraction unit 720 Branch instruction arrangement unit 730 Branch destination instruction arrangement unit 740 Object code generation unit 750 Prefetch timing detection unit 760 Next implement fetch unit 770 Branch destination line prefetch unit 790 Prefetch address register

Claims (7)

Indicates the high possibility of branching to an instruction that is not included in either the instruction payload or the next instruction payload due to an instruction payload obtained by dividing the instruction sequence of the program by a predetermined size and a branch instruction included in the instruction payload. An instruction packet holding unit for holding an instruction packet including an instruction header including branch prediction information;
An instruction packet separation unit for separating the instruction packet held in the instruction packet holding unit into the instruction payload and the instruction header;
Based on the branch prediction information included in the instruction header, there is a high possibility of branching to an instruction not included in either the instruction payload or the next instruction payload by a branch instruction included in the instruction payload corresponding to the instruction header. A branch prediction information determination unit for instructing prefetch suppression of the next instruction packet,
An instruction fetch device comprising: an instruction prefetch unit that executes prefetch of the next instruction packet unless the prefetch suppression is instructed.   The apparatus further comprises an instruction execution unit that reads an instruction sequence corresponding to the instruction dictionary reference instruction from the instruction dictionary table based on an instruction dictionary reference instruction included in the instruction payload separated by the instruction packet separation unit and decompresses the instruction string. The instruction fetch device according to claim 1.   3. The instruction fetch apparatus according to claim 2, further comprising: an instruction decompression unit that decompresses an instruction string from an instruction payload corresponding to the instruction header based on an instruction payload compression flag included in the instruction header. Indicates the high possibility of branching to an instruction that is not included in either the instruction payload or the next instruction payload due to an instruction payload obtained by dividing the instruction sequence of the program by a predetermined size and a branch instruction included in the instruction payload. An instruction packet holding unit for holding an instruction packet including an instruction header including branch prediction information;
An instruction packet separation unit for separating the instruction packet held in the instruction packet holding unit into the instruction payload and the instruction header;
An instruction execution unit that executes an instruction sequence included in the instruction payload separated by the instruction packet separation unit;
Based on the branch prediction information included in the instruction header, there is a high possibility of branching to an instruction not included in either the instruction payload or the next instruction payload by a branch instruction included in the instruction payload corresponding to the instruction header. A branch prediction information determination unit for instructing prefetch suppression of the next instruction packet,
A processor comprising: an instruction prefetch unit that executes prefetch of the next instruction packet and supplies the next instruction packet to the instruction packet separation unit unless the prefetch suppression is instructed. Indicates the high possibility of branching to an instruction that is not included in either the instruction payload or the next instruction payload due to an instruction payload obtained by dividing the instruction sequence of the program by a predetermined size and a branch instruction included in the instruction payload. An instruction packet separation procedure for separating the instruction packet held in an instruction packet holding unit that holds an instruction packet including an instruction header including branch prediction information into the instruction payload and the instruction header;
Based on the branch prediction information included in the instruction header, there is a high possibility of branching to an instruction not included in either the instruction payload or the next instruction payload by a branch instruction included in the instruction payload corresponding to the instruction header. Branch prediction information determination procedure for instructing prefetch suppression of the next instruction packet,
And an instruction prefetch procedure for executing prefetch of the next instruction packet unless the prefetch suppression is instructed. An instruction packet generation unit that generates an instruction packet including an instruction payload and an instruction header obtained by dividing a program instruction sequence into predetermined sizes;
For each of the instruction payloads, branch prediction information indicating the likelihood of branching to an instruction not included in either the instruction payload or the next instruction payload due to a branch instruction included in the instruction payload is included in the instruction payload. A branch prediction information setting unit set in the corresponding instruction header;
An instruction packet generation apparatus comprising: an instruction packet holding unit that holds an instruction packet including an instruction header in which the branch prediction information is set.   When the branch prediction information in two consecutive instruction packets indicates that there is a high possibility that a branch will occur to an instruction that is not included in either the instruction payload of the instruction packet or the next instruction payload. The instruction packet generation device according to claim 6, further comprising an instruction compression unit that compresses an instruction between the two branch instructions so that the two branch instructions included in the instruction packet can be accommodated in the same instruction payload.

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