JP2011205449A - Frequency conversion device and frequency conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency conversion device and a frequency conversion method, capable of starting frequency conversion without depending upon a frequency of a synchronizing signal.

SOLUTION: The frequency conversion device includes a branching filter 11 which frequency-splits an input analog signal Xm into frequency bands of N channels, frequency conversion units 12-1 to 12-N which frequency-convert analog signals Xm of the respective channels into intermediate frequency signals IF1 to IFN, ADCs 13-1 to 13-N which sample and convert the intermediate frequency signals IF1 to IFN into digital signals D1 to DN, and a phase detection unit 20 which detects a phase ϕ_R at any timing of sampling by the ADCs 13-1 to 13-N when a reference time T_R which is a time interval longer than cycles of respective local signals L₁ to L_N and repeats in each timing synchronized with the respective local signals L₁ to L_N is regarded as one cycle.

COPYRIGHT: (C)2012,JPO&INPIT

Description

  The present invention relates to a frequency conversion device and a frequency conversion method, and more particularly to a frequency conversion device and a frequency conversion method for correcting an error that occurs when frequency conversion is performed by demultiplexing an analog signal into a plurality of frequency bands.

  An apparatus for converting a frequency of a wideband analog signal has been proposed (for example, see Patent Document 1). The apparatus of Patent Document 1 demultiplexes a wideband analog signal into a plurality of channels having different frequency bands, performs frequency conversion for each channel, converts the signal into an intermediate frequency signal, and converts the intermediate frequency signal into a digital signal. The digital signal of each channel is synthesized by matching the phase of each digital signal.

  In the apparatus of Patent Document 1, each local signal is generated in synchronization with a common synchronization signal in order to match the phase of each digital signal, and frequency conversion is started when the synchronization signal rises.

JP 2009-246958 A

  In the apparatus of Patent Document 1, since frequency conversion is started at the rising edge of the synchronization signal, there is a problem that jitter (variation) at the start of measurement depends on the frequency of the synchronization signal.

  Accordingly, an object of the present invention is to provide a frequency conversion device and a frequency conversion method capable of starting frequency conversion without depending on the frequency of the synchronization signal.

  In order to achieve the above object, the frequency conversion device and the frequency conversion method of the present invention have a time interval longer than the period of each local signal and a reference time repeated at each timing synchronized with each local signal as one period. It is characterized in that the phase when detected is detected.

  Specifically, the frequency conversion device of the present invention includes a demultiplexing unit (11) for demultiplexing an input analog signal into a plurality of frequency bands, and an analog signal from the demultiplexing unit synchronized with each other and Using the local signals having different frequencies, the plurality of frequency conversion units (12-1 to 12-N) for frequency conversion and the intermediate frequency signals from the respective frequency conversion units are sampled and converted into digital signals. The plurality of ADCs (13-1 to 13-N), a storage unit (18) for storing output values of digital signals from the plurality of ADCs in association with sampling timing, and the period of each local signal Sample of the plurality of ADCs when a reference time which is a longer time interval and is repeated every time the phases of the local signals are synchronized is one cycle. Comprising phase detecting section for detecting a phase at any timing grayed (20), the.

  Since a demultiplexing unit, a plurality of frequency conversion units, a plurality of ADCs, and a storage unit are provided, it is possible to perform frequency conversion of an input analog signal by synthesizing digital signals from the ADCs. it can. In addition, since the phase detection unit is provided, the phase of each digital signal from the ADC at the timing at which the phases of the local signals match can be calculated. Thereby, the frequency converter of the present invention can start frequency conversion without depending on the frequency of the synchronization signal.

  The frequency conversion device according to the present invention further includes a synchronization signal generation unit (15) that generates a synchronization signal having the reference time as one cycle, and the phase detection unit receives the synchronization signal from the synchronization signal generation unit as described above. A synchronization signal sampling unit (21) that samples at a timing synchronized with the sampling timing of a plurality of ADCs and converts it into a digital signal, and an output value detection unit that detects an output value of the digital signal from the synchronization signal sampling unit ( 22) and an output value calculation for calculating a phase at an arbitrary timing of sampling of the synchronization signal sampling unit using the output value of the digital signal from the output value detection unit as one cycle of the reference time Part (23).

  The frequency converter according to the present invention further includes a sampling clock generator (17) that generates a clock signal indicating the sampling timing of the ADC, and the phase detector receives the clock signal from the sampling clock generator. A counter (25) that changes the counter value every time and resets the counter value every reference time, a counter value detection unit (26) that detects the counter value of the counter, and a counter value from the counter value detection unit And a counter value calculation unit (27) for calculating a phase at an arbitrary timing at which the counter value is changed in the counter when the reference time is one cycle.

  Specifically, the frequency conversion method of the present invention demultiplexes an input analog signal into a plurality of frequency bands, performs frequency conversion using local signals that are synchronized with each other and have different frequencies, and converts an intermediate frequency signal. Output, sample the intermediate frequency signal, convert it to a digital signal, store the output value of the digital signal in association with the sampling timing, and have a time interval longer than the period of each local signal and each local signal A phase calculation procedure for detecting a phase at an arbitrary timing of the sampling when a reference time repeated at each timing at which the phases are synchronized is one cycle.

  The input analog signal is demultiplexed into multiple frequency bands, frequency-converted using local signals that are synchronized with each other and having different frequencies, and output an intermediate frequency signal. The intermediate frequency signal is sampled and converted into a digital signal. Since conversion is performed and the output value of the digital signal is stored in association with the sampling timing, the frequency conversion of the input analog signal can be performed by synthesizing the digital signals of the respective frequency bands. In addition, since the phase at an arbitrary sampling timing when the reference time is one cycle is detected, the phase of each digital signal at the timing at which the phases of the local signals coincide can be calculated. Thereby, the frequency conversion method of the present invention can start frequency conversion without depending on the frequency of the synchronization signal.

  In the frequency conversion method of the present invention, in the phase calculation procedure, the synchronization signal sampling in which the synchronization signal having the reference time as one cycle is sampled at a timing synchronized with the sampling timing of the intermediate frequency signal and converted into a digital signal. The reference time is defined as one cycle using a procedure, an output value detection procedure for detecting an output value of the digital signal converted by the synchronization signal sampling procedure, and an output value of the digital signal detected by the output value detection procedure And an output value calculation procedure for calculating a phase at an arbitrary timing of sampling of the synchronization signal.

  In the frequency conversion method of the present invention, a counter (25) that resets a counter value for each reference time is used in the phase calculation procedure, and the counter is displayed each time a clock signal indicating the sampling timing of the intermediate frequency signal is input. Using the counter value change procedure for changing the value, the counter value detection procedure for detecting the counter value after the change in the counter value change procedure, and the counter value detected in the counter value detection procedure, the reference time is set to one cycle. And a counter value calculation procedure for calculating a phase at an arbitrary timing for changing the counter value.

  According to the present invention, it is possible to provide a frequency conversion device and a frequency conversion method capable of starting frequency conversion without depending on the frequency of the synchronization signal.

An example of the frequency converter which concerns on Embodiment 1 is shown. An example of the input analog signal Xm is shown. Is an example of the relationship between the local signal _L 1 ~L _N and synchronizing signal R, (a) shows a local signal _{L 1,} (b) shows a local signal _{L 2,} (c) shows a local signal _{L N} , (D) shows the synchronization signal R. 2 shows an example of a phase detection unit according to the first embodiment. Is an example of the relationship between the digital signal D1~DN and the digital signal _{D R,} (a) shows the digital signal D1, (b) shows the digital signals D2, (c) shows the digital signals D3, (d) shows a digital signal _{D R.} An example of the frequency converter which concerns on Embodiment 2 is shown. An example of the phase detection part which concerns on Embodiment 2 is shown. It is an example of the relationship between the digital signals D1 to DN and the counter value. (A) shows the digital signal D1, (b) shows the digital signal D2, (c) shows the digital signal D3, and (d) shows the counter. It indicates the value _{D R.}

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
FIG. 1 shows an example of a frequency conversion device according to the first embodiment. The frequency conversion device according to the present embodiment includes a demultiplexing unit 11, frequency conversion units 12-1 to 12-N, ADCs 13-1 to 13-N, an arithmetic processing unit 14, a synchronization signal generating unit 15, A local signal generation unit 16, a sampling clock generation unit 17, a storage unit 18, a calibration signal generation unit 19, and a phase detection unit 20 are provided.

  FIG. 2 shows an example of the input analog signal Xm. The demultiplexing unit 11 demultiplexes the input analog signal Xm into N (where N is an integer of 2 or more) channels CH1 to CHN. For example, the frequency filter 11-1 extracts the frequency band of the channel CH1, and the frequency filter 11-N extracts the frequency band of the channel CHN.

Synchronizing signal generator 15 generates a synchronizing signal R to one cycle reference time T _R. The local signal generator 16 generates local signals L _{1 to} L _N that are synchronized with the synchronization signal R. Frequency conversion section 12-1 to 12-N, the analog signal Xm from the demultiplexing unit 11, and outputs an intermediate frequency signal IF1~IFN and frequency conversion using a local signal _L 1 ~L _N.

FIG. 3 shows an example of the relationship between the local signals L _{1 to} L _N and the synchronization signal R. (a) shows the local signal L ₁ , (b) shows the local signal L ₂ , and (c) shows the local signal. L represents _N , and (d) represents the synchronization signal R. The local signals L _{1 to} L _N have different frequencies f _{L1 to} f _LN that are higher than the frequency of the synchronization signal R and correspond to the frequency bands of the channels CH 1 to CHN. For example, the frequency f _L1 is a frequency equal to the difference between the center frequency f _C1 of the channel CH1 and the frequency f _IF1 of the intermediate frequency signal IF1. Synchronizing signal R, a reference time from time t0 to time t20 as one cycle is repeated for each reference time T _R. The local signals L _{1 to} L _N and the synchronization signal R have the same phase every time t0 to time t20.

  The sampling clock generator 17 generates a clock signal C indicating the sampling timing of the ADCs 13-1 to 13-N. The ADCs 13-1 to 13-N sample the intermediate frequency signals IF1 to IFN from the frequency converters 12-1 to 12-N at timing synchronized with the clock signal C and convert them to digital signals D1 to DN.

  The arithmetic processing unit 14 combines the digital signals D1 to DN from the ADCs 13-1 to 13-N in correspondence with the frequency bands of the channels CH1 to CHN. Thereby, the frequency conversion device according to the present embodiment can perform frequency conversion of the input analog signal Xm.

The frequency conversion device according to the present embodiment executes the frequency conversion method according to the present embodiment. The frequency conversion method according to the present embodiment has a phase calculation procedure. The phase calculation procedure, demultiplexes the analog signal Xm of the demultiplexer 11 is input to a plurality of frequency bands, the frequency conversion section 12-1 to 12-N is frequency-converted using the local signal L ₁ ~L _N The intermediate frequency signals IF1 to IFN are output, the ADCs 13-1 to 13-N sample the intermediate frequency signals IF1 to IFN and convert them into digital signals D1 to DN, and the arithmetic processing unit 14 outputs the digital signals D1 to DN. The value is stored in the storage unit 18 in association with the sampling timing.

Further, the phase calculation procedure, the phase detector 20 detects the phase phi _R of the synchronization signal R at any time of the sampling. Thus, the phase detector 20, when the reference time _{T R} to one cycle, detecting the phase phi _R at any timing of the sampling of ADC13-1~13-N.

  FIG. 4 shows a configuration example of the phase detection unit 20. The phase detection unit 20 includes a synchronization signal sampling unit 21, an output value detection unit 22, and an output value calculation unit 23. In this case, in the phase calculation procedure, a synchronization signal sampling procedure, an output value detection procedure, and an output value calculation procedure are executed in order.

The synchronous signal sampling procedure, synchronization signal sampling unit 21 shown in FIG. 4, and converting the sampled at timing synchronized synchronization signals R with the clock signal C into a digital signal D _R. At this time, the synchronization signal sampling unit 21 performs sampling at a timing synchronized with the sampling timing of the plurality of ADCs 13-1 to 13 -N. The output value detection procedure, the output value detecting section 22 shown in FIG. 4, the output value of the digital signal D _R which is converted by the synchronization signal sampling procedure, to detect with the sampling timing of the digital signal D _R. The output value calculation procedure, the output value calculating unit 23 shown in FIG. 4, using the output value of the digital signal D _R which is detected by the output value detection procedure, when the reference time T _R to the one period, the digital signal D The phase at an arbitrary timing of _R sampling is calculated.

Here, the digital signal _{D R,} because they are sampled at a timing synchronized with the clock signal C, the timing of the sampling of the digital signal _{D R} is consistent with the sampling ADC13-1~13-N. Therefore, the output value calculating unit 23, when the reference time _{T R} to one cycle, it is possible to calculate the phase phi _R at any timing of the sampling of ADC13-1~13-N.

Figure 5 is an example of the relationship between the digital signal D1~DN and the digital signal _{D R,} (a) shows the digital signal D1, (b) shows the digital signals D2, (c) shows the digital signals D3 , (d) shows the digital signal _{D R.} ADC13-1~13-N and the synchronization signal sampling unit 21, shown for the case of 20 times sampled during the reference time _{T R} from time t0 to time t20.

For example, if an arbitrary timing of the sampling is the time t5, the output value detection unit 22 detects the output value of the digital signal D _R from time t5 to time t20. Output value calculating section 23, by Fourier transform of the output value of the digital signal D _R from time t5 to time t20, and calculates the phase phi _R at the timing of time t5.

Arithmetic processing unit 14, by using the phase phi _R, it is possible to calculate the phase of the local signal _L 1 ~L _N at time t0 where the phase of the local signal _L 1 ~L _N and synchronization signals R are identical.
For example, the phase phi ₁ of the local signal _{L 1} is
φ ₁ = φ _R / (2πf _R ) · (2πf _c1 )
Can be used to calculate. The same applies to the phases of the local signals L _{2 to} L _N. For this reason, even if the frequency conversion is not started when the synchronization signal R rises, the phases of the digital signals D1 to DN can be matched.

The frequency conversion device according to the present embodiment may measure the phase difference between the digital signals D1 to DN and perform correction using the measured phase difference. In this case, the calibration signal generator 19 generates a calibration signal Xr having frequencies fa _{2 to} fa _N at the boundaries of the frequency bands of the channels CH1 to CHN. For example, the calibration signal Xr having the frequency fa ₂ at the boundary between the frequency bands of the channels CH1 and CH2 is generated.

In this case, the demultiplexing unit 11 demultiplexes the calibration signal Xr into the channel CH1 and the channel CH2. The frequency converter 12-1 and the ADC 13-1 convert the frequency of the calibration signal Xr and output the digital signal D1 to the arithmetic processing unit 14. The frequency conversion unit 12-2 and the ADC 13-2 frequency-convert the calibration signal Xr and output the digital signal D2 to the arithmetic processing unit 14. The storage unit 18 stores the output values of the digital signals D1 and D2 in association with the sampling timing in the ADCs 13-1 and 13-2. The phase detector 20 detects the phase phi _R of the synchronization signal R at any timing of the sampling of the sync signals R.

At this time, the phase φ ₁ and the phase φ ₂ of the local signal L ₁ and the local signal L ₂ at time t 0 when the phases of the local signals L _{1 to} L _N and the synchronization signal R coincide with _{each other} are
φ ₁ = φ _R / (2πf _R ) · (2πf _c1 )
φ ₂ = φ _R / (2πf _R ) · (2πf _c2 )
It becomes. Therefore, by calculating the difference between φ ₁ and φ ₂ , it is possible to measure the phase difference between the digital signals D 1 and D 2 at the time t 0 when the phases of the local signals L _{1 to} L _N and the synchronization signal R match. The phase difference between the digital signals D2 to DN can be measured in the same manner. As described above, the frequency conversion device according to the present embodiment can measure the phase difference between the digital signals D2 to DN without starting the frequency conversion when the synchronization signal R rises. Thereby, the phase difference caused by the phase rotation of each of the local signals L _{1 to} L _N depending on the arbitrary sampling timing included in the phase difference of the digital signals D 2 to DN at the time of measurement can be removed. For this reason, the jitter (variation) at the start of measurement depending on the frequency f _R of the synchronization signal R can be reduced.

  When the arithmetic processing unit 14 synthesizes the digital signals D1 to DN to reconstruct the analog signal Xm, the arithmetic processing unit 14 corrects the phase difference of the measured digital signals D1 to DN, and then adjusts the frequency band of each channel CH1 to CHN. Combining them in correspondence. Since the frequency converter according to the present embodiment can reduce jitter (variation) at the start of measurement depending on the frequency of the synchronization signal R, the phase difference between the digital signals D1 to DN can be accurately corrected. it can.

(Embodiment 2)
FIG. 6 shows an example of the frequency conversion device according to the second embodiment. The frequency converter according to the present embodiment differs from the frequency converter shown in FIG. 1 in the configuration and operation of the phase detector 20. Accordingly, the sampling clock generation unit 17 generates a clock signal C that is synchronized with the synchronization signal R from the synchronization signal generation unit 15, and outputs the clock signal C to the ADCs 13-1 to 13 -N and the phase detection unit 20. .

  FIG. 7 shows a configuration example of the phase detection unit 20. The phase detection unit 20 includes a counter 25, a counter value detection unit 26, and a counter value calculation unit 27. In this case, in the phase calculation procedure, a counter value change procedure, a counter value detection procedure, and a counter value calculation procedure are executed in order.

The counter value change procedure, the counter 25, the counter value B is changed from the sampling clock generator 17 every time the clock signal C is inputted, and resets the counter value B to each reference time T _R. In the counter value detection procedure, the counter value detection unit 26 detects the counter value B of the counter 25 together with the output timing of the counter value B. The counter value calculation procedure, the counter value calculating unit 27, using a counter value B from the counter value detection unit 26, when the reference time T _R to one cycle, of any of the counter 25 changes the counter value B to calculate the phase phi _R in the timing.

Here, since the counter value B is changed every time the clock signal C is input, the output timing of the counter value B coincides with the sampling timing of the ADCs 13-1 to 13-N. Therefore, the counter value determination unit 27, when the reference time _{T R} to one cycle, it is possible to calculate the phase phi _R at any timing of the sampling of ADC13-1~13-N.

FIG. 8 shows an example of the relationship between the digital signals D1 to DN and the counter value B. (a) shows the digital signal D1, (b) shows the digital signal D2, (c) shows the digital signal D3, (D) shows the counter value B. ADC13-1~13-N shows a case of 20 times sampled during the reference time _{T R} from time t0 to time t20. Counter 25, during the reference time _{T R} from time t0 to time t20, in synchronization with the clock signal C, and increases the counter value B by 1 from 0 to 19.

For example, when the arbitrary timing of sampling is time t5, the counter value B is 06. In this case, the counter value detection unit 26 detects the counter value “06” from the counter 25. When the reference time _{T R} to one cycle, the phase phi _R counter value B expressed by B / 20 · (2π). Counter value determination unit 27, by calculating the 06/20 · (2π), it is possible to calculate the phase phi _R at the timing of time t5.

Arithmetic processing unit 14, by using the phase phi _R, it is possible to calculate the phase of the local signal _L 1 ~L _N at time t0 where the phase of the local signal _L 1 ~L _N and synchronization signals R are identical. For this reason, even if the frequency conversion is not started when the synchronization signal R rises, the phases of the digital signals D1 to DN can be matched.

  The present invention can be used in the information communication industry.

11: demultiplexing units 11-1, 11-2, 11-N: frequency filters 12-1, 12-2, 12-N: frequency converting units 13-1, 13-2, 13-N: ADC
14: arithmetic processing unit 15: synchronization signal generation unit 16: local signal generation unit 17: sampling clock generation unit 18: storage unit 19: calibration signal generation unit 20: phase detection unit 21: synchronization signal sampling unit 22: output value detection Unit 23: Output value calculation unit 25: Counter 26: Counter value detection unit 27: Counter value calculation unit

Claims (6)

A demultiplexing unit (11) for demultiplexing an input analog signal into a plurality of frequency bands;
A plurality of frequency converters (12-1 to 12-N) for frequency-converting analog signals from the demultiplexing units using local signals that are synchronized with each other and have different frequencies;
A plurality of ADCs (13-1 to 13-N) for sampling and converting the intermediate frequency signals from the respective frequency conversion units into digital signals;
A storage unit (18) for storing output values of digital signals from the plurality of ADCs in association with sampling timing;
Phases at arbitrary timings of sampling of the plurality of ADCs, where a reference time which is a time interval longer than the period of each local signal and is repeated every time the phases of the local signals are synchronized is one period A phase detector (20) for detecting
A frequency conversion device comprising: A synchronization signal generator (15) for generating a synchronization signal having the reference time as one cycle;
The phase detector
A synchronization signal sampling unit (21) that samples the synchronization signal from the synchronization signal generation unit at a timing synchronized with the sampling timing of the plurality of ADCs and converts the sampling signal to a digital signal;
An output value detector (22) for detecting an output value of a digital signal from the synchronization signal sampling unit;
Using the output value of the digital signal from the output value detection unit, an output value calculation unit (23) for calculating a phase at an arbitrary timing of sampling of the synchronization signal sampling unit when the reference time is one cycle When,
The frequency converter according to claim 1, further comprising: A sampling clock generator (17) for generating a clock signal indicating the sampling timing of the ADC;
The phase detector
A counter (25) that changes a counter value every time a clock signal is input from the sampling clock generator, and resets the counter value every reference time;
A counter value detector (26) for detecting a counter value of the counter;
A counter value calculation unit (27) for calculating a phase at an arbitrary timing for changing the counter value in the counter, using the counter value from the counter value detection unit as one cycle;
The frequency converter according to claim 1, further comprising:   The input analog signal is demultiplexed into multiple frequency bands, frequency-converted using local signals that are synchronized with each other and having different frequencies, and output an intermediate frequency signal. The intermediate frequency signal is sampled and converted into a digital signal. Converting and storing the output value of the digital signal in association with the sampling timing, and a reference time which is repeated at every timing which is longer than the period of each local signal and the phase of each local signal is synchronized A frequency conversion method including a phase calculation procedure for detecting a phase at an arbitrary timing of sampling when a period is set. In the phase calculation procedure,
A synchronization signal sampling procedure in which the synchronization signal having the reference time as one cycle is sampled at a timing synchronized with the sampling timing of the intermediate frequency signal and converted into a digital signal;
An output value detection procedure for detecting an output value of the digital signal converted by the synchronization signal sampling procedure;
Using the output value of the digital signal detected in the output value detection procedure, an output value calculation procedure for calculating a phase at an arbitrary timing of sampling of the synchronization signal when the reference time is one cycle;
The frequency conversion method according to claim 4, further comprising: In the phase calculation procedure,
A counter value changing procedure for changing the counter value every time a clock signal indicating the sampling timing of the intermediate frequency signal is input, using a counter (25) that resets the counter value at each reference time;
A counter value detection procedure for detecting the counter value after the change in the counter value change procedure;
Using the counter value detected in the counter value detection procedure, a counter value calculation procedure for calculating a phase at an arbitrary timing for changing the counter value when the reference time is one cycle;
The frequency conversion method according to claim 4, further comprising:

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