JP2011203970A - Disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk device 1 which includes a capacitor Cs supplying power at power failure, stores data in a nonvolatile memory 14 via a volatile memory 15, and stores the data stored in the volatile memory 15 to the nonvolatile memory 14 at power failure, while accurately measuring capacity of the capacitor Cs and to reliably determine service life of the capacitor Cs.SOLUTION: The disk device includes: a load 21 for measurement as a load of the capacitor Cs; switches SW1 and SW2 provided on a power input side and a power output side with respect to the capacitor Cs, respectively; and a switch SW3 provided between the capacitor Cs and the load 21 for measurement and turned on and off inversely with on/off of the switches SW1 and SW2. The switch SW3 is turned on at a predetermined time. Discharge time Ta until the capacitor Cs becomes equal to or lower than a predetermined voltage Va is measured. The capacity of the capacitor Cs is estimated on the basis of the discharge time Ta.

Description

  The present invention relates to a technique for determining the life of a power backup capacitor in a disk device such as a semiconductor disk device.

  In a semiconductor disk device composed of a nonvolatile memory such as a flash memory, the writing speed is slow and the number of rewrites is limited due to the characteristics of the nonvolatile memory used.

  In order to solve this problem, a volatile memory such as a DRAM capable of high-speed writing is used as a cache memory, the speed is increased by writing to the nonvolatile memory after writing to the volatile memory, and A write-back cache method with a reduced number of writes is used.

  In this write-back cache system, a large-capacity capacitor such as a supercapacitor is provided to prevent the loss of data in the volatile memory when the power is cut off. Data is written out, and the contents of the volatile memory are written into the nonvolatile memory (see, for example, Patent Document 1 and Patent Document 2).

  FIG. 14 shows the configuration of the conventional disk device 100. As shown in the figure, the conventional disk device 100 includes a power input unit 120 that constitutes a power source and a memory main body 10 that comprises a memory and the like.

  The power input unit 120 includes a capacitor Cs. The capacitor Cs is charged with power from the DC input Vcc, and the diode logic of the power from the DC input Vcc and the power from the capacitor Cs by the diodes D1 to D3. The sum is taken and supplied to the memory body 10 as a DC output Vdd. In the following description, the voltage drop of the diode D2 is assumed to be small enough to be ignored for convenience.

  On the other hand, the memory main unit 10 temporarily holds the control unit 13 that controls the whole and the write data transmitted from the host device (not shown) via the I / F unit 11 and the management data of the disk device 100. The volatile memory 15 and the nonvolatile memory 14 that holds the write data.

  With the above configuration, the conventional disk device 100 operates as shown in the time chart of FIG. That is, first, when the DC input Vcc of the voltage Vs is turned on (timing T1), power is supplied to the memory body 10 via the diode D3, the memory body 10 is activated, and the memory body 10 is activated. During the time processing, the capacitor Cs is charged by the power supplied via the diode D1 (timing T2).

  Then, the memory main unit 10 finishes the process at the time of startup and shifts to the normal operation, and the write data and the management data of the disk device 100 transmitted from the host device etc. via the I / F unit 11 are temporarily stored. After being written to the volatile memory 15, it is sequentially written to the nonvolatile memory.

  When the DC input Vcc is cut off (timing T3), the voltage of the capacitor Cs, that is, the DC output Vdd is decreased to the operable voltage Vw of the memory body 10 using the power charged in the capacitor Cs. At (timing T4), the data written in the volatile memory 15 is written into the nonvolatile memory 14 as the write-back cache data writing process described above.

  By the way, the capacitor Cs that backs up the power source of the volatile memory 15 is composed of a supercapacitor, an electrolytic capacitor, or the like as a large-capacity capacitor. There is.

  Thus, when the capacity of the capacitor Cs decreases, it becomes difficult to back up the power supply during the time required for writing the write-back cache data, and all the data written in the volatile memory 15 is stored in the nonvolatile memory 14. It becomes impossible to write.

  For this reason, it is necessary to estimate the life of the capacitor Cs in advance and warn the life of the capacitor Cs by an alarm or the like.

  As a technique for predicting the life of the capacitor Cs, there is a technique for continuously measuring the charging voltage and the ambient temperature to estimate the life of the capacitor Cs (see, for example, Patent Document 3).

JP 2006-163753 A JP 2006-252535 A Special table 2009-503724

  However, in the above conventional technique, the life of the capacitor is estimated using indirect measured values such as the charging voltage and the ambient temperature of the capacitor, so that an estimation error of the capacity occurs and it is necessary to write out the write-back cache data. There was a risk that sufficient time could not be secured and all write-back cache data could not be written out.

  The present invention employs the following configuration in order to solve the above-described problems. That is, a disk device having a capacitor capable of supplying power when the power is shut off, storing data in the nonvolatile memory via the volatile memory, and storing the data stored in the volatile memory in the nonvolatile memory when the power is shut off The load means serving as a load of the capacitor, the first switch and the second switch provided on the power input side and the power output side to the capacitor, respectively, and provided between the capacitor and the load means. Switch means comprising a third switch that turns on and off the first switch and the second switch, and at a predetermined time, the third switch is turned on at a predetermined time. The discharge time until the voltage became lower than the voltage was measured, so that the capacity of the capacitor could be estimated based on the discharge time.

  According to the disk device of the present invention, the capacitor is provided that can supply power when the power is shut off, stores data in the nonvolatile memory via the volatile memory, and stores the data stored in the volatile memory when the power is shut off. A disk device that can be stored in a volatile memory, comprising: a load means serving as a load of the capacitor; a first switch and a second switch provided on a power input side and a power output side to the capacitor; the capacitor; Switch means comprising a first switch and a third switch that is turned on and off opposite to the on / off state of the second switch, and the third switch is provided at a predetermined time. It is possible to estimate the capacity of the capacitor based on the discharge time by measuring the discharge time until the capacitor is turned on and below the predetermined voltage. Having to, with high accuracy can be estimated the capacitance of the capacitor, it can be reliably determined the lifetime of the capacitor.

1 is a configuration diagram of a disk device of Example 1. FIG. 1 is a configuration diagram of a measurement load circuit in Example 1. FIG. 6 is an operation explanatory diagram of a power input unit of the disk device of Embodiment 1. FIG. 6 is an operation explanatory diagram of a power input unit of the disk device of Embodiment 1. FIG. FIG. 3 is a time chart diagram of a power input unit of the disk device according to the first embodiment. FIG. 6 is a time chart diagram of a power input unit of the disk device according to the second embodiment. FIG. 6 is a configuration diagram of a disk device according to a third embodiment. FIG. 11 is an operation explanatory diagram of a power input unit of the disk device of Example 3. FIG. 11 is an operation explanatory diagram of a power input unit of the disk device of Example 3. FIG. 11 is an operation explanatory diagram of a power input unit of the disk device of Example 3. FIG. 6 is a time chart diagram of a power input unit of the disk device according to the third embodiment. FIG. 6 is a time chart diagram of a power input unit of a disk device of Example 4. FIG. 10 is a time chart diagram of a power input unit of a disk device according to a fifth embodiment. It is a block diagram of a conventional disk device. It is a time chart which shows operation | movement of the conventional disc apparatus.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element common to drawing.

(Constitution)
FIG. 1 shows the configuration of a disk device 1 according to the first embodiment. As shown in FIG. 1, the disk device 1 according to the first embodiment includes a power input unit 20 that constitutes a power source and a memory main unit 10 that includes a memory and the like. Since the memory main body 10 has the same configuration as that of the conventional disk device, detailed description thereof is omitted for the sake of brevity.

  In the power input unit 20, the diode D1 and the diode D2 are connected to the capacitor Cs via the switch SW1 and the switch SW2, respectively, and the power from the DC input Vcc is charged, and the power and the capacitor from the DC input Vcc are charged. A DC output Vdd, which is a diode logical sum of power from Cs, is supplied to the memory body 10. In the following description, the voltage drop of the diode D2 is assumed to be small enough to be ignored for convenience.

  In the power supply input unit 20, the switch SW3 is connected to the capacitor Cs, and a measurement load 21 is connected as load means on the capacitor Cs side. The switches SW1 to SW3 may be configured by on / off elements such as relay circuits and FETs.

  An example of the configuration of the measurement load 21 is shown in FIG. As shown in the figure, the measurement load 21 of the disk device 1 according to the first embodiment includes a load circuit 21a that is a load of the capacitor Cs and a voltage measurement circuit 21b that measures an input voltage Vx that is a voltage of the capacitor Cs. Thus, the measurement result of the voltage measurement circuit 21b is output as a voltage measurement result signal Vz as a signal that can be referred to from the control unit 12 or the like via a D / A converter (not shown).

(Operation)
With the above configuration, the disk device 1 according to the first embodiment operates as follows. This operation will be described in detail with reference to the operation explanatory diagrams of FIGS. 3 and 4 and the time chart of FIG.

  First, FIG. 3 shows the states of the switches SW1 to SW3 of the power input unit 20 and the current flow in a normal state. As shown in the figure, normally, the switches SW1 and SW2 are turned on, the switch SW3 is turned off, the current from the DC input Vcc flows through the capacitor Cs, and DC is output from the capacitor Cs to the memory body 10. At this time, the capacitor Cs is charged.

  FIG. 4 shows the states of the switches SW1 to SW3 and the current flow when measuring the capacitance of the capacitor Cs. As shown in the figure, the switches SW1 and SW2 are turned off, the switch SW3 is turned on, a current is passed through the measurement load 21, and the voltage of the capacitor Cs, that is, the voltage measurement result signal Vz is equal to or lower than a predetermined reference voltage Va. The time Ta until is reached is measured. As described above, the on / off of the switches SW1 and SW2 and the on / off of the switch SW3 are contrary to each other.

  Next, the operation of the disk device 1 according to the first embodiment will be described in more detail with reference to the time chart of FIG.

  First, when the power is turned on, the DC input Vcc of the voltage Vs rises (timing T1), and since the switches SW1 and SW2 are on and SW3 is off in the normal mode, the capacitor Cs is charged. When charging is completed, the switches SW1 and SW2 are turned off as the capacity measurement mode, the switch SW3 is turned on, and the capacity measurement of the capacitor Cs is started (timing T5).

  Then, a current Ta flows from the capacitor Cs to the measurement load 21, and a time Ta until the voltage of the capacitor Cs, that is, the voltage measurement result signal Vz becomes equal to or lower than a predetermined reference voltage Va is measured.

  Then, when the control unit 12 determines that the write-back cache data write time has been reduced to a capacity that cannot be taken sufficiently based on the measured time Ta, the capacitor Cs has reached the end of its life. Is notified to the upper level by the SMART information. In addition, in an electric double layer capacitor such as a supercapacitor, the voltage drops linearly due to discharge, so that the capacity can be estimated from the time Ta until the voltage drops below a predetermined reference voltage Va.

  After the capacitance measurement is finished (timing T6), the switches SW1 and SW2 are turned on, the switch SW3 is turned off, the capacitor Cs is charged again, and when the charging is completed (timing T7), the memory body 10 The process shifts to a normal operation for writing data to the nonvolatile memory 14 via the volatile memory 15.

  Note that the time until the transition to the normal operation, that is, the timings T1 to T7, is that the activation time of the memory body 10 is about 1 second, the charging time of the capacitor Cs is about 1 second, and the measurement time of the capacitor Cs is 3 Since the recharge time is about 1 second in about seconds, the total is about 6 seconds. Accordingly, since the startup time of the disk device is normally about 10 seconds, the normal operation can be shifted during this time, and the startup time of the disk device 1 is not delayed in order to measure the capacity.

  When the DC input Vcc is cut off during normal operation, the power charged in the capacitor Cs is used to write the write-back cache data of the volatile memory 15 to the nonvolatile memory 14 and finish (timing T3). ~ T4).

(Effect of Example 1)
As described above, the disk device according to the first embodiment includes the capacitor that can supply power when the power is shut off, stores data in the nonvolatile memory via the volatile memory, and stores the data in the volatile memory when the power is shut off. A disk device capable of storing the stored data in the nonvolatile memory, a load means serving as a load of the capacitor, a first switch and a second switch respectively provided on a power input side and a power output side to the capacitor, A switch means provided between the capacitor and the load means, and comprising a third switch that is turned on and off contrary to on and off of the first switch and the second switch, and the capacitor at the time of start-up After completion of charging, the third switch is turned on to measure the discharge time until the capacitor becomes a predetermined voltage or less. Since to be able to estimate the capacity of the capacitor Zui, accuracy can be estimated the capacitance of the capacitor, can be reliably determined the lifetime of the capacitor.

(Constitution)
Since the configuration of the disk device of the second embodiment is the same as that of the first embodiment, detailed description thereof is omitted for the sake of brevity.

(Operation)
The operation of the disk device of the second embodiment will be described in detail below with reference to the time chart of FIG. Note that the operation is the same as that of the first embodiment except for the limited operation A of the memory body 10 that is performed from the timing T5 at which the capacitance measurement of the capacitor Cs is started to the timing T7 at which charging is completed again and the normal operation is started. Detailed description thereof is omitted for simplification.

  In the limited operation A, the read process for reading data from the nonvolatile memory 14 can be performed in the same manner as the normal operation. In the write process for writing to the nonvolatile memory 14, the received write data is immediately nonvolatile. Write to the memory 14 and write-back cache operation using the volatile memory 15 are not performed.

  By providing the limited operation A as described above, in the limited operation A from the timing T5 to the timing T7, the write speed is decreased in order to write the write data to the nonvolatile memory 14 each time. The read / write operation can be performed while measuring the capacity of Cs.

(Effect of Example 2)
As described above, according to the disk device of the second embodiment, the write data is immediately written to the nonvolatile memory from the timing when the capacitance measurement of the capacitor is started until the timing when the charging is completed again and the normal operation is started. As a result, the time until the nonvolatile memory can be accessed can be shortened.

(Constitution)
FIG. 7 shows the configuration of the disk device 1 according to the third embodiment. As shown in the figure, in the disk device 1 of the third embodiment, the power input unit 20 includes two capacitors Csa and Csb, and the diode D1a and the diode D2a are connected to the capacitor Csa via the switch SW1a and the switch SW2a, respectively. And the diode D1b and the diode D2b are connected to the capacitor Csb via the switches SW1b and SW2b, respectively, and charge the power from the DC input Vcc. In this configuration, a DC output Vdd, which is a diode OR of the power from the DC input Vcc and the power from the capacitors Csa and Csb, is supplied to the memory body 10.

  Further, the capacitors Csa and Csb are connected to the measurement load 21 shared via the switches SW3a and SW3b, respectively. Since the memory main body 10 has the same configuration as that of the conventional disk device, detailed description thereof is omitted for the sake of brevity.

(Operation)
The operation of the disk device 1 according to the third embodiment will be described in detail below with reference to the operation explanatory diagrams of FIGS. 8 to 10 and the time chart of FIG.

  FIG. 8 shows the states of the switches SW1a to SW3a and SW1b to SW3b of the power input unit 20 at normal times and the flow of current. As shown in the figure, the switches SW1a and SW2a are turned on, the switch SW3a is turned off, the switches SW1b and SW2b are turned on and SW3b is turned off, and the current from the DC input Vcc is supplied to the capacitors Ca and Cb for charging. However, the data is also output to the memory body 10 via the diodes D2a and D2b. At this time, the DC input Vcc is also output to the memory main body 10 via the diode D3 as a diode logical sum with the output.

  FIG. 9 shows the states of the switches SW1a to SW3a and SW1b to SW3b and the current flow when measuring the capacitance of the capacitor Csa. The switches SW1a and SW2a are turned off, the switch SW3a is turned on, and a current is passed through the measurement load 21 connected to the capacitor Csa until the voltage of the capacitor Csa, that is, the voltage measurement result signal Vz becomes equal to or lower than a predetermined reference voltage Va. The time Ta is measured. During this time, the output of the DC voltage to the memory body 10 is continued while the capacitor Csb is charged.

  FIG. 10 shows the states of the switches SW1a to SW3a and SW1b to SW3b and the current flow when measuring the capacitance of the capacitor Csb. The switches SW1b and SW2b are turned off, the switch SW3b is turned on, the current from the capacitor Csb is passed through the measurement load 21, and the voltage of the capacitor Csb, that is, the voltage measurement result signal Vz is equal to or lower than the predetermined reference voltage Vb. The time Tb is measured. During this time, the output of the DC voltage to the memory body 10 is continued while the capacitor Csa is charged.

  The operation of the disk device 1 according to the third embodiment will be described in more detail with reference to the time chart of FIG. First, after the power is turned on, the capacitors Csa and Csb are charged in the normal state of FIG. 8 (timing T1). When the charging is completed, the capacitance measurement of the capacitor Csa is performed in the state at the time of measuring the capacitance of the capacitor Csa in FIG. Perform (timing T5).

  At this time, the limited operation B is started in which only the amount of data that can write the write-back cache data on the volatile memory 15 to the nonvolatile memory 14 with only the capacity of the capacitor Csb is written.

  When the capacitance measurement of the capacitor Csa is completed, the normal state of FIG. 8 is restored and the capacitor Csa is charged again (timing T6). When the charging is completed, the state of the capacitor Csb of FIG. The capacity is measured (timing T7).

  At this time, the limited operation B in which only the amount of data that can write the write-back cache data on the volatile memory 15 to the nonvolatile memory 14 with only the capacity of the capacitor Csa is written to the volatile memory 15 is continued.

  When the capacitance measurement of the capacitor Csb is completed, the normal state of FIG. 8 is restored (timing T8), the capacitor Csb is charged again, and when the charging is completed, normal operation is started (timing T9). Start write-back caching of data to Thereby, the limited operation B started at the timing T5 is completed.

  When the DC input Vcc is cut off during normal operation, the power stored in the capacitors Csa and Csb is used to write the write-back cache data of the volatile memory 15 to the nonvolatile memory 14 and the process ends ( Timing T3-T4).

(Effect of Example 3)
As described above, according to the disk device of the third embodiment, the power input section includes two capacitors, and the DC input is connected to the capacitors via the respective diodes and switches. A DC output that is a logical OR of the power of the diode is supplied to the memory body, and each capacitor is connected to a shared measurement load via each switch, while the capacitance of one capacitor is measured. Since the limited operation B, in which only the amount of data that can be written back according to the capacity of the other capacitor is written via the volatile memory, can be performed, the write-back cache operation can be performed during the capacity measurement of any capacitor. And shorten the time until the nonvolatile memory can be accessed without reducing the writing speed. It is possible.

(Constitution)
Since the configuration of the disk device of the fourth embodiment is the same as that of the third embodiment, detailed description thereof is omitted for the sake of brevity.

(Operation)
The operation of the disk device 1 according to the fourth embodiment will be described in detail below with reference to the time chart of FIG. Since the operation from the timing T1 to T9 from the start to the normal operation described with reference to FIG. 11 is the same as the operation of the disk device of the third embodiment, detailed description thereof is omitted for simplification.

  In the disk device 1 according to the fourth embodiment, the switches SW1a to SW3a are switched as shown in the figure every time a predetermined time, for example, 24 hours elapses after the capacitance measurement of the capacitors Csa and Csb is performed immediately after starting. The capacity measurement of Csa is started (timing T11). At this time, the normal operation is switched to the limited operation B described above.

  Then, when the capacitance measurement of the capacitor Csa is completed, the switches SW1a to SW3a are switched as shown in the figure, and charging of the capacitor Csa is started again (timing T12). When the charging is completed, the switches SW1b to SW3b are switched as shown in the figure, and the Csb capacity measurement is started (timing T13). Then, when the capacitance measurement of the capacitor Csb is completed, the switches SW1b to SW3b are switched as shown in the figure, and the capacitor Csb is charged again.

  When the charging of the capacitor Csb is completed, the limited operation B is returned to the normal operation (timing T14). By repeating the above operation every predetermined time, even a disk device that does not stop for a long period of time can periodically measure the capacities of the capacitors Csa and Csb and check the lifetime of the capacitors Csa and Csb. .

(Effect of Example 4)
As described above, according to the disk device of the fourth embodiment, the capacitance of the capacitor can be measured every time a predetermined time elapses after the capacitance of the capacitor is measured immediately after startup. Thus, even in a disk device that does not stop for a long time, the capacity of the capacitor can be accurately estimated, and the life of the capacitor can be reliably determined.

(Constitution)
Since the configuration of the disk device according to the fifth embodiment is the same as the configuration of the disk device according to the first or third embodiment, detailed description thereof is omitted for the sake of brevity. In the following description of the disk device of the fifth embodiment, the case of the configuration of the disk device 1 of the first embodiment shown in FIG. 1 will be described as an example.

(Operation)
The operation of the disk apparatus of the fifth embodiment having the above configuration will be described with reference to the time chart of FIG.

  In the figure, the time chart of the voltage of the capacitor Cs when the capacitor Cs is normal is indicated by a solid line, and the time chart of the voltage of the capacitor Cs when it is deteriorated due to the lifetime or the like is indicated by a broken line. As described above, the voltage drops at a slope proportional to the decrease in the capacity both during the capacity measurement (timing T21 to T24) and when the power is shut off (timing T25 to T25).

  In the disk device 1 according to the fifth embodiment, by using this characteristic, the time Ta that drops to a predetermined reference voltage Va when measuring the capacitance of the capacitor is measured, so that the voltage drops to the memory body operable voltage Vw when the power is turned off. The time, ie, the time Tw at which the write-back cache data can be written is estimated, and the write-back cache data amount that can be written at the time of power-off is calculated based on the time Ta that is the measurement result at the time of capacity measurement. ) To limit the amount of write-back cache data.

  For example, when the amount of write-back cache data that can be written when the time Ta is about 3 seconds is 300 KB, the amount of write-back cache data that can be written is about 200 KB when the time Ta is about 2 seconds.

  When there are two or more capacitors Cs, the times Ta and Tb that fall to the predetermined reference voltages Va and Vb are obtained at the time of each capacitance measurement, and a write that can be written when the power is shut off based on the total time The back cache data amount may be calculated to limit the write back cache data amount in the normal operation (2).

(Effect of Example 5)
As described above, according to the disk device of the fifth embodiment, the measurement load is connected at the time of starting or every elapse of a predetermined time after the activation, and the discharge time to drop to the predetermined reference voltage is obtained. Since the amount of write-back cache data in the operation is limited, the operation according to the capacity of the capacitor can be continued even when the capacitor is deteriorated.

<< Other modifications >>
In the above description of the embodiment, the semiconductor disk device has been described as an example. However, the present invention can also be applied to a RAID device or a disk drive device equipped with a write-back cache memory.

  In the disk devices of the third and fourth embodiments, the description has been given of the example using two capacitors. However, as in the third and fourth embodiments, a switch and a shared measurement load are connected to each capacitor. If so, three or more capacitors may be provided.

  As described above, the present invention can be widely used for disk devices such as a semiconductor disk device including a power backup capacitor.

DESCRIPTION OF SYMBOLS 1 Disk apparatus 10 Memory main-body part 11 I / F part 12 Control part 14 Volatile memory 15 Non-volatile memory 20 Power supply input part 21 Measuring load 21a Load circuit 21b Voltage measuring circuit D1-D3, D1a-D3a, D1b-D3b Diode Va Reference voltage Vw Memory main body operable voltage Vcc DC input Vdd DC output Vz Voltage measurement result signals SW1 to SW3, SW1a to SW3a, SW1b to SW3b Switches Cs, Csa, Csb Capacitors

Claims (6)

A disk device comprising a capacitor capable of supplying power when the power is shut off, storing data in the nonvolatile memory via a volatile memory, and storing data stored in the volatile memory in the nonvolatile memory when the power is shut off. And
Load means to be a load of the capacitor;
A first switch and a second switch provided on a power input side and a power output side to the capacitor, respectively, and a first switch and a second switch provided between the capacitor and the load means. And a switch means comprising a third switch that is turned on and off,
A disk characterized in that, at a predetermined time, the third switch is turned on to measure a discharge time until the capacitor falls below a predetermined voltage, and the capacity of the capacitor can be estimated based on the discharge time. apparatus. A first diode provided between an input power supply and the first switch;
A second diode provided between an output power supply and the second switch;
2. The disk device according to claim 1, further comprising a rectifying unit comprising a third diode provided between the input power source and the output power source.   2. The disk device according to claim 1, wherein the write data is immediately stored in the nonvolatile memory from the start of measurement at the predetermined time until the capacitor is charged.   2. The disk apparatus according to claim 1, wherein the predetermined time is set every time a predetermined time elapses from the time of starting or the previous capacity measurement. Equipped with multiple capacitors that can supply power when the power is shut off,
2. The disk device according to claim 1, wherein the load unit, the switch unit, and the switch unit are provided for each capacitor.   2. The amount of data stored in the non-volatile memory via the volatile memory is limited based on the discharge time until the capacitor becomes a predetermined voltage or less. Disk unit.

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