JP2011203967A - Electronic control apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of further suppressing unnecessary power consumption, in an electronic control apparatus having a plurality of microcomputers.SOLUTION: Only when filter circuits of respective control microcomputers 20, 30 detect signal values of dominant levels consecutively twice at mutually different sampling periods, a wake-up signal is regarded to be inputted, and the control microcomputers 20, 30 are returned to normal modes from sleep modes. Thereby, even if one filter circuit detects a signal value of the dominant level "1" consecutively twice regarding intermittently produced noise, when the other filter circuit can detect a signal value of an inferior level "0", operation modes of the control microcomputers 20, 30 are not required to be unnecessarily returned to the normal modes.

Description

  The present invention relates to an electronic control device including a plurality of microcomputers.

  Conventionally, a vehicle is equipped with a large number of electronic control devices (so-called ECUs) for controlling in-vehicle devices, and these ECUs share control data or perform integrated control of the vehicle. They are connected to each other via a communication bus so that data communication is possible.

  In addition, the number of ECUs mounted on vehicles is increasing for higher functionality and safety improvement of in-vehicle devices, and the number of ECUs connected to the communication bus is also increasing. When the number of ECUs connected increases, the communication wiring route becomes longer, so that the route design for ensuring communication quality becomes complicated, and it becomes difficult to ensure communication quality.

For this reason, in recent years, in order to reduce the number of ECUs mounted on a vehicle, it has been considered to consolidate functions conventionally realized by a plurality of ECUs into one electronic control unit.
However, when integrating various functions in one ECU, designing a new microcomputer (microcomputer) that can realize all of the functions not only costs design (specifically software development) but also a microcomputer. Therefore, the microcomputer must be configured to be capable of processing at a higher speed than the conventional one. Furthermore, since the power consumption of the microcomputer increases as the processing load increases, new measures such as heat dissipation measures are also required.

  For this reason, when integrating functions that have been realized by a plurality of ECUs in the past into one ECU, instead of newly designing a multi-function microcomputer, a plurality of microcomputers incorporated in each ECU in the past, It is good to incorporate in one ECU.

  By the way, this type of ECU is provided with a large number of interfaces for inputting various signals (binary signals) such as state signals from sensors and switches indicating the state of the vehicle and control signals from other ECUs. The microcomputer executes various processes based on the state of the binary signal fetched through these interfaces.

  For example, when the engine is operating, the microcomputer executes various processes in the normal mode that is the normal startup state, and when the ignition key is at the accessory position in the engine stopped state, The mode is shifted to a power saving mode with low power consumption. This suppresses exhaustion of battery power when the engine is stopped.

  Specifically, the microcomputer is configured to return from the power saving mode to the normal mode when a wakeup signal (dominant level signal value) is input via the interface in the power saving mode. Further, in order to prevent erroneous detection of the wake-up signal, the signal value is detected every sampling period set to be shorter than half the pulse width of the signal, and the signal value is continuously dominant twice. There is known a technique for determining that an input signal is a wake-up signal (hereinafter referred to as a wake-up technique) (see, for example, Patent Document 1).

  In other words, by applying this wake-up technology to the ECU, it is possible to treat a signal with a pulse width smaller than that of the wake-up signal as noise, and the operating mode of the microcomputer is returned to the normal mode unnecessarily due to the noise. Can be suppressed.

JP 2006-215706 A

  However, this wake-up technology, for example, treats the noise as a wake-up signal when the noise generation timing overlaps the signal value detection timing twice in succession. May be unnecessarily restored to the normal mode.

  Especially when applied to an ECU having a plurality of microcomputers, if the microcomputer operation mode is returned to the normal mode unnecessarily, more power is wasted depending on the number of microcomputers. Therefore, it is required to minimize such possibility as much as possible.

  In order to solve the above problems, an object of the present invention is to provide a technique capable of further suppressing unnecessary power consumption in an electronic control device including a plurality of microcomputers.

  The electronic control device according to claim 1, which is an invention made to achieve the above object, is connected to an interface for taking in a binary signal inputted from the outside via a signal line, and is communicably connected to each other, And a plurality of microcomputers that execute processing based on a signal value representing a state of a binary signal fetched from the interface as a dominant level or an inferior level.

  Among these, in each microcomputer, the mode switching means switches between a normal mode that is a preset activation state and a power saving mode that consumes less power than the normal mode. And among the above binary signals, the signal indicating the prevailing level only during the interruption period in which the signal value is set in advance is used as a wake-up signal, and the wake-up means is configured while the microcomputer operation mode is the power saving mode. When the wake-up signal is input via the signal line, the operation mode is set to the normal mode via the mode switching means.

  Further, in each microcomputer, the filter unit detects a signal value at every sampling period set to be shorter than at least half the length of the above-described interrupt period, and the detected signal value continuously reaches the dominant level twice. When shown, it passes a binary signal taken from the interface. Then, the first condition is that the wake-up determination means detects the binary signal that has passed through the filter unit, and an internal notification indicating that the first condition is satisfied is sent to all other microcomputers in the electronic control unit. Only when the first condition and the preset second condition are satisfied, the binary signal is determined to be a wake-up signal.

  Here, the sampling period is set to a different period for each microcomputer, and the second condition is that the wakeup determination means inputs the above internal notification from all the other microcomputers in the electronic control unit. Configure.

  In other words, in the electronic control device of the present invention, the wakeup signal is input from the signal line only when all the filter units detect the signal level of the dominant level twice continuously at different sampling periods. Therefore, each microcomputer is returned from the power saving mode to the normal mode (wake-up).

  As a result, in the electronic control device of the present invention, the possibility (risk) that one filter unit erroneously handles noise as a wake-up signal can be dispersed by using a plurality of filter units, and as a result, Therefore, the possibility that the operation mode of the microcomputer is returned to the normal mode unnecessarily can be reduced.

Therefore, according to the electronic control device of the present invention, unnecessary power consumption can be further suppressed in a configuration including a plurality of microcomputers.
Specifically, as described in claim 2, in the electronic control device of the present invention, each microcomputer includes a control unit having a CPU that performs processing for controlling a preset control target device, and a mode. The switching unit may switch the operation mode from the normal mode to the power saving mode by stopping the clock supplied to the control unit or reducing the clock speed.

  According to the electronic control device configured as described above, in the power saving mode, for example, by reducing the speed of the clock supplied to the control unit, the processing speed of the CPU is reduced, so that the power consumption of the microcomputer is surely reduced. Can be made.

  According to a third aspect of the present invention, the signal line is a communication bus that is communicably connected to another electronic control unit, and the control unit is connected to the other electronic device via the communication bus (and interface). In a configuration having a communication controller for performing data communication with a control device according to a predetermined protocol, the mode switching means stops the clock supplied to the communication controller when the operation mode is switched from the normal mode to the power saving mode. You may make it make it.

According to the electronic control device configured as described above, since the processing of the communication controller is stopped in the power saving mode, the power consumption of the microcomputer can be further reduced.
Similarly, as described in claim 4, the mode switching means may stop the clock supplied to the CPU when the operation mode is switched from the normal mode to the power saving mode. That is, since the CPU processing is stopped in the power saving mode, the power consumption of the microcomputer can be further reduced.

  Conversely, as described in claim 5, the mode switching means may stop the clock supplied to the filter unit when the operation mode is switched from the power saving mode to the normal mode. In this case, by stopping the processing of the filter unit, unnecessary power consumption can be suppressed even in the normal mode.

It is a block diagram which shows the structure of the vehicle-mounted network which is embodiment to which this invention was applied. It is a state transition diagram which shows the operation mode of a control microcomputer. It is a block diagram which shows the structure of a control microcomputer. It is a matrix diagram for explaining the operation of the clock control circuit. It is a timing diagram for demonstrating operation | movement of a filter circuit and an edge detector. It is a flowchart which shows the detail of the wakeup determination process which CPU performs. It is a timing diagram for demonstrating operation | movement of one filter circuit. It is a timing diagram for explaining operation of a plurality of filter circuits.

Embodiments of the present invention will be described below with reference to the drawings.
[overall structure]
FIG. 1 is a block diagram showing a configuration of an in-vehicle network 10 that is an embodiment to which the present invention is applied.

  As shown in FIG. 1, the in-vehicle network 10 is constructed in order to exchange control data between various electronic control units (ECUs) mounted on the vehicle, and information such as navigation devices and audio devices is provided. Control system ECU 1 for controlling system control target equipment, body system ECU 2 for controlling body system control target equipment such as power window device and lighting device, and control system for drive system control such as engine and automatic transmission The drive system ECU 3 is configured to be connected via the communication bus 4.

  An actual vehicle is equipped with a large number of ECUs corresponding to the number of devices to be controlled. However, details are omitted because they are not the main points, and are described using the above three roughly classified ECUs 1-3. To do. Similarly, in the actual in-vehicle network 10, control data is exchanged using a plurality of communication protocols corresponding to communication speeds, etc., but description of communication protocol conversion by a relay device or the like is omitted below. To do.

  When the drive system ECU 3 receives control data representing a target speed or the like from the inter-vehicle control ECU (not shown) that controls the inter-vehicle distance and the speed of the host vehicle, for example, via the communication bus 4, the received data The engine, the brake, and the automatic transmission are controlled so that the driving state specified by Further, for example, when the driver turns the ignition key to the start position and detects that the engine switch 5 is turned on, the engine is started and a signal indicating that the engine switch 5 is turned on (hereinafter referred to as a START signal). Is transmitted to the information system ECU 1 via the communication bus 4.

  When the body system ECU 2 receives, via the communication bus 4, for example, control data representing the vehicle running state (vehicle speed, yaw rate, etc.) from the drive system ECU 3 and control data representing the vehicle traveling environment from the information system ECU 1, The optical axis and the amount of light of the headlight are adjusted so as to be in an irradiation state specified from the received data (an irradiation state easy for the driver to visually recognize). For example, when the driver turns the ignition key to the accessory position and detects that the accessory switch 6 is turned on, the driver controls the power window device and various lighting devices to be operable.

  Note that the accessory switch 6 of this embodiment is also connected to the information system ECU 1, and when the switch 6 is turned on, a signal indicating this (hereinafter referred to as an ACC signal) is output to the information system ECU 1. It is configured.

  When the information system ECU 1 receives, for example, control data representing the running state (vehicle speed, yaw rate, etc.) of the vehicle from the drive system ECU 3 via the communication bus 4, the information such as the moving distance and the moving direction of the vehicle is used. Is calculated, and control data representing a traveling environment based on the current position of the vehicle, map data, and the like is transmitted to the body system ECU 2 via the communication bus 4.

  In the following description, it is normal to set a startup state that is set in advance so that these ECUs 1 to 3 can transmit and receive control data to and from each other via the communication bus 4 and perform processing for controlling the control target device. We will call it a mode.

[Detailed configuration of information system ECU]
Specifically, the information system ECU 1 includes a microcomputer (main control microcomputer) 20 as a main control circuit as a control circuit that performs control for realizing a navigation (NAVI) function and an audio visual (AV) function. A microcomputer (sub-control microcomputer) 30 as a sub-control circuit that operates in accordance with instructions from the main control microcomputer 20 is provided, and the control microcomputers 20 and 30 are connected to the internal buses 11 and 12, respectively.

  In addition, the information system ECU 1 is used to input to the control microcomputers 20 and 30 detection signals and reception signals from various sensors and switches included in the control target device (navigation device, audio device) and external devices. Input circuits 13 and 14 and output circuits 15 and 16 for outputting various data (images, sounds, etc.) output from the control microcomputers 20 and 30 to a display and a speaker included in the control target device are provided. Yes.

  For example, in the normal mode, the main control microcomputer 20 is stored in advance in a GPS receiver, a gyroscope, a detection signal from a geomagnetic sensor, an external storage device (not shown) or the like input via the input circuit 13. Based on the map data, a process for calculating the optimum route from the current position of the vehicle to the destination (route calculation process) is performed, and the sub-control microcomputer 30 performs route guidance based on the route calculation of the main control microcomputer 20. Configured to do.

  In the present embodiment, in the power saving mode in which the power consumption is smaller than that in the normal mode, the main control microcomputer 20 controls the map data and control based on the received signal from the wireless communication device input via the input circuit 13. A process of updating the program (information update process) is performed, while the sub-control microcomputer 30 is configured to stop all processes.

  Hereinafter, in the power saving mode, a state in which some processing is performed as in the main control microcomputer 20 is referred to as a sleep mode, and a state in which all processing is stopped as in the sub control microcomputer 30 is referred to as a stop mode. Similarly, the clock supplied to each of the control microcomputers 20 and 30 is stopped, or the ignition key is rotated to the lock position by the driver (ie, the ignition switch is turned off), and the battery (not shown). A state in which the supply of power from is stopped is also referred to as a stop mode.

  Although details will be described later, for example, the operation mode of the main control microcomputer 20 shifts to the sleep mode when an ACC signal is input from the accessory switch 6 via the input circuit 13 in the stop mode or the normal mode as shown in FIG. To do. Further, when a START signal is input from the drive system ECU 3 via the communication bus 4 in the sleep mode, a transition is made to the normal mode when a determination condition by a wake-up determination process described later is satisfied. Note that when the ignition switch is turned off (the IG-OFF signal is input) in the normal mode or the sleep mode, a transition is made to the stop mode.

  Returning to FIG. 1, the information system ECU 1 has a receiver as an interface for taking in signals (binary signals) input from other ECUs 2 and 3 via the communication bus 4, and other ECUs 2 and 2 via the communication bus 4. 3 is provided with a transceiver 17 including a driver as an interface for transmitting control data, and the control microcomputers 20 and 30 are connected to the transceiver 17.

[Configuration of control microcomputer]
Next, FIG. 3 is a block diagram showing the configuration of the control microcomputers 20 and 30. Since the control microcomputers 20 and 30 have substantially the same configuration, the main control microcomputer 20 will be described below as a representative, and the sub control microcomputer 30 will be additionally described.

  As shown in FIG. 3, the main control microcomputer 20 includes a CPU 21 that performs various processes such as a route calculation process and an information update process, a ROM 22 that stores various control programs necessary for the process of the CPU 21, and a process performed by the CPU 21. Via the RAM 23 used as a work area when performing the operation, an interface (I / O) 24 for receiving various signals from the input circuit 13 and outputting various data to the output circuit 15, and the internal buses 11 and 12. A predetermined protocol (e.g., between the input port 25a and the output port 25b for inputting / outputting control data and internal notification described later with the sub-control microcomputer 30 and the ECUs 2 and 3 via the communication bus 4). And a communication controller 26 for performing data communication according to the CAN protocol.

  The communication controller 26 arbitrates the communication bus 4 based on the signal value representing the state of the binary signal fetched from the transceiver 17 as the dominant level or the inferior level, and transmits the transmission signal flowing through the communication bus 4 to the CPU 21. And a process for transmitting a signal based on control data generated by the CPU 21 to the other ECUs 2 and 3 via the communication bus 4.

  Further, the main control microcomputer 20 detects the above signal value based on a filter clock different from that of the sub control microcomputer 30, and takes in from the transceiver 17 when the detected signal value indicates the predominance level twice. A filter circuit 27 that passes the signal, an edge detector 28 that detects an edge of the signal that has passed through the filter circuit 27, an interrupt controller 29 that outputs various interrupt requests to the CPU 21, and the CPU 21 and the units 26 to 29. And a clock circuit 40 for supplying each clock necessary for each operation.

  Among these, the clock circuit 40 generates a plurality of types of clocks used by the CPU 21 and the units 26 to 29 by multiplying or / and dividing the frequency of an original clock supplied from an oscillator (not shown). 41 and a clock control circuit 42 that controls the clock generated by the clock generation circuit 41 in accordance with the operation mode of the main control microcomputer 20 and supplies various clocks to the CPU 21 and the units 26 to 29.

  As shown in FIG. 4, the clock control circuit 42 stops the clock supplied to the CPU 21 and each of the units 26 to 29 in the stop mode, and receives a signal (ACC signal or edge detection signal) from the I / O 24 or the edge detector 28. Then, in order to switch from the stop mode to the sleep mode, supply of clocks to the units 27 to 29 other than the communication controller 26 and the CPU 21 is started. In the sleep mode, various low-speed clocks are selected as compared with the normal mode.

  The clock control circuit 42 stops the clock supplied to the filter circuit 27 and the edge detector 28 in the normal mode, and supplies various high-speed clocks to the CPU 21 and the controllers 26 and 29. When an ACC signal is input via the I / O 24, various clocks that are slower than those in the normal mode are selected as clocks to be supplied to the CPU 21 and the interrupt controller 29 in order to switch from the normal mode to the sleep mode. Then, the clock supplied to the communication controller 26 is stopped, and the supply of the clock to the filter circuit 27 and the edge detector 28 is started.

  When the IG-OFF signal is input via the I / O 24 in the sleep mode or the normal mode, the clock control circuit 42 stops the clock supplied to the CPU 21 and each unit 26 to 29 (that is, the stop mode is set). Migrate).

  Furthermore, when a wake-up command (to be described later) is input from the CPU 21 in the sleep mode, the clock control circuit 42 starts supplying a clock to the communication controller 26 and switches the CPU 21 and the interrupt controller to switch from the sleep mode to the normal mode. As clocks to be supplied to 29, various clocks that are faster than those in the sleep mode are selected, and the clocks to be supplied to the filter circuit 27 and the edge detector 28 are stopped.

  The filter circuit 27 detects the signal value of the input terminal (INT terminal) from the transceiver 17 at the falling edge of the clock (filter clock) supplied from the clock control circuit 42, as shown in FIG. When the measured signal value indicates the dominant level twice in succession, it is treated as if a START signal (hereinafter referred to as a wake-up signal) is input via the transceiver 17, and the input signal from the transceiver 17 is passed.

  In the present embodiment, the period (pulse width) indicating the dominant level in the wake-up signal is set longer than any pulse width in signals based on other control data. The interval between the falling edges of the filter clock (hereinafter referred to as sampling cycle) is set to be shorter than at least half the pulse width of the wakeup signal, and is set to a different cycle for each of the control microcomputers 20 and 30. Has been.

  When the edge detector 28 detects a signal that has passed through the filter circuit 27 at the falling edge of the clock (peripheral clock) supplied from the clock control circuit 42, the edge detector 28 outputs an edge detection signal to the interrupt controller 29 and the clock control circuit 42. Is configured to do.

  Returning to FIG. 3, when the edge detection signal is input from the edge detector 28, the interrupt controller 29 is configured to output an interrupt request signal for starting a wakeup determination process described later to the CPU 21. ing.

[Wake-up judgment processing]
Here, the wake-up determination process executed by the CPU 21 will be described in detail along the flowchart shown in FIG. This process is started when an interrupt request signal is input from the interrupt controller 29.

  First, when this processing is started, in S110, an internal notification signal indicating that the binary signal that has passed through the filter circuit 27 is detected by the edge detector 28 is sent to the CPU of the sub-control microcomputer 30 via the internal bus 11. Output to. In the present embodiment, an internal notification signal is output by applying a voltage at the dominant level to the output port 25b.

  In subsequent S <b> 120, it is determined whether or not an internal notification signal is input from the CPU of the sub-control microcomputer 30 via the internal bus 11. That is, since the sub-control microcomputer 30 has substantially the same configuration as the main control microcomputer 20 (however, the sampling period is different), the binary signal that has passed through the filter circuit is detected by the edge detector. This is because the internal notification signal is output to the CPU 21 of the main control microcomputer 20. In the present embodiment, when the input port 25a indicates the dominant level, the internal notification signal is treated as input, and the process proceeds to S130, and when the input port 25a indicates the inferior level, the internal notification signal is not input. The process proceeds to S140.

  In S130, it is determined that the input signal from the transceiver 17 is a wake-up signal, and a wake-up command is output to the clock control circuit 42, thereby returning the operation mode of the main control microcomputer 20 from the sleep mode to the normal mode. This process is terminated. At this time, since the CPU of the sub-control microcomputer 30 performs the same process as this process, an internal notification signal is input from the main control microcomputer 20 side, and the operation mode of the sub-control microcomputer 30 is changed from the sleep mode to the normal mode. Will return to.

  On the other hand, in S140, it is determined that the input signal from the transceiver 17 (INT terminal) is noise, the sleep mode is continued, and this process is terminated. That is, as shown in FIG. 7, the input signal from the INT terminal is regarded as noise that overlaps twice with the edge falling timing in the filter clock on the main control microcomputer 20 side.

[Effect of this embodiment]
As described above, in the information system ECU 1 according to the present embodiment, communication is performed only when the filter circuits of the control microcomputers 20 and 30 detect the dominant level signal value twice consecutively at different sampling periods. Assuming that a wake-up signal is input from the bus 4 via the transceiver 17, the control microcomputers 20 and 30 are returned from the sleep mode to the normal mode.

  As a result, as shown in FIG. 8, for example, one filter circuit of the control microcomputers 20 and 30 detects the signal value of the dominant level “1” twice in succession with respect to intermittently generated noise. Even in this case, if the other filter circuit having a different sampling period can detect the signal value of the inferior level “0”, it is not necessary to unnecessarily return the operation mode of the control microcomputers 20 and 30 to the normal mode. .

  That is, in the information system ECU 1, the possibility (risk) that the noise is erroneously handled as a wake-up signal in one filter circuit can be dispersed by the plurality of filter circuits. As a result, the control microcomputers 20 and 30 The possibility that the operation mode is returned to the normal mode unnecessarily can be reduced.

Therefore, according to the information system ECU 1 of the present embodiment, unnecessary power consumption can be suppressed in the configuration including the plurality of control microcomputers 20 and 30.
In the information system ECU 1, when the edge detector 28 detects a signal that has passed through the filter circuit 27, the edge detection signal is also output to the clock control circuit 42, and the clock control circuit 42 to which the edge detection signal is input is stopped. In order to switch from the mode to the sleep mode, supply of clocks to the units 27 to 29 other than the communication controller 26 and the CPU 21 is started.

  For this reason, according to the information system ECU 1, during the power saving mode, for example, the clock supplied to the CPU of the sub-control microcomputer 30 can be set to a stopped state (stop mode), thereby further reducing power consumption. Can be made.

  Furthermore, since the information ECU 1 stops the clock supplied to the filter circuit 27 and the edge detector 28 in the normal mode, it is possible to prevent unnecessary power consumption even in the normal mode.

[Correspondence between this embodiment and claims]
In the above embodiment, the information system ECU 1 is an electronic control device, the body system ECU 2 and the drive system ECU 3 are other electronic control devices, the transceiver 17 is an interface, the main control microcomputer 20 and the sub control microcomputer 30 are each microcomputer, clock. The control circuit 42 corresponds to mode switching means, the CPU 21 corresponds to wakeup means, the filter circuit 27 corresponds to a filter unit, and the wakeup determination processing corresponds to wakeup determination means.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  For example, the main control microcomputer 20 of the above embodiment is configured to input a wake-up signal from the communication bus 4 to the filter circuit 27 via the transceiver 17, but the present invention is not limited to this. A wakeup signal may be directly input to the filter circuit 27 from an external device (for example, the engine switch 5) via the O24.

  In the information system ECU 1 of the above embodiment, the operation mode is switched from the normal mode to the sleep mode by stopping the clock supplied to the control microcomputers 20 and 30 (or reducing the clock speed). However, the present invention is not limited to this. For example, the power supply from the battery may be stopped for a specific part such as the communication controller 26.

In the information system ECU 1 of the above embodiment, the configuration including the two control microcomputers 20 and 30 has been described as an example, but the number of these microcomputers may be three or more.
In the above-described embodiment, the information system ECU 1 is described as an example of the electronic control device of the present invention. However, the present invention is not limited to this, and may be applied to other ECUs 2 and 3. For example, the configuration including a plurality of microcomputers can be applied to various ECUs without being limited to those mounted on a vehicle.

  DESCRIPTION OF SYMBOLS 1 ... Information system ECU, 2 ... Body system ECU, 3 ... Drive system ECU, 4 ... Communication bus, 5 ... Engine switch, 6 ... Accessory switch, 10 ... In-vehicle network, 11, 12 ... Internal bus, 17 ... Transceiver, 20 ... Main control microcomputer, 21 ... CPU, 24 ... I / O, 26 ... Communication controller, 27 ... Filter circuit, 28 ... Edge detector, 29 ... Interrupt controller, 30 ... Sub control microcomputer, 40 ... Clock circuit, 41 ... Clock Generation circuit, 42... Clock control circuit.

Claims (5)

An interface for capturing a binary signal input from the outside via a signal line;
A plurality of microcomputers that are communicably connected to each other and that execute processing based on a signal value representing a state of a binary signal taken from the interface as a dominant level or an inferior level;
An electronic control device comprising:
Each microcomputer is
Mode switching means for switching the operation mode of the microcomputer to either a normal mode which is a preset startup state or a power saving mode in which power consumption is lower than the normal mode;
Of the binary signals, the signal value indicating the prevailing level only during an interrupt period set in advance is used as a wake-up signal, and the wake-up signal is displayed while the operation mode of the microcomputer is the power saving mode. Wakeup means for setting the operation mode to the normal mode via the mode switching means when input via the signal line;
When the signal value is detected at every sampling period set to be shorter than at least half the length of the interrupt period, and the detected signal value indicates the dominant level twice in succession, 2 captured from the interface A filter section for passing a value signal;
Detecting a binary signal that has passed through the filter unit as a first condition, an internal notification indicating that the first condition is satisfied is output to all other microcomputers in the electronic control unit, and the first Wakeup determination means for determining that the binary signal is the wakeup signal only when one condition and a preset second condition are satisfied;
With
The sampling period is set to a different period for each microcomputer,
The electronic control apparatus according to claim 1, wherein the wakeup determination unit treats input of the internal notification from all the other microcomputers as the second condition. Each of the microcomputers includes a control unit having a CPU that performs processing for controlling a preset control target device,
The mode switching means switches the operation mode from the normal mode to the power saving mode by stopping a clock supplied to the control unit or reducing a speed of the clock. Item 2. The electronic control device according to Item 1. The signal line is a communication bus that is communicably connected to another electronic control unit,
The control unit includes a communication controller for performing data communication according to a predetermined protocol with the other electronic control device via the communication bus,
The electronic control device according to claim 2, wherein the mode switching unit stops a clock supplied to the communication controller when the operation mode is switched from the normal mode to the power saving mode.   4. The electronic control device according to claim 2, wherein the mode switching unit stops a clock supplied to the CPU when the operation mode is switched from the normal mode to the power saving mode. 5. .   The said mode switching means stops the clock supplied to the said filter part, when switching the said operation mode from the said power saving mode to the said normal mode, The any one of Claim 1 thru | or 4 characterized by the above-mentioned. The electronic control device according to 1.

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