JP2011199559A - Dual rate receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately switch a normal mode and a test mode.SOLUTION: A dual rate receiving circuit includes: a squelch circuit 120 for providing a squelch state by shutting off an output of a 10 Gbps amplifier 110; a squelch circuit 140 for providing a squelch state by shutting off an output of a 1 Gbps amplifier 130; an LOS detection circuit 200 for outputting a LOS signal 210 indicating whether or not an amplitude of a received signal is smaller than or equal to a reference amplitude; and gate circuits 400, 600, 610, 620, 630, 640 for generating squelch control signals 800, 810 in accordance with the LOS signal 210 and a rate select signal 500 indicating a current rate of the received signal during a normal mode, and generating the squelch control signals 800, 810 in which at least either squelch control according to the LOS signal 210 or squelch control according to the rate select signal 500 is invalidated during a test mode.

Description

  The present invention relates to a dual rate receiving circuit used in a receiver or the like of an optical communication system, and more particularly to squelch control of a dual rate receiving circuit.

  A PON (Passive Optical Network) optical communication system is composed of a station side terminal device (Optical Line Terminal: OLT), a plurality of subscriber side devices (Optical Network Unit: ONU), and a passive optical splitter. And a plurality of ONUs by an optical splitter to exchange data. In such an optical communication system, a light receiving element that receives an optical signal and converts it into a current signal, a TIA (Trans-Impedance Amplifier) that converts a current signal output from the light receiving element into a voltage signal, and a TIA output. An amplitude limiting amplifier circuit (Limiting Amplifier: LA) which is a post-amplifier that amplifies the voltage signal to a certain amplitude is used. The signal amplified to a constant amplitude by LA is sent to CDR (Clock Data Recovery). The CDR performs extraction of a clock signal, retiming of a data signal, parallel development of the data signal, and the like, and sends an output signal to the digital signal processing LSI.

  Currently, the data rate of 1.25 Gbps is commercialized in the PON system, but in order to cope with the future increase in capacity, the development of a 10.3125 Gbps system called 10G-EPON is underway. However, even if the 10G-EPON service is put into practical use, not all users need a speed of 10.3125 Gbps, but 1.25 Gbps (hereinafter abbreviated as 1 Gbps) and 10.3125 Gbps (hereinafter abbreviated as 10 Gbps). Is likely to be mixed. In this case, one OLT is connected to a plurality of ONUs having different data rates, and the OLT must receive signals having different rates. In such an OLT, the LA has an output port for each rate and is connected to the corresponding CDR.

  Since the CDR has a PLL (Phase-Locked Loop) circuit for extracting a clock from the input data, when a signal other than the target rate is input, it is synchronized to match the frequency of the signal once. As a result, there is a problem that it takes time to synchronize when a signal of a target rate is input next. Further, when noise is output from LA in the no-signal section, the same problem occurs because a signal other than the target rate is the same as that input to the CDR. In order to prevent such a problem, the LA has a built-in squelch circuit that blocks the output signal or fixes the output signal at a constant voltage level.

  In general, in an optical receiving system, in order to prevent the above-described noise from the LA when there is no signal, the output of an LOS (Loss of Signal) circuit that detects the amplitude of the input signal is used to control the LA squelch circuit. The LOS output is enabled when the received signal is lower than the reference level, such as when there is a signal loss between bursts or due to a communication path failure. The squelch circuit function is turned on and the LA output is kept constant. Fix to level.

  An example of such LA is disclosed in Non-Patent Document 1. A generalized connection based on the diagram disclosed in Non-Patent Document 1 is shown in FIG. The LA 700 includes an input buffer 101 that receives a signal output from a preceding circuit (not shown), an amplifier 110 that amplifies the signal output from the input buffer 101, and outputs the output of the amplifier 110 as it is or at a certain level. A squelch circuit 120 that controls whether the output is fixed, an output buffer 150 that outputs a signal output from the squelch circuit 120 to an output terminal 170, and an LOS detection circuit 200 that receives an output signal of the input buffer 101 as an input. I have. The AND gate 400 outputs a control signal 410 that is the logical product of the LOS output signal 210 from the LOS detection circuit 200 and the control signal 310 for enabling or disabling the LOS output signal, and turns on the squelch circuit 120. / Turn off. When the output signal of the input buffer 101 becomes smaller than the reference level, the LOS output signal 210 is enabled. If the control signal 310 is also enabled at this time, the squelch circuit 120 is turned on, and the output of the LA 700 is fixed at a constant level. The

  Even when the optical reception system is compatible with the dual rate, the squelch control at the time of no signal can be similarly performed with the LOS output. In this case, both the outputs of 10 Gbps and 1 Gbps may be fixed according to the LOS output. However, as a problem specific to a dual rate compatible system, only a signal of one rate of 10 Gbps or 1 Gbps is received at a certain time, but the same signal is output from an output terminal of a rate not received. Is output. The reason is that the input signal is distributed to the circuit for 10 Gbps and the circuit for 1 Gbps within LA. As described above, when a signal other than the target rate is input, the CDR once synchronizes to match the frequency of the signal, and then synchronizes when the signal of the target rate is input next. It will take.

  In order to prevent this problem, it is necessary to block or fix the level of the LA output other than the target rate. In a dual rate receiving system, if a signal representing the current rate of the received signal is obtained, the output of one rate can be cut off using the signal representing this rate. An example of such a system is disclosed in reference 2. In Reference Document 2, a rate selection signal representing a current data rate is generated using a determination circuit that determines a rate from a received data signal, and the signal is passed / blocked by a gate circuit.

MAX3761 data sheet, MAXIM, <http: // datasheets. maxim-ic. com / en / ds / MAX3761-MAX3762. pdf>, 2008 Kazutaka Hara et al., "1.25 / 10.3 Gbit / s Resetless Dual Rate Burst Mode Receiver", IEICE 2009 General Conference, B-10-101, 2009

As described above, squelch control for no signal input can be realized by using the LOS signal, and squelch control for dual rate can be realized by using the rate select signal. The squelch circuit can be controlled so that it is not.
However, at the time of system development or maintenance, there are cases where it is desired to know the output state of LA when there is no signal and the output state of a circuit on the rate side different from the rate of the received signal. Such a request cannot be met only by the circuits described so far. That is, in order to respond to such a request, control for enabling or disabling the LOS signal and control for enabling or disabling the rate select signal are necessary.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a dual rate receiving circuit capable of appropriately switching between a normal mode and a test mode.

  According to the present invention, in a dual rate receiving circuit that receives two time-divided signals of different data rates, the first rate signal amplifying signal having a received signal input to a signal input terminal is input. A squelch state in which an output signal from the first amplifier is cut off in accordance with a first squelch control signal and a second amplifier for amplifying a signal at a second rate that receives the received signal as an input Or a first squelch circuit that outputs an output signal of the first amplifier to a signal output terminal for a first rate, and an output signal of the second amplifier in response to a second squelch control signal A second squelch circuit that outputs the output signal of the second amplifier to the signal output terminal for the second rate, and a reference amplitude in which the amplitude of the received signal is predetermined Less than A detection circuit that outputs a LOS signal indicating whether or not, and in the normal mode, the first and second in accordance with the LOS signal and a rate select signal that is input from the outside and indicates the current rate of the received signal A squelch control signal, and in the test mode, a gate circuit for generating the first and second squelch control signals in which at least one of the squelch control by the LOS signal and the squelch control by the rate select signal is invalidated It is characterized by comprising.

Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit includes the first and second based on a logical product of the LOS signal and an LOS valid / invalid control signal input from the outside. By generating the squelch control signal, it is possible to select whether to enable or disable the squelch control by the LOS signal according to the LOS enable / disable control signal.
Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit outputs an output for a rate different from a current received signal rate when the amplitude of the received signal is larger than a reference amplitude in the normal mode. The first and second squelch control signals are generated so that the signal is in a squelch state, and when the amplitude of the received signal is equal to or lower than a reference amplitude in the normal mode, the output signals for the first and second rates The first and second squelch control signals are generated so that both are in a squelch state, and the squelch control by the LOS signal is invalidated by the LOS valid / invalid control signal, regardless of the state of the LOS signal. Generating the first and second squelch control signals so that an output signal for a rate different from the current received signal rate is in a squelch state. Is shall.

Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit includes the first and second gates based on a logical product of the rate select signal and a rate select valid / invalid control signal input from outside. By generating the second squelch control signal, it is possible to select whether to enable or disable the squelch control by the rate select signal according to the rate select enable / disable control signal.
Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit outputs an output for a rate different from a current received signal rate when the amplitude of the received signal is larger than a reference amplitude in the normal mode. The first and second squelch control signals are generated so that the signal is in a squelch state, and when the amplitude of the received signal is equal to or lower than a reference amplitude in the normal mode, the output signals for the first and second rates In the test mode in which the first and second squelch control signals are generated so that both are in a squelch state, and the squelch control by the rate select signal is invalidated by the rate select valid / invalid control signal, the amplitude of the received signal is The first and second squelch control signals are generated so that the output signals for the first and second rates do not enter the squelch state when the amplitude is larger than the reference amplitude. It is characterized in that it has a selectable Rukoto.

Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit inputs the logical product of the LOS signal and the LOS valid / invalid control signal input from the outside, and the rate select signal and the input from the outside. The first and second squelch control signals are generated by calculating a logical sum with a logical product result of the rate select valid / invalid control signal.
Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit outputs an output for a rate different from a current received signal rate when the amplitude of the received signal is larger than a reference amplitude in the normal mode. The first and second squelch control signals are generated so that the signal is in a squelch state, and when the amplitude of the received signal is equal to or lower than a reference amplitude in the normal mode, the output signals for the first and second rates The first and second squelch control signals are generated so that both are in a squelch state, and the squelch control by the LOS signal is invalidated by the LOS valid / invalid control signal, regardless of the state of the LOS signal. Generating the first and second squelch control signals so that an output signal for a rate different from the rate of the current received signal is in a squelch state; In the test mode in which the squelch control by the rate select signal is invalidated by the effective / ineffective control signal, the output signals for the first and second rates are in the squelch state when the amplitude of the received signal is larger than the reference amplitude. In the test mode in which the first and second squelch control signals are generated so that the squelch control by the LOS signal and the rate select signal is invalidated by the LOS valid / invalid control signal and the rate select valid / invalid control signal, The first and second squelch control signals are generated so that the output signals for the first and second rates do not enter a squelch state.

Further, in one configuration example of the dual rate receiving circuit of the present invention, the gate circuit is configured such that the LOS signal is input to one input terminal and the LOS valid / invalid control signal is input to the other input terminal. An AND gate; a second AND gate to which the rate select signal is input to one input terminal and the rate select enable / disable control signal is input to the other input terminal; an inverter that logically inverts the rate select signal; The rate select enable / disable control signal is input to one input terminal, the output signal of the inverter is input to the other input terminal, and the second AND gate of the second AND gate is input to one input terminal. An output signal is input, the output signal of the first AND gate is input to the other input terminal, and the first squelch control signal is output. The output signal of the third AND gate is input to the first OR gate and one input terminal, the output signal of the first AND gate is input to the other input terminal, and the second squelch control signal And a second OR gate for outputting.
Also, one configuration example of the dual rate receiving circuit of the present invention is characterized in that a NAND gate is used instead of the AND gate and the OR gate.

  According to the present invention, in a dual rate receiving circuit that receives two time-divided signals of different data rates, in the normal mode, a LOS signal and a rate select indicating the rate of the current received signal input from the outside The first and second squelch control signals are generated in response to the signals, and in the test mode, the first and second squelch controls in which at least one of the squelch control by the LOS signal and the squelch control by the rate select signal is invalidated By providing a gate circuit that generates a signal and controlling the first and second squelch circuits, a function that outputs data only from the signal output terminal corresponding to the rate of the received signal, and noise is output when there is no signal When testing the system while maintaining the function to prevent the It is possible to easily disable at least one of the squelch control by, can make various squelch control if necessary, it is possible to improve the convenience and system maintainability of test.

1 is a block diagram showing a configuration of a dual rate receiving circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the dual rate receiving circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the connection of the LOS detection circuit and squelch circuit of the conventional limiting amplifier.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a dual rate receiving circuit according to a first embodiment of the present invention. In the following description, the logic level is represented as “H” and the logic level is represented as “L”. The dual rate receiving circuit includes a dual rate compatible limiting amplifier (LA) 100 and a gate circuit.

  The LA 100 includes an input buffer 101 that receives a differential output signal input to the signal input terminal 102 from a circuit (not shown) such as a TIA in the previous stage, and a 10 Gbps amplifier that amplifies the differential output signal output from the input buffer 101. An amplifier 110, a 10 Gbps squelch circuit 120 that outputs a differential output signal output from the amplifier 110 as it is by blocking off a differential output signal output from the amplifier 110, or an input buffer 101 The 1 Gbps amplifier 130 that amplifies the differential output signal output from the amplifier 130, and the differential output signal output from the amplifier 130 is cut off to be in a no-signal output state, or the differential output signal output from the amplifier 130 is The 1 Gbps squelch circuit 140 that outputs the signal as it is and the differential output signal output from the squelch circuit 120 are 1 An output buffer 150 for 10 Gbps output to the signal output terminal 170 for Gbps, an output buffer 160 for 1 Gbps for outputting the differential output signal output from the squelch circuit 140 to the signal output terminal 180 for 1 Gbps, and an output signal of the input buffer 101 And a LOS detection circuit 200 for detecting whether or not is lower than a reference level.

  The squelch circuit 120 controls passage or blocking of the output signal of the amplifier 110 according to the digital control signal input from the squelch control signal input terminal 125 for 10 Gbps. Similarly, the squelch circuit 140 controls passage or blocking of the output signal of the amplifier 130 according to the digital control signal input from the 1 Gbps squelch control signal input terminal 145. In this embodiment, it is assumed that when “H” is input to the input terminals 125 and 145, the squelch state, that is, the reception signal is cut off.

  The LOS detection circuit 200 detects the amplitude of the output signal of the input buffer 101 and outputs from the LOS signal output terminal 215 an LOS signal 210 indicating whether or not the amplitude of the output signal of the input buffer 101 is equal to or smaller than a predetermined reference amplitude. Output as a binary digital signal. In this embodiment, it is assumed that “H” is output from the LOS signal output terminal 215 when the amplitude of the output signal of the input buffer 101 becomes equal to or lower than the reference amplitude.

  In the gate circuit, the LOS signal 210 is input to one input terminal, and the LOS valid / invalid control signal 310 that is a binary digital control signal that enables or disables the control by the LOS signal 210 is input to the other input terminal. The AND gate 400 is a binary digital control signal that receives a rate select signal 500 indicating the rate of the current received signal at one input terminal and enables or disables the control by the rate select signal 500 at the other input terminal. An AND gate 600 to which a certain rate select valid / invalid control signal 520 is inputted, an inverter 620 that logically inverts the rate select signal 500, a rate select valid / invalid control signal 520 is inputted to one input terminal, and the other input terminal is inputted. An AND gate 610 to which the output signal 510 of the inverter 620 is input. The output signal 530 of the AND gate 600 is input to one input terminal, the OR gate 630 to which the output signal 410 of the AND gate 400 is input to the other input terminal, and the output signal 540 of the AND gate 610 to one input terminal. And an OR gate 640 to which the output signal 410 of the AND gate 400 is input at the other input terminal.

  A subsequent digital control LSI (not shown) outputs a rate select signal 500 indicating the current rate of the received signal as a binary digital signal. In this embodiment, it is assumed that an “H” rate select signal 500 is input at 10 Gbps, and an “L” rate select signal 500 is input at 1 Gbps. Note that, as described above, the light receiving element and the TIA are provided in the previous stage of the dual rate receiving circuit of this embodiment, and the reception signal output from the TIA is input to the signal input terminal 102.

  Further, the gate circuit includes a LOS valid / invalid control signal 310 which is a binary digital control signal for validating or invalidating the control by the LOS signal 210 and a binary digital for validating or invalidating the control by the rate select signal 500. A rate select valid / invalid control signal 520 which is a control signal is given from the outside. In the present embodiment, when the LOS valid / invalid control signal 310 is “H”, the control by the LOS signal 210 is valid, and when the LOS valid / invalid control signal 310 is “L”, the control by the LOS signal 210 is invalid. When the rate select valid / invalid control signal 520 is “H”, control by the rate select signal 500 is valid, and when the rate select valid / invalid control signal 520 is “L”, control by the rate select signal 500 is invalid. Will be described.

  The AND gate 400 takes a logical product of the LOS signal 210 and the LOS valid / invalid control signal 310 and outputs the result of the logical product as a control signal 410. That is, when the LOS valid / invalid control signal 310 is “H”, “H” / “L” of the control signal 410 is determined according to the LOS signal 210, but when the LOS valid / invalid control signal 310 is “L”, the control signal 410 is determined. Always becomes “L”, and the control by the LOS signal 210 becomes invalid.

  On the other hand, the AND gate 600 takes a logical product of the rate select signal 500 and the rate select valid / invalid control signal 520 and outputs the result of the logical product as a control signal 530. The AND gate 610 calculates the logical product of the signal 510 obtained by logically inverting the rate select signal 500 with the inverter 620 and the rate select valid / invalid control signal 520 and outputs the result of the logical product as the control signal 540. By this logical operation, when the rate select valid / invalid control signal 520 is “H”, if the rate select signal 500 is “H”, the control signal 530 becomes “H”, the control signal 540 becomes “L”, and the rate select valid / invalid. When the control signal 520 is “H” and the rate select signal 500 is “L”, the control signal 530 is “L”, the control signal 540 is “H”, and the control by the rate select signal 500 becomes effective. When the rate select valid / invalid control signal 520 is “L”, the control signals 530 and 540 are always “L”, and the control by the rate select signal 500 is invalid.

The OR gate 630 takes a logical sum of the control signal 410 and the control signal 530 and outputs the result of the logical sum as a 1 Gbps squelch control signal 800. Similarly, the OR gate 640 takes a logical sum of the control signal 410 and the control signal 540 and outputs the result of the logical sum as a squelch control signal 810 for 10 Gbps.
Table 1 shows the control logic described above using a truth table.

According to Table 1, it is as follows.
(1) When a signal in which the output amplitude of the input buffer 101 is larger than the reference amplitude is received in the normal mode (both the LOS valid / invalid control signal 310 and the rate select valid / invalid control signal 520 are “H”). (LOS signal 210 is “L”), the squelch control signal (800 or 810) for a rate different from the rate of the current received signal becomes “H”, and the output for this rate is the squelch circuit (120 or 140). ) And is squelched. For example, if the rate select signal 500 is “L”, that is, the rate of the current received signal is 1 Gbps, the 1 Gbps squelch control signal 800 is “L”, the 10 Gbps squelch control signal 810 is “H”, and the squelch circuit 120 cuts off the output for 10 Gbps.

(2) In the normal mode, when a signal whose output amplitude of the input buffer 101 is lower than the reference amplitude is received (LOS signal 210 is “H”), the 1 Gbps squelch control signal 800 and the 10 Gbps squelch control signal Both 810 become “H”, the squelch circuit 120 cuts off the output for 10 Gbps, the squelch circuit 140 cuts off the output for 1 Gbps, and both outputs are in the squelch state.

(3) In the LOS signal invalid mode (the LOS valid / invalid control signal 310 is “L” and the rate select valid / invalid control signal 520 is “H”), which is a test mode, a signal in which the output amplitude of the input buffer 101 is less than the reference amplitude. , The squelch control signal for the current received signal rate remains “L”, and the output for the current received signal rate does not squelch.

(4) In the rate select invalid mode (LOS valid / invalid control signal 310 is “H” and the rate select valid / invalid control signal 520 is “L”), which is a test mode, the output amplitude of the input buffer 101 is larger than the reference amplitude. When a signal is received (LOS signal 210 is “L”), the outputs for both 1 Gbps and 10 Gbps are not squelched regardless of the current received signal rate.

(5) When both the LOS signal invalid mode and the rate select invalid mode are on (the LOS valid / invalid control signal 310 and the rate select valid / invalid control signal 520 are both “L”), the states of the LOS signal 210 and the rate select signal 500 Regardless of the output, both outputs for 1 Gbps and 10 Gbps are not squelched.

  As described above, in this embodiment, the squelch control signals 800 and 810 are generated according to the LOS signal 210 and the rate select signal 500 in the normal mode, and the squelch control and the rate select signal using the LOS signal 210 are performed in the test mode. By providing a gate circuit for generating squelch control signals 800 and 810 in which at least one of the squelch controls by 500 is invalidated and controlling the squelch circuits 120 and 140, only the signal output terminal on the side corresponding to the rate of the received signal is provided. In the case of a system test or the like while retaining the function of outputting data from the signal and the function of preventing the output of noise when there is no signal, the squelch control by the LOS signal 210 and the squelch control by the rate select signal 500 At least one can be easily disabled , You can make various squelch control if necessary, it is possible to improve the convenience and system maintainability of test.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a configuration of a dual rate receiving circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The configuration of LA100 is the same as that of the first embodiment.

  In the gate circuit of the present embodiment, a NAND gate 401 to which a LOS signal 210 is input to one input terminal and a LOS valid / invalid control signal 310 is input to the other input terminal, and a rate select signal 500 to one input terminal. Is input to the other input terminal and the NAND gate 601 to which the rate select enable / disable control signal 520 is input to the other input terminal, and the NAND gate 621 that inputs the rate select signal 500 to both input terminals and logically inverts the rate select signal 500. The rate select enable / disable control signal 520 is input to one input terminal, the output signal 511 of the NAND gate 621 is input to the other input terminal, and the output signal 531 of the NAND gate 601 is input to one input terminal. Is input to the other input terminal. NAND gate 631 to which 411 is input, and NAND gate 641 to which the output signal 541 of NAND gate 611 is input to one input terminal and the output signal 411 of NAND gate 401 is input to the other input terminal. .

  The control logic of the present embodiment is as shown in Table 1 of the first embodiment. In the first embodiment, a circuit using an AND gate and an OR gate is shown. However, in this embodiment, the same logic as that of the first embodiment can be realized using only a NAND gate. As described above, in this embodiment, only the NAND gate can be used, and the cost can be reduced as compared with the first embodiment.

  The present invention can be applied to a dual rate receiving circuit used in a receiver or the like of an optical communication system.

  DESCRIPTION OF SYMBOLS 100 ... Dual-rate limiting amplifier, 101 ... Input buffer, 102 ... Signal input terminal, 110 ... Amplifier for 10Gbps, 120 ... Squelch circuit for 10Gbps, 125 ... Squirch control signal input terminal for 10Gbps, 130 ... Amplifier for 1Gbps ... 1 Gbps squelch circuit, 145 ... 1 Gbps squelch control signal input terminal, 150 ... 10 Gbps output buffer, 160 ... 1 Gbps output buffer, 170 ... 10 Gbps signal output terminal, 180 ... 1 Gbps signal output terminal, 200 ... LOS detection Circuit, 210 ... LOS signal, 215 ... LOS signal output terminal, 310 ... LOS valid / invalid control signal, 400, 600, 610 ... AND gate, 401, 601, 611, 621, 631, 641 ... NAND gate, 500 Rate select signal, 520 ... Rate Select valid or invalid control signal, 620 ... inverter, 630,640 ... OR gate, 800 ... squelch control signal for 1Gbps, 810 ... 10Gbps for squelch control signal.

Claims (9)

In a dual rate receiving circuit that receives signals of two different data rates that are time-divided,
A first amplifier for amplifying a signal at a first rate, which receives a received signal input to a signal input terminal;
A second amplifier for signal amplification at a second rate, which receives the received signal,
In response to a first squelch control signal, the output signal of the first amplifier is cut off to enter a squelch state, or the output signal of the first amplifier is output to a signal output terminal for a first rate. 1 squelch circuit,
In response to a second squelch control signal, the output signal of the second amplifier is cut off to enter a squelch state, or the output signal of the second amplifier is output to a signal output terminal for a second rate. Two squelch circuits,
A detection circuit that outputs a LOS signal indicating whether the amplitude of the received signal is equal to or less than a predetermined reference amplitude;
In the normal mode, the first and second squelch control signals are generated according to the LOS signal and a rate select signal indicating the rate of the current received signal input from the outside. In the test mode, the LOS signal is generated. A dual rate receiving circuit comprising: a gate circuit that generates the first and second squelch control signals in which at least one of squelch control by signals and squelch control by the rate select signal is invalidated. The dual rate receiver circuit according to claim 1, wherein
The gate circuit generates the first and second squelch control signals based on a logical product of the LOS signal and an LOS valid / invalid control signal input from the outside, thereby generating the LOS valid / invalid control signal. According to the dual rate receiving circuit, the squelch control by the LOS signal can be selected to be enabled or disabled. The dual rate receiver circuit according to claim 2, wherein
In the normal mode, when the amplitude of the received signal is larger than a reference amplitude, the gate circuit performs the first and second squelch so that an output signal for a rate different from the current received signal rate is in a squelch state. When the control signal is generated and the amplitude of the received signal is equal to or lower than the reference amplitude in the normal mode, the first and second squelch are set so that the output signals for the first and second rates are both in the squelch state. In the test mode in which the control signal is generated and the squelch control by the LOS signal is invalidated by the LOS valid / invalid control signal, an output signal for a rate different from the current received signal rate is generated regardless of the state of the LOS signal. A dual-rate receiving circuit, wherein the first and second squelch control signals are generated so as to be in a squelch state. The dual rate receiver circuit according to claim 1, wherein
The gate circuit generates the first and second squelch control signals based on a result of a logical product of the rate select signal and a rate select enable / disable control signal input from the outside, thereby enabling the rate select enable A dual-rate receiving circuit, wherein it is possible to select whether to enable or disable the squelch control by the rate select signal according to an invalid control signal. The dual rate receiver circuit according to claim 4,
In the normal mode, when the amplitude of the received signal is larger than a reference amplitude, the gate circuit performs the first and second squelch so that an output signal for a rate different from the current received signal rate is in a squelch state. When the control signal is generated and the amplitude of the received signal is equal to or lower than the reference amplitude in the normal mode, the first and second squelch are set so that the output signals for the first and second rates are both in the squelch state. In the test mode in which the control signal is generated and the squelch control by the rate select signal is invalidated by the rate select valid / invalid control signal, the first and second rates when the amplitude of the received signal is larger than a reference amplitude Dual-rate receiving, wherein the generation of the first and second squelch control signals can be selected so that the output signal for use is not in a squelch state. Circuit. The dual rate receiver circuit according to claim 1, wherein
The gate circuit includes a logical product of the LOS signal and an LOS valid / invalid control signal input from outside, and a logical product of the rate select signal and a rate select valid / invalid control signal input from outside. The dual rate receiving circuit, wherein the first and second squelch control signals are generated by taking the logical sum of The dual rate receiver circuit according to claim 6, wherein
In the normal mode, when the amplitude of the received signal is larger than a reference amplitude, the gate circuit performs the first and second squelch so that an output signal for a rate different from the current received signal rate is in a squelch state. When the control signal is generated and the amplitude of the received signal is equal to or lower than the reference amplitude in the normal mode, the first and second squelch are set so that the output signals for the first and second rates are both in the squelch state. In the test mode in which the control signal is generated and the squelch control by the LOS signal is invalidated by the LOS valid / invalid control signal, an output signal for a rate different from the current received signal rate is generated regardless of the state of the LOS signal. The first and second squelch control signals are generated so as to be in the squelch state, and the rate select signal is generated by the rate select enable / disable control signal. In the test mode in which the squelch control is disabled, the first and second squelch controls are performed so that the output signals for the first and second rates do not enter the squelch state when the amplitude of the received signal is larger than a reference amplitude. Output for the first and second rates in a test mode in which a signal is generated and the squelch control by the LOS signal and the rate select signal is invalidated by the LOS valid / invalid control signal and the rate select valid / invalid control signal. A dual-rate receiving circuit, wherein the first and second squelch control signals are generated so that the signal does not enter a squelch state. The dual rate receiving circuit according to claim 6 or 7,
The gate circuit is
A first AND gate in which the LOS signal is input to one input terminal and the LOS valid / invalid control signal is input to the other input terminal;
A second AND gate to which the rate select signal is input to one input terminal and the rate select enable / disable control signal is input to the other input terminal;
An inverter that logically inverts the rate select signal;
A third AND gate in which the rate select enable / disable control signal is input to one input terminal and the output signal of the inverter is input to the other input terminal;
The output signal of the second AND gate is input to one input terminal, the output signal of the first AND gate is input to the other input terminal, and the first OR that outputs the first squelch control signal is output. The gate,
The output signal of the third AND gate is input to one input terminal, the output signal of the first AND gate is input to the other input terminal, and the second OR outputs the second squelch control signal. A dual rate receiving circuit comprising a gate. The dual rate receiver circuit according to claim 8, wherein
A dual rate receiving circuit using a NAND gate instead of the AND gate and the OR gate.

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