JP2011198100A - Processor and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor which attains area reduction and operation frequency reduction, and a control method thereof.SOLUTION: The processor executes a maximum of eight instructions out of first to fourth instructions and fifth to eighth instructions in parallel and includes: first to m-th operation units 142-148 each of which one of the first to eighth instructions is input to; and selectors which are provided correspondingly to the first to m-th operations units 142-148 respectively and each of which selects one of the first to m-th instructions to input the selected instruction to corresponding one of the first to m-th operation units 142-148. The first to fourth instructions are input to the first to eighth selectors respectively, and the fifth to eighth instructions are input to the fifth to eighth and following selectors respectively.

Description

  The present invention relates to a processor capable of executing instructions in parallel and a control method thereof, and more particularly to a processor capable of executing, for example, a VLIW (Very Long Instruction Word) instruction and a control method thereof.

  Conventionally, there is a method of executing a plurality of instructions in parallel in order to improve the processing capability of a processor such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor). This method is called a superscalar where the hardware automatically detects the parallel execution of instructions and executes them in parallel, and when the program is compiled and assembled, the parallelism of the instructions is detected in advance. There is a so-called VLIW (Very Long Instruction Word) that generates a possible instruction code. Processors for embedded devices often use the VLIW method with a simple circuit configuration in terms of power consumption and area.

  In order to improve performance in recent processors, the degree of instruction parallelism may increase, and even if the VLIW processor is simple in circuit configuration, each instruction included in a group of instructions executed in parallel is issued to the corresponding arithmetic unit. The problem is that the operating frequency becomes large and the operating frequency decreases.

  As described in Patent Document 1 as a technique for solving this problem, the instruction group read from the instruction memory is issued by rearranging the order of the instructions in the instruction group before issuing the instruction group to each arithmetic unit. An instruction memory that reduces the circuit selection circuit to reduce area and frequency degradation, and arranges the order of instructions in the instruction group in a fixed order during compilation and assembly as described in Patent Document 2. In some cases, the selection circuit of the issuing circuit is reduced to reduce the area and the frequency deterioration. All of them are characterized in that each instruction is arranged in a certain order (law) at the stage of issuing each instruction to the corresponding arithmetic unit.

  Instructions when the order of instructions when issuing instructions is free and when they are based on a certain order (law) in a processor having eight arithmetic units of MX / MY / AX / AY / DX / DY / SX / SY The difference between the issuing circuits will be described. Here, MX / MY, AX / AY, DX / DY, and SX / SY each indicate two identical arithmetic units, the first being * X and the second being * Y. In addition, since MY, AY, DY, and SY are the second arithmetic units, instructions are not issued only to MY, AY, DY, and SY, and instructions to MX, AX, DX, and SY are always issued. Issue needs to be made. For convenience of explanation, the maximum number of instructions executed in parallel read from the instruction memory is 8 in parallel.

  When the instruction order is free, an instruction belonging to the MX arithmetic unit may exist in any slot of the instruction 1 slot to the instruction 8 slot in the instruction register. Similarly, an instruction belonging to the AX arithmetic unit, an instruction belonging to the DX arithmetic unit, and an instruction belonging to the SX arithmetic unit may exist in any slot of the instruction 1 slot to the instruction 8 slot in the instruction register. In addition, instructions belonging to the MY arithmetic unit, instructions belonging to the AY arithmetic unit, instructions belonging to the DY arithmetic unit, and instructions belonging to the SY arithmetic unit are premised on execution of instructions belonging to the MX, AX, DX, and SX arithmetic units, respectively. There is a possibility that the slot exists in any slot of the instruction 2 slot to the instruction 8 slot in the instruction register. Therefore, the instruction issuance circuit is an 8to1 selection circuit that can be selected from any of the instruction 1 slot to the instruction 8 slot for the MX / AX / DX / SX arithmetic unit, and the instruction 2 slot for the MY / AY / DY / SY arithmetic unit. ~ 7 to 1 selection circuit which can be selected from any of the instruction 8 slots. In other words, four 8to1 selection circuits and four 7to1 selection circuits are required.

Next, an instruction issue circuit when the order of instructions at the time of issuing instructions is fixed in the order of MX → MY → AX → AY → DX → DY → SX → SY will be described.
When the order of instructions is fixed as described above, the following can be said.

  (1) An instruction belonging to the MX operation unit exists in the instruction 1 slot, or there is no instruction to be executed and there is no instruction register.

  (2) Since an instruction belonging to the MY arithmetic unit is premised on an instruction belonging to the MX arithmetic unit being executed, it does not exist in the instruction 1 slot. Therefore, either in the instruction 2 slot, or there is no instruction to be executed and there is no instruction register.

  (3) The instruction slot in which an instruction belonging to the AX arithmetic unit exists depends on the presence / absence of an instruction belonging to the MX arithmetic unit and the MY arithmetic unit. MX / MY does not exist and exists in the instruction 1 slot, or only MX exists in the instruction 2 slot, MX / MY exists in the instruction 3 slot, or there is no instruction to be executed Either not present in the register.

  (4) The instruction slot in which an instruction belonging to the AY arithmetic unit exists depends on the presence or absence of an instruction belonging to the MX arithmetic unit and the MY arithmetic unit, and is determined on the assumption that the instruction belonging to the AX arithmetic unit is executed. MX / MY does not exist, AX exists in the instruction 1 slot, AY exists in the instruction 2 slot, or only MX exists, AX exists in the instruction 2 slot, AY exists in the instruction 3 slot, or MX / MY exists Either AX is in the instruction 3 slot and AY is in the instruction 4 slot, or there is no instruction to be executed and there is no instruction register.

  Similarly, the instruction slots in which instructions belonging to the DX, DY, SX, and SY operation units exist are as follows.

  (5) The instruction belonging to the DX arithmetic unit exists either in the instruction 1 slot to the instruction 5 slot, or there is no instruction to be executed and it does not exist in the instruction register.

  (6) The instruction belonging to the DY operation unit exists in any of the instruction 2 slot to the instruction 6 slot, or there is no instruction to be executed and there is no instruction register.

  (7) The instruction belonging to the SX arithmetic unit is either in the instruction 1 slot to the instruction 7 slot, or there is no instruction to be executed and it is not in the instruction register.

  (8) The instruction belonging to the SY arithmetic unit is either in the instruction 2 slot to the instruction 8 slot, or there is no instruction to be executed and it is not in the instruction register.

Therefore, the instruction issue circuit has the following configuration.
(A) For MX / MY, the instruction 1 slot and instruction 2 slot are directly connected to each other.
(A) For AX / AY, select from three instruction slots of instruction 1 slot to instruction 3 slot and instruction 2 slot to instruction 4 slot, respectively.
(C) For DX / DY, select from five instruction slots of instruction 1 slot to instruction 5 slot and instruction 2 slot to instruction 6 slot, respectively.
(D) For SX / SY, select from 7 instruction slots from instruction 1 slot to instruction 7 slot and instruction 3 slot to instruction 8 slot, respectively.
In other words, two 3to1 selection circuits, two 5to1 selection circuits, and two 7to1 selection circuits are required.

  If each selection circuit is configured with a 2to1 selection circuit for area comparison, the 8to1 selection circuit has seven 2to1 selection circuits, the 7to1 selection circuit has six 2to1 selection circuits, the 5to1 selection circuit has four 2to1 selection circuits, and 3to1. Since the selection circuit is replaced with two 2to1 selection circuits, the instruction issuing circuit portion when the instruction order is free is 7 × 4 + 6 × 4 = 52, which corresponds to 52 2to1 selection circuits, and the instruction issuing circuit when the instruction order is fixed The portion is 6 × 2 + 4 × 2 + 2 × 2 = 24, which corresponds to 24 2to1 selection circuits, and it can be seen that the area can be greatly reduced.

  Regarding the frequency, the number of logic stages of the 8to1 selection circuit and the 7to1 selection circuit does not change with 3 stages, so the number of logic stages of the maximum delay path does not change, but optimization at the time of logic synthesis by clarifying a path with a large delay and a small path The operation frequency is improved by the effect of reducing the wiring length, reducing the number of detour wirings, and the like.

  Such an instruction processing method will be described in more detail. FIG. 3 is a diagram showing the VLIW processor described in Patent Document 2. As shown in FIG. As shown in FIG. 3, the VLIW processor includes an instruction reading unit 221 that reads an instruction from the memory 220, an instruction register 222 having four instruction slots 0 to 3, and an instruction issuing unit 223 that distributes instructions from the instruction register 222. And an instruction execution unit 224 for executing instructions. Each arithmetic unit of the instruction execution unit 224 executes an instruction from the instruction register 222 while referring to the registers PC, GR, and FR. Here, the instruction execution unit 224 includes IU0 and IU1 that are integer units, FU0 and FU1 that are floating-point units, and BU0 and BU1 that are branch units. The processor includes a general-purpose register GR, a floating-point register FR, and a program counter PC.

  Here, it is assumed that the 22 VLIW instructions shown in FIG. 4 can be executed as a sequence of basic instructions in the VLIW instruction. In FIG. 4, the meanings of the symbols are as follows. I0 means that a basic instruction executed in IU0 is arranged. I1 means that a basic instruction executed by IU1 is arranged. F0 means that a basic instruction executed in FU0 is arranged. F1 means that a basic instruction executed in FU1 is arranged. B0 means that a basic instruction executed in BU0 is arranged. B1 means that a basic instruction executed in BU1 is arranged. A blank means that a basic instruction is not arranged.

  The instruction issuing unit supplies the instruction read from the instruction register to the corresponding functional units IU, FU, and BU. Up to 4 instructions can be executed simultaneously, and instructions are supplied to up to 4 functional units out of 6 functional units.

  Basic instructions held in the instruction slot 0 can be supplied to the IU0, FU0, and BU0. The basic instruction held in the instruction slot 1 can be supplied to FU0, IU1, FU1, BU0, and BU1. The basic instruction held in the instruction slot 2 can be supplied to IU1, FU1, BU0, and BU1. The basic instruction held in the instruction slot 3 can be supplied to FU1, BU0, and BU1. In addition, the arrangement of basic instructions in the VLIW instruction allowed in this processor is as shown in FIG.

  When the order of the instructions is determined in this way, the instruction issuing unit 223 does not need to be able to supply each instruction to all the functional units but can be configured to be stored in a predetermined functional unit. it can.

JP2001-100997 JP 2002-323882

  However, the technique described in Patent Document 2 has no problem in the case of a new processor, but there is a problem in terms of diversion of past software assets in the case of an extension of a past processor, that is, a processor that requires compatibility. . Specific examples are shown below.

  The method described in Patent Document 2 is a technique for solving a problem when the degree of instruction parallelism has increased for the recent performance improvement. In other words, it can be said that the instruction parallelism was not so high in the previous processor because of the required performance and the chip area, and it was not a required technology. For example, in the previous generation processor, it is assumed that the instruction parallelism is 4 parallelism. In the case of about 4 parallels, there may be a case where the instruction order is free due to the size and frequency of the instruction issuing circuit. In that case, it is possible that the instructions are arranged in the order of AX → MX → DX in the instruction register. In such a case, since MX can only read from the instruction 1 slot, the MX instruction existing in the instruction 2 slot cannot be read and cannot be executed.

  In the case of software developed in-house, it is possible to rearrange the order of instructions by compiling or reassembling. However, in the case of software purchased from an IP vendor, the source code is usually intellectual property and cannot be obtained. For this reason, the difficulty of rearranging the order of instructions becomes very high. At present, software distribution by IP vendors specializing in multimedia processing such as video and images is active, and there is a possibility that a large amount of software that cannot be diverted by conventional technology may occur.

  The processor according to the present invention parallels a maximum of m instructions from the first instruction to the nth instruction (n is a natural number) and the (n + 1) th instruction to the mth instruction (m> n is a natural number of 2 or more). A processor to be executed, which is provided corresponding to each of the first to m-th arithmetic units to which any one of the first to m-th instructions is input and executed; A first to m-th selector for selecting any of the first to m-th instructions and inputting the selected instruction to the first to m-th arithmetic units, wherein the first to n-th instructions are the first to m-th instructions. The (n + 1) th to mth instructions are input to each of the selectors, and are input to the (n + 1) th to mth and subsequent selectors, respectively.

  The control method of the processor according to the present invention is a maximum of m instructions from the first instruction to the nth instruction (n is a natural number) and the (n + 1) th instruction to the mth instruction (m> n is a natural number of 2 or more). Are controlled in parallel by the first to m-th arithmetic units, and the first to n-th instructions are input to any one of the first to m-th arithmetic units. The (n + 1) th to mth instructions are input to the (n + 1) th to mth arithmetic units.

  In the present invention, since the first to n-th instructions are input to the first to m-th selectors, they can be operated in any of the first to m-th arithmetic units. On the other hand, when there are n or more instructions, the instructions are input in order, so that the (n + 1) th to mth instructions are input to the (n + 1) th to mth selectors, respectively. Operations can be performed by (n + 1) to the m-th operation unit.

  According to the present invention, it is possible to provide a processor capable of reducing the area and operating frequency and a control method thereof.

It is a figure which shows the processor concerning Embodiment 1 of this invention. It is a figure which shows the processor concerning Embodiment 2 of this invention. FIG. 11 is a diagram showing a VLIW processor described in Patent Document 2. It is a figure which shows the arrangement | sequence of the basic command in VLIW which can perform the modulation | alteration VLIW shown in FIG.

Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a processor that executes parallel instructions.
Embodiment 1 of the present invention.

  FIG. 1 is a diagram showing a processor 100 according to the first embodiment of the present invention. The processor 100 includes an instruction reading unit 11, an instruction register 12, an instruction issuing unit 13, an operation execution unit 14 including eight operation units, and a memory 15. Note that the memory 15 may be external to the processor.

  The instruction reading unit 11 reads a plurality of memories from the memory 15 and supplies them to the instruction register 12. In the case of this example, a maximum of eight instructions among the instructions read from the memory 15 are supplied to the instruction register 12 at the same time.

  The instruction register 12 is configured to hold eight instructions in order to execute eight instructions 1 to 8 in parallel.

  The instruction issuing unit 13 includes selection circuits 131 to 138 and distributes the instruction from the instruction register 12 to each arithmetic unit.

  The arithmetic unit is composed of eight arithmetic units: MX arithmetic unit 141, MY arithmetic unit 142, AX arithmetic unit 143, AY arithmetic unit 144, DX arithmetic unit 145, DY arithmetic unit 146, SX arithmetic unit 147, and SY arithmetic unit 148. .

  Here, the processor receives at most m instructions from the first instruction to the nth instruction (n is a natural number) and the (n + 1) th instruction to the mth instruction (m> n is a natural number of 2 or more). If the processors are executed in parallel, the arithmetic unit is an arithmetic unit that receives and executes any of the first to m-th instructions. In this example, an example of m = 8 arithmetic units is shown. Here, the MX arithmetic unit 141 and the MY arithmetic unit 142 indicate the same arithmetic unit, and are, for example, multipliers. The AX arithmetic unit 143 and the AY arithmetic unit 144 indicate the same arithmetic unit, for example, an arithmetic logic circuit. The DX arithmetic unit 145 and the DY arithmetic unit 146 indicate the same arithmetic unit, and are, for example, a data load store. The SX arithmetic unit 147 and the SY arithmetic unit 148 indicate the same arithmetic unit, and are system instructions, for example.

  In the following description, it is assumed that n = 4. That is, the order of the first to fourth instructions is not determined, and it is unknown which instruction is input to which arithmetic unit. In the fifth to eighth instructions, the instructions are input to the arithmetic unit in this order.

  In this case, the eight selectors are provided corresponding to the first to eighth arithmetic units, respectively, and select one of the first to eighth instructions and input it to the first to eighth arithmetic units. It is. The first to fourth instructions are input to the first to eighth selectors, and the fifth to eighth instructions are input to the fifth to eighth selectors, respectively.

  Here, the instructions 2 to 4 are connected to all the selection circuits, but the instruction 1 is connected only to the selection circuits 1, 3, 5, and 7. This is because the instruction 1 is input only to the MX arithmetic unit 141, the AX arithmetic unit 143, the DX arithmetic unit 145, and the SX arithmetic unit 147. The MY arithmetic unit 142, the AY arithmetic unit 144, the DY arithmetic unit 146, and This is because the SY operation unit 148 may receive an instruction for the first time when there is an instruction 1 slot.

  In this embodiment, instructions 1 to n (n is the maximum instruction parallel of the previous generation processor) so that instructions can be issued even in the case where the instruction order is free up to the instruction slot corresponding to the instruction parallelism in the previous generation processor. In the present embodiment, n = 4) is connected to the selection circuits of all the arithmetic units, and the instructions after the instruction n are present according to the respective arithmetic units and instruction order rules as in the prior art. Only possible instructions are connected to the selection circuit. However, since the selection circuit corresponding to the MY / AY / DY / SY arithmetic unit is premised on the execution of the instruction in the MX / AX / DX / SX arithmetic unit, it is not connected to the instruction 1 slot. The diagram shown in FIG. 1 shows a configuration when the instruction parallelism is 8 and the instruction parallelism of the previous generation processor is 4.

  Here, since the maximum instruction parallelism n = 4 in the previous generation processor, when instructions out of order are input, only the instructions 1 to 4 are used at the maximum, and the number of parallel instructions is 4 or less. On the other hand, when the number of instructions is 5 or more, the instructions 1 to 8 are in the order of MX → MY → AX → AY → DX → DY → MX → MY.

  For example, in the example shown in FIG. 1, even when instructions are arranged in the order of DX → MX → AX → SX, the DX instruction existing in the instruction 1 slot can be issued to the DX arithmetic unit via the selection circuit 5. Further, the MX instruction existing in the instruction 2 slot can be issued to the MX arithmetic unit via the selection circuit 1. Further, the AX instruction existing in the instruction 3 slot can be issued to the AX arithmetic unit via the selection circuit 3. Furthermore, the SX instruction existing in the instruction 4 slot can be issued to the SX arithmetic unit via the selection circuit 7.

  In this embodiment, the instruction 2 slot to the instruction 4 slot are connected to all the arithmetic units, and the instruction 1 slot is connected to the MX / AX / DX / SX arithmetic unit via the selection circuit 1 to the selection circuit 8. The instructions can be issued correctly regardless of the order in which they exist in the instruction 1 slot to the instruction 4 slot corresponding to the maximum parallelism of the previous generation processor. On the other hand, the instruction 5 slot to the instruction 8 slot are slots that are not used in the previous generation processor and are used only by the new processor. Therefore, when the number of instructions is 5 or more, the area is reduced by fixing the instruction order. The operating frequency can be improved.

  That is, since the instruction 5 to 8 slots are sequentially input to the DX operation unit 145, the DY operation unit 146, the SX operation unit 147, and the SY operation unit 148, the instruction 5 slot corresponds to the selection circuits 5 to 8 after the selection circuit 5. The instruction 6 slot may be connected to the selection circuits 6 to 8 after the selection circuit 6, the instruction 7 slot may be connected to the selection circuits 7 to 8 after the selection circuit 7, and the instruction 8 slot only to the selection circuit 8.

  In the present embodiment, when the area is calculated on the basis of the 2to1 selection circuit as in the conventional example, 6 × 2 + 4 × 2 + 3 × 2 + 2 × 2 = 30, which corresponds to 30 2to1 selection circuits. Although the area is larger than the equivalent of 24 conventional 2to1 selection circuits, even if the instruction parallelism is expanded to improve performance, area reduction and operation are maintained while maintaining binary compatibility with previous generation processors. Frequency reduction can be achieved.

In addition, by clarifying paths with large delays and paths with small delays, the optimization of logic synthesis is easy to proceed, and by reducing the area, the operating frequency is reduced due to effects such as reduced wiring length and reduced bypass wiring. improves.
Embodiment 2 of the present invention.

  Next, a second embodiment of the present invention will be described. In the present embodiment, the configuration of the instruction issuing unit 16 and the operation executing unit 17 is different from that of the first embodiment. That is, there are three types of arithmetic units, MX, MY, and MZ are the same arithmetic unit, AX is only one arithmetic unit, and DX, DY, DZ1, and DZ2 are the same arithmetic unit. The connection of the instruction issuing unit 16 in this case is as shown in FIG. FIG. 2 is a diagram illustrating the processor according to the present embodiment.

  As in the first embodiment, the number m of arithmetic units is 8, and the maximum instruction parallelism n of the previous generation processor is 4. In this case, the instruction 2-4 slots are connected to all the selection circuits 1-8. On the other hand, the instruction 1 slot is connected to the MX arithmetic unit 171, the AY arithmetic unit 174, and the DX arithmetic unit 175. As described above, since the MY arithmetic unit 172 and the DY arithmetic unit 176 have an instruction when the instruction of the MX arithmetic unit 171 and the DX arithmetic unit 175 exists, the instruction 1 slot includes the selection circuits 2, 3, 6. There is no need to enter ~ 8.

  Also in this embodiment, for example, even if an instruction such as DX → MX → MY → AX is issued, the DX instruction existing in the instruction 1 slot is issued to the DX arithmetic unit 175 via the selection circuit 5. Is done. The MX instruction existing in the instruction 2 slot is issued to the MX arithmetic unit 171 via the selection circuit 1. Further, the MY instruction existing in the instruction 3 slot is issued to the MY arithmetic unit 172 via the selection circuit 2, and the AX instruction existing in the instruction 4 slot is issued to the AY arithmetic unit 174 via the selection circuit 4. Is done.

  When the number of instructions is five or more, the instructions are input in the order of MX → MY → MZ → AX → DX → DY → DZ1 → DZ2, and therefore the instruction 5 slot has a selection circuit 5 after the selection circuit 5. If the instruction 6 slot is connected to the selection circuit 6 or later, the instruction 7 slot is connected to the selection circuit 7 or later, and the instruction 8 slot is connected to the selection circuit 8 only. Good.

  Also in this embodiment, the same effects as in the embodiment can be obtained. When the area is calculated on the basis of the 2to1 selection circuit as in the conventional example, 5 × 2 + 4 × 2 + 3 × 2 + 2 × 2 = 20 corresponds to 28 2to1 selection circuits. Even when the instruction parallelism is expanded to improve performance, it is possible to reduce the area and operating frequency while maintaining binary compatibility with the previous generation processor.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 11 Instruction reading part 12 Instruction register 13, 16 Instruction issuing part 14, 17 Operation execution part 15 Memory 141 MX operation unit 142 MY operation unit 143 AX operation unit 144 AY operation unit 145 DX operation unit 146 DY operation unit 147 SX operation unit 148 SY operation unit 171 MX operation unit 172 MY operation unit 173 MZ operation unit 174 AX operation unit 175 DX operation unit 176 DY operation unit 177 DZ1 operation unit 178 DZ2 operation unit 220 memory 221 instruction read unit 222 instruction issue unit 224 instruction Execution unit PC register GR register FR register

Claims (9)

A processor that executes at most m instructions in parallel among a first instruction to an nth instruction (n is a natural number) and an (n + 1) th instruction to an mth instruction (m> n is a natural number of 2 or more),
First to m-th arithmetic units that receive and execute any of the first to m-th instructions;
First to m-th selectors provided corresponding to the first to m-th arithmetic units, respectively, for selecting any one of the first to m-th instructions and inputting the selected instruction to the first to m-th arithmetic units. And
The first to nth instructions are input to each of the first to m selectors,
The (n + 1) th to mth instructions are input to the (n + 1) th to mth and subsequent selectors, respectively.   When the 1 to m arithmetic units are composed of s (s is a natural number) groups of the same arithmetic unit for every k (k is an arbitrary variable), the first instruction is the first arithmetic unit of each group. The processor according to claim 1, wherein the processor is input only to a selector corresponding to.   3. The processor according to claim 1, wherein the first to nth instructions are instructions whose order is not defined, and the (n + 1) th to mth instructions are instructions whose order is defined.   The processor according to claim 1, wherein n represents a maximum instruction parallelism of a previous generation processor.   5. The processor according to claim 1, wherein the processor is a VLIW (Very Long Instruction Word) type processor. The first to m-th arithmetic units receive a maximum of m instructions from the first instruction to the n-th instruction (n is a natural number) and the (n + 1) -th instruction to the m-th instruction (m> n is a natural number of 2 or more). A method for controlling a processor that executes in parallel,
The first to n-th instructions are input to any one of the first to m-th arithmetic units;
The processor control method, wherein the (n + 1) through m-th instructions are input to the (n + 1) through m-th and subsequent arithmetic units.   When the 1 to m arithmetic units are composed of s (s is a natural number) groups of the same arithmetic unit for every k (k is an arbitrary variable), the first instruction is the first arithmetic unit of each group. The processor according to claim 6, wherein the processor is input only to a selector corresponding to.   The processor according to claim 6 or 7, wherein the first to nth instructions are instructions whose order is not defined, and the (n + 1) th to mth instructions are instructions whose order is defined.   The processor according to any one of claims 6 to 8, wherein n represents a maximum instruction parallelism of a previous generation processor.

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