JP2011197876A - Program, apparatus and method for optimization processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of executing optimization by blocking even to a multiple loop not smaller than a triple loop, and the multiple loop including an array of a three-dimensional array or more.SOLUTION: A processing target loop analysis part 100 extracts a tight loop from a source program as a blocking target loop. An array analysis part 110 extracts an array included in the blocking target loop. When there is an array whose access pattern is a cross, an access pattern analysis part 120, determines that blocking to the blocking target loop is valid. A memory size calculation formula generation part 130 generates a calculation formula of a size of a memory to be accessed by the array. A divided block length calculation part 140 determines a divided block length by which a memory size not exceeding a cache size can be obtained by using the memory size calculation formula. An optimization execution part 17 executes blocking using the determined divided block length.

Description

  The present invention relates to an optimization processing program, an optimization processing apparatus, and an optimization processing method for optimizing a loop included in a source program described in a programming language.

  The compiler provides an optimization technique called blocking as a technique for effectively using cache memory from software. Blocking is a technology that divides the number of rotations of a multi-loop so that memory access to the array used in the innermost loop is within the size of the cache memory for the multi-loop processing structure existing in the source program. is there. When the compiler performs blocking optimization on the source program, the array data is always held in the cache memory, and the cache hit rate is improved.

  A blocking technique is known in which optimization is performed only for the innermost loop and the innermost loop outside the multiple loop to be optimized. In addition, there is known a blocking technique that optimizes only the innermost loop of a multiple loop including a three-dimensional array or more.

JP-A-5-265770

  In the conventional technique for optimizing multiple loops by blocking, it is not possible to apply blocking to three or more loops, and it is possible to apply blocking to multiple loops including arrays of three or more dimensions. There was a problem that I could not.

  In recent years, there has been a tendency for more sophisticated and complex scientific operations to be performed as hardware performance improves. In order to answer such needs, it is necessary to solve the above-mentioned problems of the prior art.

  The present invention is a technique for solving the above-described problems and enabling optimization by blocking over a wide range for loops of three or more loops and for multiple loops including arrays of three or more dimensions. The purpose is to provide.

  In the disclosed program, a compiler that compiles a source program written in a programming language causes a computer that performs optimization processing by blocking against multiple loops included in the source program to function as follows.

  That is, the program includes a procedure for extracting, as a blocking target loop, a loop having a structure having an executable statement only in the innermost loop from the multiple loops included in the source program on a computer on which the program is installed and executed. The procedure for extracting an array existing in a loop, and the order of control variables appearing as subscripts in the extracted array from the innermost loop of the blocking target loop to the outermost loop When there is a different sequence, the procedure for determining that blocking for the blocking target loop is effective and the blocking target loop for which blocking is determined to be effective are arranged within the range optimized by blocking for the blocking target loop. Memory used by Calculate the memory size used by all arrays in the blocking target loop within the range that is optimized by blocking for the blocking target loop from the calculation formula generated for each array Using the procedure for generating the calculation formula to be used and the calculation formula for calculating the memory size used by all arrays, the divided block length that does not cause a cache miss due to access to the array within the range optimized by blocking for the blocking loop is determined. A procedure for automatic calculation and a procedure for performing optimization by blocking the blocking target loop using the automatically calculated divided block length are executed.

  With the above technique, it is possible to perform optimization by blocking over a wide range without affecting the number of dimensions of the array included in the innermost loop for a loop of three or more layers. This improves the execution performance of the optimized program by improving the cache memory hit rate by applying blocking to loops that could not be optimized by blocking. .

It is a figure explaining the example of the conventional blocking with respect to a triple loop. It is a figure which shows the example of a memory access. It is a figure which shows the example of the optimization object loop after blocking at the time of blocking with respect to all the triple loops. It is a figure which shows the example of a memory access. It is a figure explaining the example of the conventional blocking with respect to the multiple loop containing a three-dimensional arrangement | sequence. It is a figure which shows the example of the optimization object loop after blocking when loops other than innermost loop are also blocked with respect to the multiple loop containing a three-dimensional arrangement | sequence. It is a figure which shows the function structural example of the compiler by this Embodiment. It is a figure which shows the hardware structural example of the computer by this Embodiment. It is a figure which shows the function structural example of the source analysis part by this Embodiment. It is a blocking optimization process flowchart by the optimization process part of this Embodiment. It is a figure which shows the example of the loop used as the object of the optimization by this Embodiment, and the loop after the optimization execution by blocking. It is a figure which shows the example of the data structure of the loop data by this Embodiment. It is a figure explaining the tight loop by this Embodiment. It is a process target loop analysis process flowchart by the process target loop analysis part of this Embodiment. It is a figure explaining management of arrangement data by this embodiment. It is a sequence analysis processing flowchart by the sequence analysis unit of the present embodiment. It is a figure explaining the access pattern by this Embodiment. It is a figure which shows the example which set the valid flag in the loop data by this Embodiment. It is an access pattern analysis process flowchart by the access pattern analysis part of this Embodiment. It is a subscript chain creation processing flowchart by the access pattern analysis unit of the present embodiment. It is a figure explaining the production | generation of the memory calculation formula classified by arrangement | sequence by this Embodiment. It is a figure explaining the production | generation of the memory size calculation formula from the memory calculation formula classified by arrangement | sequence by this Embodiment. It is a memory size calculation formula production | generation process flowchart by the memory size calculation formula production | generation part of this Embodiment. It is a memory calculation data generation processing flowchart according to arrangement | sequence by the memory size calculation formula production | generation part of this Embodiment. It is a figure explaining the example which calculates a division | segmentation block length automatically using the memory size calculation formula by this Embodiment. It is a divided block length calculation process flowchart by the divided block length calculation part of this Embodiment. It is a blocking instruction | indication processing flowchart by the blocking instruction | indication part by this Embodiment. This is an example in which the optimization by blocking of the present embodiment is executed for a loop of three or more layers. This is an example in which the optimization by blocking according to the present embodiment is performed on a multiple loop including an array of three or more dimensions. This is an example in which optimization by blocking according to the present embodiment is performed on a multiple loop including an optimization instruction line for blocking inhibition. This is an example in which the optimization by blocking according to the present embodiment is executed for a multiple loop including an optimization instruction line having a fixed divided block length.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  First, before describing the blocking technique according to the present embodiment, a conventional blocking technique will be briefly described.

  FIG. 1 is a diagram illustrating an example of conventional blocking for a triple loop.

  FIG. 1A shows an example of the optimization target loop. The optimization target loop shown in FIG. 1A is a triple loop of loop I, loop J, and loop K. In the optimization target loop shown in FIG. 1A, only the innermost loop includes an execution statement for an operation using a two-dimensional array.

  In this embodiment, the control variable is used as the name of the loop. Specifically, in the present embodiment, the loop of the control variable I is called a loop I.

  FIG. 1B shows the result of index exchange for the optimization target loop shown in FIG. An index is a control variable. The index exchange is a process of exchanging the inner loop and the outer loop so that access to the array is access to a continuous area in the memory. Since blocking is highly effective for memory access to the continuous area, if the memory access to the continuous area is caused by index exchange, it is necessary to exchange the index in advance. Details of the index exchange are described in paragraphs [0034] to [0043] of FIG.

  FIG. 1 (C) shows the result of performing conventional blocking on the optimization target loop after the index exchange shown in FIG. 1 (B). In the prior art, blocking is performed only for the innermost loop and the loop that is one outer side thereof, that is, only for the loop I and the loop J in the example shown in FIG. In the optimization target loop after blocking shown in FIG. 1C, an appropriate value is obtained for the divided block length block indicating the division unit of the loop by the blocking function of the compiler.

  FIG. 2 is a diagram illustrating an example of memory access.

  The example of memory access shown in FIG. 2 is an example of memory access in the optimization target loop after blocking shown in FIG. In FIG. 2, a thick line frame indicates a memory area in which data of each array is stored, and a thin line frame indicates an area whose one side is a divided block length block. In FIG. 2, the shaded area is when the control variables JJ and II are fixed and the loops I, J, and K are rotated in the optimization target loop after blocking shown in FIG. , Indicates the access area for each array included in the execution statement of the operation.

  As shown in FIG. 2, since the memory access is localized for the array A having the subscripts of the control variables I and J of the loop in which blocking is performed, the data is efficiently placed in the cache memory. be able to. However, since the memory access is not localized for the arrays B and C including the control variable K of the loop that has not been blocked as a subscript, data cannot be efficiently placed in the cache memory.

  In this way, with the conventional blocking technique, since it is not possible to block over three or more loops, the range of arrays in which data can be efficiently placed in the cache memory has been limited to a narrow range. .

  FIG. 3 is a diagram illustrating an example of an optimization target loop after blocking when blocking is performed on all triple loops.

  The example of the optimization target loop after blocking shown in FIG. 3 is the result of assuming that blocking is performed for all of the triple loops in the optimization target loop after index exchange shown in FIG. It is an example.

  For example, if the number of occurrences of control variables in each loop does not change much in the array subscripts included in the executable statement, better memory efficiency can be obtained by blocking all loops. There is a case.

  FIG. 4 is a diagram illustrating an example of memory access.

  The memory access example shown in FIG. 4 is an example of memory access in the optimization target loop after blocking shown in FIG. That is, the example of the memory access shown in FIG. 4 is an optimization after blocking when it is assumed that all the triple loops are blocked in the optimization target loop after the index exchange shown in FIG. It is an example of the memory access in an object loop.

  In FIG. 4, a thick line frame indicates a memory area in which data of each array is stored, and a thin line frame indicates an area whose one side is a divided block length block. In FIG. 2, the shaded area is when the control variables JJ, II, and KK are fixed and the loops I, J, and K are rotated in the optimization target loop after blocking shown in FIG. , Indicates the access area for each array included in the execution statement of the operation.

  As shown in FIG. 4, assuming that blocking is performed for all the triple loops, memory access is localized for all of the arrays A, B, and C. The cache memory can be loaded efficiently.

  If blocking for a loop of three or more loops as shown in FIG. 3 can be performed, a loop with higher memory efficiency can be optimized as compared with the conventional blocking technique.

  FIG. 5 is a diagram for explaining an example of conventional blocking for a multiple loop including a three-dimensional array.

  FIG. 5A shows an example of the optimization target loop. The optimization target loop shown in FIG. 5A is a triple loop of loop I, loop J, and loop K. In the optimization target loop shown in FIG. 5A, only the innermost loop includes an execution statement for an operation including a three-dimensional array.

  FIG. 5B shows the result of conventional blocking performed on the optimization target loop shown in FIG. In the conventional technique, when an array of three or more dimensions is used in the innermost loop, only the innermost loop, that is, only the loop I in the example shown in FIG. . However, in practice, blocking is also effective for the loop J that updates the control variable J.

  As described above, with the conventional blocking technique, it is only possible to block the innermost loop with respect to a multiple loop including a three-dimensional array. Therefore, the loop cannot be optimized very effectively.

  FIG. 6 is a diagram illustrating an example of an optimization target loop after blocking when a loop other than the innermost loop is also blocked with respect to a multiple loop including a three-dimensional array.

  The example of the optimization target loop after blocking shown in FIG. 6 is based on the assumption that blocking is performed on loop I and loop J in the optimization target loop including the three-dimensional array shown in FIG. This is an example of the result.

  As shown in FIG. 6, in a multiple loop including a three-dimensional array or more, loops other than the innermost loop are also subject to blocking, so that the loop with higher memory efficiency can be optimized. .

  In recent years, there has been a tendency for more sophisticated and complex scientific operations to be performed as hardware performance improves. In order to meet such needs, as shown in FIG. 3 and FIG. 6, the program can be expanded by broadening the blocking range even for multiple loops including three or more multiple loops and multiple loops including three-dimensional arrays. It is necessary to improve the execution performance.

  In the following, a blocking technique according to the present embodiment for solving the blocking problem with respect to multiple loops having three or more layers or multiple loops including three-dimensional or more arrays will be described.

  FIG. 7 is a diagram illustrating a functional configuration example of the compiler according to the present embodiment.

  In FIG. 7, the solid-line arrows mainly indicate the flow of control, and the broken-line arrows mainly indicate the data flow.

  The computer 1 includes a compiler 10, a storage unit 20, a linker 30, and an operating system 40. The operating system 40 provides basic functions that are commonly used by applications.

  The storage unit 20 is a storage device that can be accessed by the computer 1 and stores a source program 21, an object file 22, an execution file 23, and the like. The source program 21 is an application program described in a programming language such as Fortran. The object file 22 is an application object code file generated from the source program 21 by the compiler 10. The execution file 23 is an application executable program file in which the object file 22 and the library are linked by the linker 30.

  The compiler 10 compiles the source program 21 and generates an object file. The linker 30 links the object file 22 and the library, and generates an execution file 23.

  The compiler 10 includes a source program input unit 11, an input / output control unit 12, an intermediate language generation unit 13, an intermediate language storage unit 14, an optimization processing unit 15, a code generation unit 18, and an object file output unit 19.

  The source program input unit 11 opens a source program 21 in which compilation is specified. The input / output control unit 12 selects necessary processing according to the type of option and file.

  The intermediate language generation unit 13 converts the source program 21 into intermediate code used in the optimization process by the optimization processing unit 15 and stores it in the intermediate language storage unit 14. The intermediate language storage unit 14 is a storage device accessible by the computer 1 that stores the intermediate code converted from the source program 21 by the intermediate language generation unit 13. It is very difficult to perform the optimization process as it is on the source program 21 described in a high-level language. Therefore, the compiler 10 converts the source program 21 into an intermediate code that expresses the source program 21 with a data structure that can be easily optimized, and then performs optimization processing on the intermediate code.

  The optimization processing unit 15 performs optimization processing on the intermediate code stored in the intermediate language storage unit 14. The optimization processing unit 15 includes a source analysis unit 16 and an optimization execution unit 17. The source analysis unit 16 analyzes the intermediate code stored in the intermediate language storage unit 14, selects effective optimization, and instructs the optimization execution unit 17. The optimization execution unit 17 applies the instructed optimization to the intermediate code stored in the intermediate language storage unit 14.

  The code generation unit 18 generates assembler code from the optimized intermediate code. The object file output unit 19 generates an object file 22 from the assembler code.

  FIG. 8 is a diagram illustrating a hardware configuration example of a computer according to the present embodiment.

  The computer 1 includes hardware such as a central processing unit (CPU) 2, a memory 3 such as a random access memory (RAM) and a read only memory (ROM) 3, and a hard disk drive (HDD) 4. A part of the memory 3 is a cache memory that the CPU 2 can access at high speed. Further, an input device 5 such as a keyboard and a mouse 5 and a display device 6 such as a display are connected to the computer 1.

  Functions provided by the compiler 10, the storage unit 20, the linker 30, the operating system 40, and the like included in the computer 1 illustrated in FIG. 7 are realized by the hardware and software programs of the computer 1 illustrated in FIG.

  FIG. 9 is a diagram illustrating a functional configuration example of the source analysis unit according to the present embodiment.

  In the present embodiment, the source analysis unit 16 performs processing such as access pattern analysis, creation of a memory size calculation formula, and calculation of a divided block length as processing related to blocking that optimizes multiple loops. The optimization processing unit 15 propagates the information obtained by the source analysis unit 16 to the optimization execution unit 17, thereby executing optimization of the loop included in the source program 21, and executing the program generated by the compiler 10. Increase speed.

  The source analysis unit 16 analyzes the intermediate code stored in the intermediate language storage unit 14 as a process related to blocking for optimizing multiple loops, and automatically calculates a divided block length which is a unit of loop division by blocking. The intermediate language storage unit 14 stores loop data as intermediate code data relating to a loop included in the source program 21. The loop data storage unit 200 shown in FIG. 9 is a loop data storage area in the intermediate language storage unit 14.

  In the present embodiment, before the processing related to blocking by the optimization processing unit 15, index conversion for exchanging the inside and outside of the loop, loop division for transforming multiple loops including parallel loops into a serial nested structure, and the like. Assume that optimization has already been performed.

  The source analysis unit 16 includes, as functional units related to blocking, a processing target loop analysis unit 100, an array analysis unit 110, an access pattern analysis unit 120, a memory size calculation formula generation unit 130, a divided block length calculation unit 140, a blocking instruction unit 150, and the like. It has each functional part. The source analysis unit 16 includes storage units such as an array information storage unit 160, an array-specific memory calculation information storage unit 170, and a memory size calculation information storage unit 180. Each functional unit and each storage unit included in the source analysis unit 16 are realized by hardware such as the CPU 2, the memory 3, and the HDD 4 included in the computer 1, and a software program.

  The processing target loop analysis unit 100 extracts a loop having a tight structure from the loop to be optimized. Hereinafter, a loop to be optimized included in the source program 21 expressed by the intermediate code is referred to as an optimization target loop. A loop having a tight structure extracted from the optimization target loop by the processing target loop analysis unit 100 is referred to as a blocking target loop.

  The sequence analysis unit 110 analyzes the innermost loop of the blocking target loop and extracts a sequence existing in the blocking target loop. The sequence analysis unit 110 stores the sequence information extracted from the blocking target loop in the sequence information storage unit 160. The sequence information storage unit 160 is a storage device that can be accessed by a computer and stores sequence information extracted from the blocking target loop.

  The access pattern analysis unit 120 determines the order of the control variables appearing from the innermost loop toward the outermost loop in the blocking target loop, and the order of the control variables appearing in the subscripts of the array extracted from the blocking target loop. Analyze the relationship. When there is an array in which the order of the control variables appearing in the subscript is different from the order of the control variables appearing from the innermost loop toward the outermost loop, the access pattern analysis unit 120 performs blocking on the blocking target loop. It is determined that optimization is effective.

  The memory size calculation formula generation unit 130 generates, for each array in the blocking target loop, a calculation formula for calculating the memory size used by the array within a range optimized by blocking the blocking target loop. Hereinafter, a calculation formula for calculating a memory size used by an array within a range optimized by blocking is referred to as an array-specific memory calculation formula. The memory size calculation formula generation unit 130 stores the memory calculation formula information for each array in the memory calculation information storage unit 170 for each array. The array-based memory calculation information storage unit 170 is a computer-accessible storage device that stores information on the array-specific memory calculation formula.

  In addition, the memory size calculation formula generation unit 130 generates a calculation formula for calculating the memory size used by all the arrays in the blocking target loop within the range optimized by blocking the blocking target loop from the array-specific memory calculation formula. To do. Hereinafter, a calculation formula for calculating the memory size used by all the arrays in the blocking target loop within a range optimized by blocking is referred to as a memory size calculation formula. The memory size calculation formula generation unit 130 stores the memory size calculation formula information in the memory size calculation information storage unit 180. The memory size calculation information storage unit 180 is a computer-accessible storage device that stores information on a memory size calculation formula.

  The divided block length calculation unit 140 automatically calculates a divided block length that does not cause a cache miss due to access to the array, within a range optimized by blocking the blocking target loop, using a memory size calculation formula.

  The blocking instruction unit 150 issues an instruction for optimization by blocking the blocking target loop using the divided block length obtained by the divided block length calculation unit 140.

  The optimization execution unit 17 uses the divided block length obtained by the source analysis unit 16 to perform optimization by blocking on the blocking target loop. More specifically, the optimization execution unit 17 generates a loop for designating the number of divisions using the division block length obtained by the source analysis unit 16 outside the original blocking target loop. Deform the blocking loop.

  FIG. 10 is a flowchart of the blocking optimization process performed by the optimization processing unit according to this embodiment.

  In the source analysis unit 16 of the optimization processing unit 15, the processing target loop analysis unit 100 performs processing target loop analysis processing (step S1). The processing target loop analysis process is a process for extracting a loop having a tight structure from a loop to be optimized. Details of the processing target loop analysis processing will be described later.

  The sequence analysis unit 110 performs sequence analysis processing (step S2). The sequence analysis processing is processing for extracting a sequence existing in the blocking target loop. Details of the sequence analysis processing will be described later.

  The access pattern analysis unit 120 performs access pattern analysis processing (step S3). The access pattern analysis process determines whether the optimization for blocking is enabled or disabled based on the relationship between the order of appearance of control variables in the loop within the blocking target loop and the order of appearance of control variables in the array within the blocking target loop. This is a process of determining. Details of the access pattern analysis processing will be described later.

  The memory size calculation formula generation unit 130 performs a memory size calculation formula generation process (step S4). The memory size calculation formula generation process is a process for generating a calculation formula for calculating the memory size used by all the arrays in the blocking target loop within a range optimized by blocking the blocking target loop with respect to the blocking target loop. Details of the memory size calculation formula generation processing will be described later.

  The divided block length calculation unit 140 performs a divided block length calculation process (step S5). Divided block length calculation processing is a process of loops in the range optimized by blocking for the loop to be blocked using a memory size calculation formula, and automatically calculates the divided block length that does not cause cache misses due to access to the array. is there. Details of the division block length calculation processing will be described later.

  The blocking instruction unit 150 performs a blocking instruction process (step S6). The blocking instruction process is a process for instructing an optimization by blocking the blocking target loop using the obtained divided block length. Details of the blocking instruction process will be described later.

  The optimization execution unit 17 of the optimization processing unit 15 executes optimization by blocking the blocking target loop using the divided block length obtained by the source analysis unit 16 (step S7).

  Hereinafter, the processing of each functional unit related to blocking included in the source analysis unit 16 according to the present embodiment will be described using a specific example.

  FIG. 11 is a diagram illustrating an example of a loop to be optimized according to the present embodiment and a loop after execution of optimization by blocking.

  FIG. 11A shows an example of a loop to be optimized in the source program 21. Hereinafter, a loop to be optimized is referred to as an optimization target loop. The optimization target loop shown in FIG. 11A is a triple multiple loop having a three-dimensional array in the innermost loop.

  FIG. 11B shows an example of a loop after execution of optimization as a target when optimization by blocking of the present embodiment is executed on the optimization target loop shown in FIG. The loop after the optimization execution shown in FIG. 11B is the optimum by blocking using the divided block length block for all of the loops I, J, and K of the optimization target loop shown in FIG. Is in a state of being executed.

  As shown in FIG. 11B, in the loop after execution of optimization, the loop II, loop JJ, and loop KK that indicate the number of divisions using the divided block length block are the original loop I, loop J, and loop K. The original loop I, loop J, and loop K are transformed. In the loop after the optimization execution in FIG. 11B, the multiple loop composed of the inner loop I, loop J, and loop K becomes a loop in the range optimized by blocking. The source analysis unit 16 according to the present embodiment automatically calculates a divided block length block so that a cache miss does not occur due to access to the array in the processing in the loop optimized by blocking.

  Hereinafter, an example in which the source analysis unit 16 according to the present embodiment automatically calculates the divided block length block used in the optimization by blocking with respect to the optimization target loop shown in FIG. 11A will be described.

  The loop program shown in FIG. 11 is expressed in the form of the source program 21, but the actual optimization processing unit 15 performs processing on the loop program converted into the intermediate code.

  FIG. 12 is a diagram illustrating an example of a data structure of loop data according to the present embodiment.

  12 is an example of a data table in which a loop included in the source program 21 is converted into an intermediate code. The loop data 210k illustrated in FIG. 12 is the loop data 210 for the loop K of the optimization target loop illustrated in FIG. The loop data 210j shown in FIG. 12 is the loop data 210 for the loop J of the optimization target loop shown in FIG. The loop data 210i shown in FIG. 12 is the loop data 210 for the loop I of the optimization target loop shown in FIG.

  The loop data 210 shown in FIG. 12 includes information such as a loop name, prev (previous), next, array data, blocking flag, divided block length, and valid flag. The actual loop data 210 is data having an enormous amount of information regarding the loop. FIG. 12 shows only a part of the loop data 210 having a huge amount of information regarding the loop.

  The loop name in the loop data 210 shown in FIG. 12 indicates the name of the control variable whose value is updated in the loop.

  Prev in the loop data 210 shown in FIG. 12 indicates a pointer to the loop data 210 of the outer loop. In FIG. 12, for example, “* K” in prev of the loop data 210j represents a pointer to the loop data 210k of the loop K that is a loop outside the loop J. In FIG. 12, the prev of the loop data 210k of the loop K having no loop on the outside is “NULL”.

  Next in the loop data 210 shown in FIG. 12 indicates a pointer to the loop data 210 of the inner loop. For example, “* I” in the next of the loop data 210j represents a pointer to the loop data 210i of the loop I that is a loop inside the loop J. In FIG. 12, the next of the loop data 210i of the loop I having no loop on the inside is “NULL”.

  The array data in the loop data 210 shown in FIG. 12 indicates a pointer to array data that is information relating to the array existing in the innermost loop. The default of the array data of the loop data 210 is “NULL”. The sequence data in the loop data 210 is set by processing of the sequence analysis unit 110 described later.

  The blocking flag in the loop data 210 shown in FIG. In the present embodiment, it is also assumed that for each loop, the presence or absence of optimization by blocking can be externally instructed. In the present embodiment, “TRUE” is set in the blocking flag of the loop data 210 for a loop that has no particular instruction. For a loop whose blocking is suppressed by an optimization instruction line or the like, “FALSE” is set in the blocking flag of the loop data 210.

  The divided block length in the loop data 210 shown in FIG. 12 indicates the divided block length used for blocking. In this embodiment, it is assumed that a fixed division block length can be externally designated for each loop. In the present embodiment, “0” indicating that the divided block length used for blocking is automatically calculated is set as the divided block length of the loop data 210 for a loop that does not instruct a fixed divided block length. For a loop for which a fixed division block length is designated by an optimization instruction line or the like, the value designated for the division block length of the loop data 210 is set. For a loop in which the blocking flag of the loop data 210 is “FALSE”, “−1” indicating that blocking is not executed is set in the divided block length of the loop data 210.

  The valid flag in the loop data 210 shown in FIG. 12 indicates whether optimization by blocking is valid. The default valid flag of the loop data 210 is “NULL”. The valid flag of the loop data 210 is set by processing of the access pattern analysis unit 120 described later.

  An example of processing performed by the processing target loop analysis unit 100 according to the present embodiment will be described.

  The processing target loop analysis unit 100 first analyzes the nesting relationship of loops such as DO loops and FOR loops included in the program to find the innermost loop in the multiple loop. More specifically, the processing target loop analysis unit 100 traces the loop data 210 stored in the loop data storage unit 200 by tracing the next pointer sequentially from the outer loop, and the next loop is “NULL”. Find out. For example, in the optimization target loop shown in FIG. 11A, the processing target loop analysis unit 100 sequentially traces from the outermost loop K to the loop J and loop I, and sets the loop I having no child loop as the innermost loop. Extract.

  Next, the processing target loop analysis unit 100 extracts a range of loops having a tight structure while expanding the loops outward in order from the extracted innermost loop. The processing target loop analysis unit 100 sets the extracted loop range having a tight structure as a target loop to be optimized by blocking. In the following, the optimization target loop is called a blocking target loop.

  A tight structure in a loop is a structure in which loops are serially nested and an executable statement is included only in the innermost loop. In the present embodiment, a multiple loop having a tight structure is called a tight loop. When an executable statement is included between loops in the middle, the loop below the loop containing the executable statement is regarded as a tight loop.

  FIG. 13 is a diagram for explaining a tight loop according to the present embodiment.

  The loop shown in FIG. 13A is a double loop composed of a loop X and a loop Y. The loop shown in FIG. 13A has an execution statement for calculation only inside the innermost loop Y. That is, the multiple loop composed of the loop X and the loop Y is a tight loop.

  The loop shown in FIG. 13B is a double loop composed of a loop X and a loop Y. In the loop shown in FIG. 13B, an execution statement for the operation is included between the loop X and the loop Y. Therefore, the multiple loop composed of loop X and loop Y is not a tight loop.

  The loop shown in FIG. 13C is a triple loop including loop X, loop Y, and loop Z. In the loop shown in FIG. 13C, the execution statement of the operation is included between the loop X and the loop Y, and the multiple loop composed of the loop X, the loop Y, and the loop Z is not a tight loop. However, since an executable statement is not included between the loop Y and the loop Z, the multiple loop composed of the loop Y and the loop Z is a tight loop. The processing target loop analysis unit 100 extracts such a tight loop range.

  For example, in the optimization target loop shown in FIG. 11 (A), the execution amount of the calculation exists only inside the innermost loop I. The processing target loop analysis unit 100 extracts the loop K, loop J, and loop I from the optimization target loop shown in FIG. 11A as a tight loop and sets it as a blocking target loop. That is, the optimization target loop shown in FIG. 11A becomes a blocking target loop as it is.

  FIG. 14 is a processing target loop analysis processing flowchart by the processing target loop analysis unit of the present embodiment.

  The processing target loop analysis unit 100 extracts the innermost loop from the multiple loops to be processed (step S10). The processing target loop analysis unit 100 sets the extracted innermost loop as a tight outermost loop (step S11). The tight outermost loop here indicates the outermost loop among the loops that are confirmed to be tight at that time.

  The processing target loop analysis unit 100 determines whether there is a loop outside the current tight outermost loop (step S12).

  If there is a loop outside the current tight outermost loop (YES in step S12), the processing target loop analysis unit 100 determines that the multiple loop including the outer loop one of the current tight outermost loop is tight. It is determined whether the loop is correct (step S13).

  If the multiple loop including the loop outside the current tight outermost loop is a tight loop (YES in step S13), the processing target loop analysis unit 100 converts the tight outermost loop to the current tight outer loop. The loop is updated to the outermost loop of the outermost loop (step S14). The processing target loop analysis unit 100 returns to Step S12 and proceeds to the processing of the updated tight outermost loop.

  When there is no loop outside the current tight outermost loop (NO in step S12), the processing target loop analysis unit 100 sets the loop from the innermost loop to the tight outermost loop as a blocking target loop ( Step S15). If the multiple loop including the outer loop of the current tight outermost loop is not a tight loop (NO in step S13), the processing target loop analysis unit 100 performs a tight outermost loop from the innermost loop. The loop up to is set as a blocking target loop (step S15).

  Next, an example of processing by the sequence analysis unit 110 of this embodiment will be described.

  The sequence analysis unit 110 extracts the sequence used in the innermost loop of the blocking target loop extracted by the processing of the processing target loop analysis unit 100. At this time, the array analysis unit 110 lists all the arrays that update the memory 3 and the arrays that refer to the memory 3 by executing the operation.

  For example, in the blocking target loop of FIG. 11A, the following six sequences are extracted from the innermost loop.

Array A (I, J, K)
Array A (I, J, K)
Array B (J, K, I)
Array C (K, I, J)
Array D (I, X, J)
Array D (I, Y, J)
Among these, the array A (I, J, K) on the left side of the execution statement of the operation in the innermost loop is an array for updating the memory 3 by executing the operation, and the remaining 5 on the right side of the execution statement of the operation One array refers to the memory 3.

  When there are a plurality of sequences having the same sequence name and subscript among the extracted sequences, the sequence analysis unit 110 collectively regards these sequences as one sequence. All accesses to arrays with exactly the same array name and subscript are access to the same area on the memory 3. That is, the accessed memory 3 does not change regardless of how many times the array name and the subscript are accessed in the process within the blocking target loop. Therefore, in the procedure for calculating the memory size used by an array in a loop that has been optimized by blocking, which will be described later, even if there are multiple arrays with exactly the same array name and subscript, only one is calculated. It will be enough.

  For example, in FIG. 11A, the arrays extracted from the innermost loop include two arrays A (I, J, K). At this time, the sequence analysis unit 110 assumes that one sequence A (I, J, K) has been extracted.

  The sequence analysis unit 110 generates sequence data for each sequence extracted from the innermost loop. The sequence analysis unit 110 stores the generated sequence data in the sequence information storage unit 160 as sequence information extracted from the blocking target loop.

  FIG. 15 is a diagram for explaining management of array data according to the present embodiment.

The sequence data 165 shown in FIG. 15 is an example of the sequence data 165 extracted from the innermost loop in FIG. 11A by the sequence analysis unit 110. The array data 165a is array data of the array A (I, J, K). The array data 165b is array data of the array B (J, K, I). The array data 165c is array data of the array C (K, I, J). The array data 165d ₁ is array data of the array D (I, X, J). The array data 165d ₂ is array data of the array D (I, Y, J). As described above, the sequence analysis unit 110 generates the sequence data 165 by the number of the extracted sequences.

  The array data 165 shown in FIG. 15 has information such as an array name and a suffix for the corresponding array. In the array data 165, as many subscript fields as the number of dimensions of the array are prepared. That is, as shown in FIG. 15, in the case of array data 165 of a three-dimensional array, there are three subscript fields, subscript # 1, subscript # 2, and subscript # 3.

  As shown in FIG. 15, the sequence analysis unit 110 sets a pointer to the generated sequence data 165 in the sequence data field in the loop data 210 stored in the loop data storage unit 200. Here, it is assumed that a pointer to the generated array data 165 is set only for the loop data 210 of the innermost loop. For example, as shown in FIG. 15, pointers to five array data 165 are set in the array data field in the loop data 210i of the loop I which is the innermost loop of the blocking target loop.

  FIG. 16 is a flowchart of sequence analysis processing by the sequence analysis unit of this embodiment.

  The sequence analysis unit 110 selects one sequence existing in the innermost loop of the blocking target loop (step S20). The sequence analysis unit 110 acquires the sequence name of the selected sequence (step S21). The sequence analysis unit 110 acquires the number of dimensions of the selected sequence, that is, the number of subscripts (step S22), and the sequence analysis unit 110 acquires the subscripts of the selected sequence in the order of appearance (step S23).

  The sequence analysis unit 110 determines whether there is already sequence data 165 having a sequence name and a subscript that are exactly the same as the selected sequence (step S24). If there is not yet array data 165 of the array whose array name and subscript are exactly the same as the selected array (NO in step S24), the array analysis unit 110 generates array data 165 of the selected array. (Step S25). At this time, the array analysis unit 110 prepares array data 165 having subscript fields for the number of dimensions of the acquired array. The generated array data 165 is stored in the array information storage unit 160.

  The sequence analysis unit 110 determines whether the processing has been completed for all sequences existing in the innermost loop (step S26). If the processing has not yet been completed for all the arrays (NO in step S26), the array analysis unit 110 returns to step S20 and proceeds to processing for the next array. If the processing has been completed for all the arrays (YES in step S26), the array analysis unit 110 ends the processing.

  Next, an example of processing by the access pattern analysis unit 120 of this embodiment will be described.

  The access pattern analysis unit 120 analyzes the access pattern of the sequence extracted by the sequence analysis unit 110.

  The access pattern indicates a memory access pattern for the array. In the present embodiment, in memory access to an array, a pattern that sequentially accesses the memory 3 along the address is referred to as straight, and a pattern that accesses the memory 3 at intervals with an address interval is referred to as cross. The access pattern can be determined by the control variable appearing in the array subscript.

  FIG. 17 is a diagram for explaining an access pattern according to the present embodiment.

  In the multiple loop composed of loop K, loop J, and loop I shown in FIG. 17, when control variables K, J, and I are arranged in order of increasing tempo, control variables that appear from the innermost loop toward the outermost loop are displayed. In order, I → J → K. In this embodiment, an arrangement of control variables that appear in the order from the innermost loop to the outermost loop of the blocking target loop is called a chain of control variables.

  In the multiple loop shown in FIG. 17A, the array A (I, J, K) exists inside the innermost loop I. When the control variables used as subscripts of this array A (I, J, K) are arranged in the order of their appearing dimensions, I → J → K. In the present embodiment, in an array in the innermost loop of the blocking target loop, a control variable used as a subscript in the array in the order of appearance is called a subscript chain. Thus, an access pattern in which the subscript chain is the same as the control variable chain is straight.

  In the blocking target loop shown in FIG. 17B, as described above, the chain of control variables is I → J → K. The subscript chain of the array B (J, K, I) in the innermost loop is J → K → I. Thus, an access pattern of an array in which the subscript chain is different from the control variable chain is cross.

  The optimization by blocking is an optimization that improves the cache hit rate by localizing the access range to the memory 3 in the case where the memory access to the array is scattered not in the address order of the memory 3. . For this reason, even if the optimization by blocking is applied to a multiple loop in which the access pattern has only a straight array that sequentially accesses the memory 3, there is often no effect.

  Therefore, in this embodiment, the access pattern analysis unit 120 analyzes the access pattern of each array in the blocking target loop, thereby checking the effectiveness of applying the optimization by blocking to the blocking target loop. To do. The access pattern analysis unit 120 determines that the optimization by blocking for the blocking target loop is effective when the blocking target loop has an array of crosses in which the access pattern accesses the memory 3 point by point. .

  If the access pattern analysis unit 120 determines that the optimization by blocking for the blocking target loop is effective, the access pattern analysis unit 120 sets the effective flag in the loop data 210 of the innermost loop of the blocking target loop to “TRUE”.

  For example, as described above, the sequence analysis unit 110 extracts five sequences from the inside of the blocking target loop shown in FIG. 11A and creates five sequence data 165. The access pattern analysis unit 120 acquires the five array data 165 generated by the array analysis unit 110 from the array information storage unit 160, and creates a subscript chain for each array from the acquired array data 165.

  At this time, if there is a subscript whose value does not change in the blocking target loop, the access pattern analysis unit 120 omits the subscript and creates a subscript chain. Those whose values do not change in the blocking target loop are those other than the control variables of the loop included in the blocking target loop, such as a fixed value or a control variable of a loop outside the blocking target loop.

  The subscript chain for the five sequences extracted from the inside of the blocking target loop shown in FIG. 11A is as follows.

Array A (I, J, K): I → J → K
Array B (J, K, I): J → K → I
Array C (K, I, J): K → I → J
Array D (I, X, J): I → J
Array D (I, Y, J): I → J
The arrays D (I, X, J) and D (I, Y, J) are omitted from the chain of subscripts because X and Y are invariant values in the blocking target loop, respectively.

  Here, the loops included in the blocking target loop shown in FIG. 11A are loop I, loop J, and loop K in order from the inside. Therefore, the chain of control variables in the blocking target loop shown in FIG. 11A is I → J → K.

  When the chain of control variables in the blocking target loop shown in FIG. 11A is compared with the chain of subscripts of each array, the access pattern of each array is as follows.

Array A (I, J, K): Straight Array B (J, K, I): Cross Array C (K, I, J): Cross Array D (I, X, J): Straight Array D (I, Y) , J): Straight In this way, since the access patterns of the array B (J, K, I) and the array C (K, I, J) are crosses, the access pattern analysis unit 120 is shown in FIG. It is determined that optimization by blocking is effective for the blocking target loop shown.

  FIG. 18 is a diagram showing an example in which a valid flag is set in loop data according to the present embodiment.

  As shown in FIG. 18, the access pattern analysis unit 120 sets the validity flag in the loop data 210i of the innermost loop I for the blocking target loop shown in FIG. , “TRUE”.

  FIG. 19 is a flowchart of access pattern analysis processing by the access pattern analysis unit of the present embodiment.

  The access pattern analysis unit 120 initializes the valid flag in the loop data 210 of the innermost loop of the blocking target loop with “FALSE” indicating invalidity (step S30).

  The access pattern analysis unit 120 determines whether the blocking target loop is a multiple loop (step S31). If the blocking target loop is not a multiple loop (NO in step S31), the access pattern analysis unit 120 ends the process. When the blocking target loop is a single loop, there is often no effect even if the optimization by blocking is applied to the blocking target loop. In this embodiment, blocking is not performed on such a blocking target loop that is a single loop. In the processing of the processing target loop analysis unit 100 described above, when the tight loop is a single loop, it may be removed from the blocking target loop.

  If the blocking target loop is a multiple loop (YES in step S31), the access pattern analysis unit 120 creates a chain of control variables from the loop data 210 of the blocking target loop (step S32).

  The access pattern analysis unit 120 selects one sequence data 165 of the sequence in the innermost loop of the blocking target loop from the sequence information storage unit 160 (step S33). The access pattern analysis unit 120 performs a chain creation process for the subscript of the selected array data 165 (step S34). Subscript chain creation processing will be described later.

  The access pattern analysis unit 120 compares the chain of control variables with the chain of subscripts of the selected sequence data 165, and confirms the access pattern (step S35). If the access pattern is cross (cross in step S35), the access pattern analysis unit 120 sets “TRUE” indicating validity in the valid flag in the loop data 210 of the innermost loop of the blocking target loop (step S36). , Terminate the process.

  If the access pattern is straight (straight in step S35), the access pattern analysis unit 120 determines whether the processing has been completed for the array data 165 of all the arrays in the innermost loop of the blocking target loop (step S37). ). If the processing has not been completed for all the array data 165 (NO in step S37), the access pattern analysis unit 120 returns to step S33 and proceeds to the processing of the next array data 165. If the processing has been completed for all the array data 165 (YES in step S37), the access pattern analysis unit 120 ends the processing.

  FIG. 20 is a flowchart of subscript chain creation processing by the access pattern analysis unit of this embodiment.

  The access pattern analysis unit 120 acquires one subscript in the order of appearance from the array data 165 of the target sequence for creating a subscript chain (step S340). The access pattern analysis unit 120 determines whether the acquired subscript is a control variable of a loop included in the blocking target loop (step S341).

  If the acquired subscript is a control variable of a loop included in the blocking target loop (YES in step S341), the access pattern analysis unit 120 adds the acquired subscript to the subscript chain (step S342). .

  The access pattern analysis unit 120 determines whether processing has been completed for all subscripts in the array data 165 (step S343). If the processing has not been completed for all the subscripts (NO in step S343), the access pattern analysis unit 120 returns to step S340 and proceeds to the processing of the next subscript. If the processing has been completed for all the subscripts (YES in step S343), the access pattern analysis unit 120 ends the processing.

  Next, an example of processing by the memory size calculation formula generation unit 130 of this embodiment will be described.

  As a result of the determination by the access pattern analysis unit 120, the memory size calculation formula generation unit 130 generates a memory size calculation formula for the blocking target loop whose effective flag in the loop data 210 is “TRUE”. The memory size calculation formula is a calculation formula for calculating the memory size used by all the arrays in the blocking target loop within a range optimized by blocking the blocking target loop.

  For example, in the optimization target loop after blocking shown in FIG. 11B, loop K, loop J, and loop I are ranges optimized by blocking using the divided block length block. At this time, the memory size calculation formula is used by all the arrays in the innermost loop within a range in which only the loop K, loop J, and loop I in the optimization target loop after blocking shown in FIG. This is a calculation formula for calculating the memory size.

  The memory size calculation formula generation unit 130 generates a memory size calculation formula from the array-specific memory calculation formula generated for each array in the blocking target loop. The memory calculation formula for each array is a calculation formula for calculating the memory size used by each array within a range that is generated for each array and is optimized by blocking the blocking target loop.

  FIG. 21 is a diagram for explaining the generation of the memory calculation formula for each array according to the present embodiment.

  FIG. 21A shows a tight quadruple loop consisting of loop L, loop K, loop J, and loop I having a four-dimensional array A (I, J, K, L) inside the innermost loop I. An example is shown. Here, when optimization by blocking is performed on the quadruple loop shown in FIG. 21, the memory size used by the array A (I, J, K, L) is calculated within the range optimized by blocking. An example of generating a calculation formula is described.

  As shown in FIG. 21A, the array A (I, J, K, L) is declared that the type of the array is a real number, and the array A (I, J, K) , L) type size is 8 bytes. Further, the loop L is instructed not to execute blocking, and “FALSE” is set in the blocking flag in the loop data 210. Further, a fixed divided block length 20 is instructed to the loop J, and 20 is set in the divided block length field in the loop data 210. Since there is no specific instruction for the loop K and the loop I, 0 indicating automatic calculation is set in the field of the divided block length in the loop data 210.

  FIG. 21B shows an example of memory calculation data 175 for each array. The array-specific memory calculation data 175 is data representing an array-specific memory calculation formula in the present embodiment. The array-specific memory calculation data 175 has a variable part and a fixed part.

The variable part indicates a part where the memory size used by the array changes depending on the value of the automatically calculated divided block length in the memory calculation formula for each array. In the memory calculation data 175 for each array shown in FIG. 21B, n indicates the divided block length to be automatically calculated. In the array for generating the calculation formula, if the number of subscripts that are control variables of the loop that performs optimization with the automatically calculated divided block length is Z, the variable part of the array-specific memory calculation data 175 is represented by n ^Z. Is done. Here, Z is called an exponent part.

  The fixed portion indicates a portion where the memory size used by the array does not change depending on the value of the automatically calculated divided block length in the memory calculation formula for each array. The fixed part of the array-specific memory calculation data 175 includes the value of the type size of the array if the subscript does not include a loop control variable for which a fixed divided block length is specified in the array that generates the calculation formula. Become. Also, the fixed part of the array-specific memory calculation data 175 is the fixed block length if the subscript includes a loop control variable for which a fixed divided block length is specified in the array for generating the calculation formula. And the type size of the array.

  A subscript that is a control variable of a loop in which blocking is not executed is not included in the memory calculation for each array. In addition, subscripts whose values do not change in the blocking target loop are not affected by the optimization due to blocking, and are therefore ignored when generating memory formulas for each array.

For example, in the array A (I, J, K, L) in the multiple loop shown in FIG. 21A, a loop in which two subscripts I and K are optimized with the automatically calculated divided block length. Control variable. Therefore, the exponent part Z = 2, and the variable part in the memory calculation formula for each array is n ² . The subscript J is a control variable of a loop in which 20 is designated as a fixed divided block length. Since the type size of the array A is 8 bytes, the fixed part in the memory calculation formula for each array is 8 (array type size) × 20 (fixed divided block length) = 160. Note that the subscript L is a control variable of a loop in which it is specified that blocking is not executed, and thus is not included in the variable part or the fixed part in the memory calculation formula for each array.

In the memory calculation data 175 for each array, the calculation result of the fixed part is stored in the field indicating the calculation result of the variable part. That is, as shown in FIG. 21B, the calculation result 160 of the fixed part is stored in the field of the calculation result n ² of the variable part. In the memory calculation data 175 for each array, the initial value of the fixed part of each field is 0.

The memory calculation formula for each array represented by the memory calculation data for each array 175 shown in FIG.
(N ⁰ × 0) + (n ¹ × 0) + (n ² × 160) + (n ³ × 0) + (n ⁴ × 0)
= 160n ²
It becomes. This array memory calculation formula 160n ² is an array A (I, J, K, L) in the case where optimization by blocking using the divided block length n is performed on the multiple loop shown in FIG. Is a calculation formula for calculating the memory size used.

  FIG. 22 is a diagram for explaining generation of a memory size calculation formula from an array-specific memory calculation formula according to the present embodiment.

  The memory size calculation formula generation unit 130 stores each array data 165 stored in the array information storage unit 160 and each loop data storage unit 200 for each array extracted from the blocking target loop shown in FIG. Using each loop data 210, an array-specific memory calculation formula is generated.

  Here, it is assumed that the real type is declared as the array type for all of the arrays A, B, C, and D, and the type size of all the arrays is 8 bytes.

For array A (I, J, K), array B (J, K, I), and array C (K, I, J), all subscripts are control variables for the loops included in the blocking target loop. The variable part of the memory calculation formula for each array is n ³ . Further, since there is no loop for which a fixed divided block length is instructed in the blocking target loop, the fixed part of the memory calculation formula for each array is 8 only in the array type size. Note that all blocking flags in the loop data 210 of each loop included in the blocking target loop are “TRUE”. Therefore, the array-specific memory calculation formulas for array A (I, J, K), array B (J, K, I), and array C (K, I, J) are all 8n ³ .

For array D (I, X, J) and array D (I, Y, J), subscript X and subscript Y are not control variables of the loop included in the blocking target loop, but are in the blocking target loop, respectively. It becomes an invariant value. Since subscript I and subscript J are control variables of the loop included in the blocking target loop, the variable part of the memory calculation formula for each array is n ² . Further, since there is no loop for which a fixed divided block length is instructed in the blocking target loop, the fixed part of the memory calculation formula for each array is 8 only in the array type size. Therefore, the memory calculation formula for each of the arrays D (I, X, J) and D (I, Y, J) is 8n ² .

The array-specific memory calculation data 175 representing the array-specific memory calculation formula generated for each array is as shown in FIG. The array-specific memory calculation data 175a is data representing an array-specific memory calculation formula for calculating the memory size used by the array A (I, J, K). The array-specific memory calculation data 175b is data representing an array-specific memory calculation formula for calculating the memory size used by the array B (J, K, I). The array-specific memory calculation data 175c is data representing an array-specific memory calculation formula for calculating the memory size used by the array C (K, I, J). The array-specific memory calculation data 175d ₁ is data representing an array-specific memory calculation formula for calculating the memory size used by the array D (I, X, J). The array-specific memory calculation data 175d ₂ is data representing an array-specific memory calculation formula for calculating the memory size used by the array D (I, Y, J). The memory size calculation formula generation unit 130 stores the generated memory calculation data 175 for each array in the memory calculation information storage unit 170 for each array.

  Next, the memory size calculation formula generation unit 130 generates a memory size calculation formula for calculating the memory size used by all the arrays from the array-specific memory calculation formula for each array. The memory size calculation formula is obtained by adding all the memory calculation formulas for each array generated for each array.

  In FIG. 22, memory size calculation data 185 is data representing a memory size calculation formula. The data structure of the memory size calculation data 185 is the same as the data structure of the memory calculation data 175 for each array.

  As shown in FIG. 22, the memory size calculation formula generation unit 130 merges the fixed portion of the memory calculation data 175 for each array stored in the memory calculation information storage unit 170 for each array on the memory size calculation data 185. To do. In the memory size calculation data 185, the initial value of the fixed part of each field is 0.

  As described above, the memory size calculation formula generation unit 130 generates the memory size calculation data 185 shown in FIG. 22 as data representing the calculation formula for calculating the memory size used by all the arrays in the blocking target loop shown in FIG. Is done. The memory size calculation formula generation unit 130 stores the generated memory size calculation data 185 in the memory size calculation information storage unit 180.

The memory size calculation formula represented by the memory size calculation data 185 shown in FIG.
(N ⁰ × 0) + (n ¹ × 0) + (n ² × 16) + (n ³ × 24)
= 16n ² + 24n ³
It becomes. Since the unit of the array type size is calculated in bytes, the unit of size obtained by this memory size calculation formula is bytes.

  FIG. 23 is a flowchart of a memory size calculation formula generation process by the memory size calculation formula generation unit of the present embodiment.

  The memory size calculation formula generation unit 130 selects one array data 165 of the array extracted from the blocking target loop stored in the array information storage unit 160 (step S40). The memory size calculation formula generation unit 130 performs an array-specific memory calculation data generation process for the selected array data 165 (step S41). Details of the memory calculation data generation processing for each array will be described later.

  The memory size calculation formula generation unit 130 determines whether the processing has been completed for the array data 165 of all the arrays extracted from within the blocking target loop (step S42). If the processing has not been completed for all the array data 165 of the arrays (NO in step S42), the memory size calculation formula generation unit 130 returns to step S40 and proceeds to the processing of the array data 165 of the next array.

  If processing has been completed for array data 165 of all arrays (YES in step S42), the memory size calculation formula generation unit 130 stores values from all the generated memory calculation data 175 for each array in a fixed part. The value of the maximum exponent part in the obtained variable part is acquired (step S43). The memory size calculation formula generation unit 130 generates memory size calculation data 185 in which the exponent part has a variable part field from 0 to the maximum exponent part acquired (step S44).

  The memory size calculation formula generation unit 130 selects one array-specific memory calculation data 175 (step S45). The memory size calculation formula generation unit 130 merges the selected array-specific memory calculation data 175 with the memory size calculation data 185 (step S46).

  The memory size calculation formula generation unit 130 determines whether the processing has been completed for all the generated array-based memory calculation data 175 (step S47). If the processing has not been completed for all the array-specific memory calculation data 175 (NO in step S47), the memory size calculation formula generation unit 130 returns to step S45 and proceeds to the processing of the next array-specific memory calculation data 175. . If the processing has been completed for all the array-specific memory calculation data 175 (YES in step S47), the memory size calculation formula generation unit 130 ends the processing.

  FIG. 24 is a memory calculation data generation processing flowchart for each array by the memory size calculation formula generation unit of this embodiment.

  The memory size calculation formula generation unit 130 initializes a to 1 and Z to 0 (step S410).

  The memory size calculation formula generation unit 130 selects one subscript from the array data 165 (step S411).

  The memory size calculation formula generation unit 130 refers to the loop data 210 of the blocking target loop stored in the loop data storage unit 200 and determines whether the selected subscript is a control variable of a loop included in the blocking target loop. (Step S412). If the selected subscript is not a control variable (NO in step S412), the memory size calculation formula generation unit 130 proceeds to the process of step S417.

  If the selected subscript is a control variable (YES in step S412), the memory size calculation formula generation unit 130 indicates that the blocking flag in the loop data 210 of the loop having the selected subscript as a control variable is “TRUE”. It is determined whether or not there is (step S413). If the blocking flag is not “TRUE” (NO in step S413), the memory size calculation formula generation unit 130 proceeds to the process in step S417.

  If the blocking flag is “TRUE” (YES in step S413), the memory size calculation formula generation unit 130 sets the divided block length fixed to the divided block length in the loop data 210 of the loop using the selected subscript as a control variable. Is set (step S414). If a fixed division block length is set (YES in step S414), the memory size calculation formula generation unit 130 updates the value of a with a value of a designated division block length (step S415). ). If the fixed divided block length is not specified (NO in step S414), the memory size calculation formula generation unit 130 increments the value of Z (step S416).

  The memory size calculation formula generation unit 130 determines whether the processing has been completed for all subscripts of the array data 165 (step S417). If the processing has not been completed for all the subscripts (NO in step S417), the memory size calculation formula generation unit 130 returns to step S411 and proceeds to the processing of the next subscript.

If the processing has been completed for all the subscripts (YES in step S417), the memory size calculation formula generation unit 130 acquires the array type size b (step S418). The memory size calculation formula generation unit 130 calculates c = a × b (step S419). The memory size calculation formula generation unit 130 sets the calculated c to the fixed part of the field whose variable part of the array-specific memory calculation data 175 is n ^Z (step S420).

  Next, an example of processing performed by the divided block length calculation unit 140 according to the present embodiment will be described.

  The divided block length calculation unit 140 inputs the divided block length to the memory size calculation formula generated by the memory size calculation formula generation unit 130 and calculates the memory size. At this time, the divided block length calculation unit 140 gradually increases the divided block length input to the memory size calculation formula from a small value and the obtained memory size does not exceed the size of the cache memory. Find the length.

  FIG. 25 is a diagram illustrating an example in which the divided block length is automatically calculated using the memory size calculation formula according to this embodiment.

25, the memory size calculation data 185 is the memory size calculation data 185 shown in FIG. 22 generated based on the blocking target loop shown in FIG. That is, the memory size calculation data 185 shown in FIG. 25 is the memory size calculation data 185 representing the memory size calculation formula 16n ² + 24n ³ .

  In FIG. 25, the cache size indicates the size of the primary cache memory in the hierarchical memory 3 provided in the computer 1. Here, it is assumed that the cache size is 131072 bytes.

  The divided block length calculation unit 140 inputs a value assumed as the divided block length to n of the memory size calculation data 185, and calculates the memory size. The divided block length calculation unit 140 compares the calculated memory size with the cache size, and checks whether the memory size exceeds the cache size.

  The value that is input to the memory size calculation data 185 on the assumption that the divided block length is arbitrary. In this embodiment, it is assumed that a multiple of 8 is input to the memory size calculation data 185 in consideration of cache lines and alignment. In FIG. 25, as a result of comparison between the calculated memory size and the cache size, “◯” is described when the memory size is equal to or smaller than the cache size, and “X” is described when the memory size exceeds the cache size. Yes.

  First, the divided block length calculation unit 140 inputs 8 as the divided block length to n of the memory size calculation data 185. At this time, the memory size obtained from the memory size calculation data 185 is 13312 bytes. Since the calculated memory size is equal to or smaller than the cache size, the comparison result is ◯.

  Next, the divided block length calculation unit 140 inputs 16 as the divided block length to n of the memory size calculation data 185. At this time, the memory size obtained from the memory size calculation data 185 is 102400 bytes. Since the calculated memory size is equal to or smaller than the cache size, the comparison result is ◯.

  Next, the divided block length calculation unit 140 inputs 24 as the divided block length to n of the memory size calculation data 185. At this time, the memory size obtained from the memory size calculation data 185 is 340992 bytes. Since the calculated memory size exceeds the cache size, the comparison result is x.

  The divided block length calculation unit 140 uses the input value 16 from which the maximum memory size not exceeding the cache size is obtained in the optimization by blocking for the blocking target loop shown in FIG. Determine as long.

  FIG. 26 is a divided block length calculation processing flowchart by the divided block length calculation unit of the present embodiment.

  The divided block length calculation unit 140 sets the value of the divided block length to −1 (step S50). The divided block length calculation unit 140 saves the divided block length set to −1 in the save area on the memory 3 (step S51). The processing so far is processing for initializing the value of the divided block length input to the memory size calculation data 185. When the memory size obtained by inputting the first divided block length to the memory size calculation data 185 exceeds the cache size, blocking using the automatically calculated block length for the blocking target loop is not performed. . Therefore, −1 indicating that optimization by blocking is not executed is set as the initial value of the divided block length.

  The divided block length calculation unit 140 sets the first input value as the divided block length (step S52). The divided block length calculation unit 140 makes an inquiry to the operating system 40 and acquires the cache size (step S53).

  The divided block length calculation unit 140 inputs the divided block length to the memory size calculation data 185 and calculates the memory size (step S54). The divided block length calculation unit 140 determines whether the calculated memory size exceeds the acquired cache size (step S55).

  If the memory size does not exceed the cache size (NO in step S55), the divided block length calculation unit 140 saves the value of the divided block length in the save area on the memory 3 (step S56). In this process, the divided block length previously saved in the save area is updated. The divided block length calculation unit 140 increases the value of the divided block length input to the memory size calculation data 185 (step S57), returns to step S54, and proceeds to processing of the increased divided block length.

  If the memory size exceeds the cache size (YES in step S55), the divided block length calculation unit 140 uses the value saved in the save area of the memory 3 at that time as the automatically calculated divided block length value. (Step S58), and the process ends.

  Next, an example of processing by the blocking instruction unit 150 of the present embodiment will be described.

  The blocking instruction unit 150 instructs optimization execution by blocking using the divided block length determined by the divided block length calculation unit 140. More specifically, the blocking instruction unit 150 sets the automatically calculated division block length value for the division block length in each loop data 210 of the blocking target loop stored in the loop data storage unit 200. At this time, the blocking instruction unit 150 sets the automatically calculated divided block length only for those in which 0 indicating automatic calculation is set as the divided block length in the loop data 210.

  For example, in the present embodiment, the blocking instruction unit 150 sets the divided block length value 16 determined in the example shown in FIG. 25 to the divided block length in each loop data 210 of the blocking target loop shown in FIG. Set.

  FIG. 27 is a flowchart of a blocking instruction process by the blocking instruction unit according to this embodiment.

  The blocking instruction unit 150 selects one loop data 210 of the loop included in the blocking target loop stored in the loop data storage unit 200 (step S60).

  The blocking instruction unit 150 determines whether the blocking flag in the selected loop data 210 is “TRUE” (step S61). Further, the blocking instruction unit 150 determines whether a fixed divided block length is set as the divided block length in the selected loop data 210 (step S62).

  When the blocking flag is “TRUE” (YES in step S61) and a fixed divided block length is not set as the divided block length (NO in step S62), the blocking instruction unit 150 selects the selected loop. The value of the automatically calculated divided block length is set as the divided block length of the data 210 (step S63).

  The blocking instruction unit 150 determines whether the processing has been completed for all the loop data 210 of the loop included in the blocking target loop (step S64). If the processing has not been completed for all the loop data 210 (NO in step S64), the blocking instruction unit 150 returns to step S60 and proceeds to the processing of the next loop data 210. If the processing has been completed for all the loop data 210 (YES in step S64), the blocking instruction unit 150 ends the processing.

  The optimization execution unit 17 performs optimization by blocking the blocking target loop using the value of the divided block length in the loop data 210 stored in the loop data storage unit 200 as a part of the intermediate code.

  Hereinafter, some specific examples of optimization by blocking according to the present embodiment will be described with reference to FIGS. 28 to 31.

  FIG. 28 shows an example in which the optimization by blocking according to the present embodiment is executed for a loop of three or more layers.

  The optimization target loop shown in FIG. 28 includes a loop K, a loop J, and a loop I. Since the optimization target loop shown in FIG. 28 is a tight loop having an execution statement for computation only in the innermost loop I, the processing target loop analysis unit 100 blocks the optimization target loop shown in FIG. 28 as it is. The target loop. The sequence analysis unit 110 extracts three sequences. Since the access pattern of the extracted array C (K, J) is a cross, the access pattern analysis unit 120 determines that the optimization by blocking for the optimization target loop shown in FIG. 28 is effective.

The extracted three array types are all declared as real (the array type size is 8 bytes). In addition, the three arrays are two-dimensional arrays in which the control variables of the loops included in the blocking target loop are used as subscripts. The memory size calculation formula generation unit 130 generates a memory size calculation formula 24n ² .

It is assumed that 131072 bytes are acquired as the cache size. The divided block length calculation unit 140 sequentially inputs multiples of 8 from the smallest value to the memory size calculation formula 24n ² . The divided block length calculation unit 140 determines the maximum n that the memory size obtained from the memory size calculation formula 24n ² does not exceed the cache size as the automatically calculated divided block length. Here, the memory size of 124416 bytes obtained when n = 72 is the maximum memory size that does not exceed the cache size.

  The blocking instruction unit 150 instructs the optimization execution unit 17 to use the obtained value 72 as the automatically calculated divided block length. The optimization execution unit 17 executes optimization by blocking on the optimization target loop shown in FIG. 28 using the automatically calculated divided block length block = 72. The post-blocking loop shown in FIG. 28 is obtained as an execution result of the optimization by blocking the optimization target loop shown in FIG.

  As described above, the optimization by blocking according to the present embodiment enables optimization by blocking with respect to three or more loops.

  FIG. 29 shows an example in which the optimization by blocking according to the present embodiment is performed on a multiple loop including a three-dimensional array or more.

  The optimization target loop shown in FIG. 29 includes a loop K, a loop J, and a loop I. Since the optimization target loop shown in FIG. 29 is a tight loop having an execution statement of an operation having a three-dimensional array only in the innermost loop I, the processing target loop analysis unit 100 is shown in FIG. The optimization target loop is directly used as a blocking target loop. The sequence analysis unit 110 extracts five sequences. Since the access pattern of the extracted array B (J, K, I) is a cross, the access pattern analysis unit 120 determines that optimization by blocking for the optimization target loop shown in FIG. 29 is effective.

The extracted five array types are all declared as real (the array type size is 8 bytes). In addition, three of the five arrays are three-dimensional arrays that have subscripts as control variables of the loops included in the blocking target loop. Two of the five arrays are three-dimensional arrays including one subscript that is not a control variable of a loop included in the blocking target loop. The memory size calculation formula generation unit 130 generates a memory size calculation formula 16n ² + 24n ³ .

It is assumed that 131072 bytes are acquired as the cache size. The divided block length calculation unit 140 sequentially inputs multiples of 8 from the smallest value to the memory size calculation formula 16n ² + 24n ³ . The divided block length calculation unit 140 determines, as the automatically calculated divided block length, the maximum n that the memory size obtained from the memory size calculation formula 16n ² + 24n ³ does not exceed the cache size. Here, the memory size of 102400 bytes obtained when n = 16 is the maximum memory size that does not exceed the cache size.

  The blocking instruction unit 150 instructs the optimization execution unit 17 to set the obtained value 16 as the automatically calculated divided block length. The optimization execution unit 17 executes optimization by blocking the optimization target loop shown in FIG. 29 using the automatically calculated divided block length block = 16. The post-blocking loop shown in FIG. 29 is obtained as an execution result of the optimization by blocking on the optimization target loop shown in FIG.

  As described above, the optimization by blocking according to the present embodiment enables the optimization by blocking with respect to multiple loops including arrays of three or more dimensions.

  FIG. 30 shows an example in which the optimization by blocking according to the present embodiment is executed for a multiple loop including an optimization instruction line for blocking inhibition.

  The optimization target loop shown in FIG. 30 includes a loop K, a loop J, and a loop I. Since the optimization target loop shown in FIG. 30 is a tight loop having an execution statement of an operation having a two-dimensional array only in the innermost loop I, the processing target loop analysis unit 100 is shown in FIG. The optimization target loop is directly used as a blocking target loop. The sequence analysis unit 110 extracts three sequences. Since the access pattern of the extracted array C (K, J) is a cross, the access pattern analysis unit 120 determines that the optimization by blocking for the optimization target loop shown in FIG. 30 is effective.

The extracted three array types are all declared as real (the array type size is 8 bytes). Further, the optimization target loop shown in FIG. 30 includes an optimization instruction line for blocking suppression for the loop J. One of the three arrays is a two-dimensional array in which all of the control variables of the loop included in the blocking target loop are not subscripted and are subscripts. Two of the three arrays are two-dimensional arrays that contain one control variable for the loop that is subject to blocking suppression, and that are subscripted from the control variables for the loops that are all included in the blocking target loop. . The memory size calculation formula generation unit 130 generates a memory size calculation formula 8n ² + 16n.

It is assumed that 131072 bytes are acquired as the cache size. The divided block length calculation unit 140 inputs multiples of 8 in order from the smallest value to the memory size calculation formula 8n ² + 16n. The divided block length calculation unit 140 determines, as the automatically calculated divided block length, the maximum n that the memory size obtained from the memory size calculation formula 8n ² + 16n does not exceed the cache size. Here, the memory size 117120 bytes obtained when n = 120 is the maximum memory size that does not exceed the cache size.

  The blocking instruction unit 150 instructs the optimization execution unit 17 to use the obtained value 120 as the automatically calculated divided block length. The optimization execution unit 17 executes optimization by blocking on the optimization target loop shown in FIG. 30 using the automatically calculated divided block length block = 120. At this time, the optimization execution unit 17 does not execute the optimization by blocking the loop J that is the object of blocking inhibition. A post-blocking loop shown in FIG. 30 is obtained as a result of execution of optimization by blocking the optimization target loop shown in FIG.

  As described above, the optimization by blocking of the optimization target loop can be performed except for the loop for which blocking suppression is instructed in advance by the optimization technique by blocking according to the present embodiment.

  FIG. 31 shows an example in which the optimization by blocking according to the present embodiment is performed on a multiple loop including an optimization instruction line having a fixed divided block length.

  The optimization target loop shown in FIG. 31 includes a loop K, a loop J, and a loop I. Since the optimization target loop shown in FIG. 31 is a tight loop having an execution statement of an operation having a two-dimensional array only in the innermost loop I, the processing target loop analysis unit 100 is shown in FIG. The optimization target loop is directly used as a blocking target loop. The sequence analysis unit 110 extracts three sequences. Since the access pattern of the extracted array C (K, J) is a cross, the access pattern analysis unit 120 determines that the optimization by blocking for the optimization target loop shown in FIG. 31 is effective.

The extracted three array types are all declared as real (the array type size is 8 bytes). Further, the optimization target loop shown in FIG. 31 includes an optimization instruction row instructing a fixed divided block length (value 48) for the loop J. One of the three arrays is a two-dimensional array in which a fixed variable block length is not specified and the control variable of the loop included in the blocking target loop is used as a subscript. Two of the three arrays are two-dimensional arrays that contain one control variable for the loop for which a fixed division block length is specified and that are subscripted from the control variables for the loops that are all included in the blocking target loop. is there. The memory size calculation formula generation unit 130 generates a memory size calculation formula 8n ² + 768n.

It is assumed that 131072 bytes are acquired as the cache size. The divided block length calculation unit 140 sequentially inputs multiples of 8 from the smallest value to the memory size calculation formula 8n ² + 768n. The divided block length calculation unit 140 determines, as the automatically calculated divided block length, the maximum n that the memory size obtained from the memory size calculation formula 8n ² + 768n does not exceed the cache size. Here, the memory size 129536 bytes obtained when n = 88 is the maximum memory size that does not exceed the cache size.

  The blocking instruction unit 150 instructs the optimization execution unit 17 to use the obtained value 88 as the automatically calculated divided block length. The optimization execution unit 17 executes optimization by blocking on the optimization target loop shown in FIG. 31 using the automatically calculated divided block length block = 88. At this time, the optimization execution unit 17 executes the optimization by blocking for the loop J for which the fixed division block length is instructed, using the value 48 of the instructed fixed division block length. As a result of execution of optimization by blocking the optimization target loop shown in FIG. 31, a post-blocking loop shown in FIG. 31 is obtained.

  As described above, by using the optimization technique based on blocking according to the present embodiment, the fixed division block length is used in advance for the loop, and the automatically calculated division block length is used for other loops. Therefore, it is possible to optimize the loop to be optimized by blocking.

  The processing by the optimization processing unit 15 of the present embodiment described above can be realized by hardware such as CPU and memory provided in the computer and a software program, and the program is recorded on a computer-readable recording medium. It can also be provided through a network.

  Although the present embodiment has been described above, the present invention can naturally be modified in various ways within the scope of the gist thereof.

1 Computer 2 CPU
3 Memory 4 HDD
DESCRIPTION OF SYMBOLS 5 Input device 6 Display apparatus 10 Compiler 11 Source program input part 12 Input / output control part 13 Intermediate language production | generation part 14 Intermediate language memory | storage part 200 Loop data memory | storage part 15 Optimization processing part 16 Source analysis part 100 Processing object loop analysis part 110 Array Analysis unit 120 Access pattern analysis unit 130 Memory size calculation formula generation unit 140 Division block length calculation unit 150 Blocking instruction unit 160 Array information storage unit 170 Memory calculation information storage unit by array 180 Memory size calculation information storage unit 17 Optimization execution unit 18 Code generation unit 19 Object file output unit 20 Storage unit 21 Source program 22 Object file 23 Execution file 30 Linker 40 Operating system

Claims (5)

In a compiler for compiling a source program written in a programming language, a program for causing a computer to perform optimization processing by blocking multiple loops included in the source program,
In the computer,
A procedure for extracting, from the multiple loops included in the source program, a loop having a structure having an executable statement only in the innermost loop as a blocking target loop;
Extracting a sequence present in the blocking loop;
In the extracted array, if there is an array in which the order of control variables appearing as subscripts is different from the order of control variables appearing from the innermost loop to the outermost loop of the blocking target loop, A procedure for determining that blocking for the blocking target loop is effective;
A procedure for generating, for each array, a calculation formula for calculating a memory size used by the array in a range optimized by blocking with respect to the blocking target loop for the blocking target loop determined to be effective.
Generating a calculation formula for calculating a memory size used by all the arrays in the blocking target loop from a calculation formula generated for each array in a range optimized by blocking with respect to the blocking target loop;
A procedure for automatically calculating a divided block length in which a cache miss does not occur due to access to an array within a range optimized by blocking for the blocking target loop, using a calculation formula for calculating a memory size used by all the arrays;
An optimization processing program for executing a procedure for performing optimization by blocking on the blocking target loop using the automatically calculated divided block length. In the procedure for generating the calculation formula for each array, the blocking target loop that is determined to be effective for blocking is optimized by blocking the blocking target loop except the loop instructed not to execute blocking. Generate a calculation formula for each array to calculate the memory size used by the array
In the procedure for performing the optimization by blocking, using the automatically calculated divided block length, the loop instructed not to execute the blocking is excluded, and the blocking target loop is optimized by the blocking. The optimization processing program according to claim 1, wherein: In the procedure for generating the calculation formula for each array, the blocking target loop that is determined to be effective for blocking is optimized by blocking the blocking target loop including a loop in which a fixed division block length is indicated. Generate a calculation formula for each array to calculate the memory size used by the array in the range,
In the procedure for performing the optimization by blocking, for the loop designated by the fixed divided block length included in the loop to be blocked, optimization by blocking is performed using the designated fixed block length. The optimization by blocking is performed using the automatically calculated divided block length for a loop in which the fixed divided block length included in the blocking target loop is not specified. Alternatively, the optimization processing program according to claim 2. In a compiler for compiling a source program described in a programming language, an optimization processing device that executes optimization processing by blocking against multiple loops included in the source program,
A processing target loop analysis unit that extracts a loop having an executable statement only in the innermost loop as a blocking target loop from the multiple loops included in the source program;
A sequence analysis unit for extracting a sequence existing in the blocking target loop;
In the extracted array, if there is an array in which the order of control variables appearing as subscripts is different from the order of control variables appearing from the innermost loop to the outermost loop of the blocking target loop, An access pattern analyzer that determines that blocking is effective for the blocking loop;
For each of the arrays for which the blocking is determined to be effective, a calculation formula for calculating the memory size used by the array within a range optimized by the blocking for the blocking target loop is generated for each array. A memory size calculation formula generation unit that generates a calculation formula for calculating a memory size used by all the arrays in the blocking target loop within a range optimized by blocking with respect to the blocking target loop, from the calculation formula generated for each block; ,
Divided block length that automatically calculates a divided block length that does not cause a cache miss due to access to the array within a range optimized by blocking for the blocking target loop, using a calculation formula that calculates the memory size used by the entire array A calculation unit;
An optimization processing device comprising: an optimization execution unit that performs optimization by blocking the blocking target loop using the automatically calculated divided block length. In a compiler that compiles a source program written in a programming language, an optimization processing method in which a computer executes optimization processing by blocking against multiple loops included in the source program,
The computer is
Extracting a loop having a structure having an executable statement only in the innermost loop as a blocking target loop from multiple loops included in the source program;
Extracting a sequence present in the blocking loop;
When there is an array in the extracted array in which the order of control variables appearing as subscripts is different from the order of control variables appearing from the innermost loop to the outermost loop of the blocking target loop, A process for determining that blocking is effective for a blocking target loop;
A step of generating, for each array, a calculation formula for calculating a memory size used by the array within a range optimized by blocking with respect to the blocking target loop for the blocking target loop determined to be effective;
Generating a calculation formula for calculating a memory size used by all the arrays in the blocking target loop from a calculation formula generated for each array in a range optimized by blocking with respect to the blocking target loop;
A process of automatically calculating a divided block length in which a cache miss does not occur due to an access to an array within a range optimized by blocking for the blocking target loop, using a calculation formula for calculating a memory size used by the entire array;
The optimization processing method is characterized in that, using the automatically calculated divided block length, a process of performing optimization by blocking the blocking target loop is executed.

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