JP2011194661A - Writing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a writing controller capable of reducing the scale of a circuit for array transformation of image data.SOLUTION: The writing controller for controlling a writing light source of an image forming apparatus includes: a plurality of address counters 103, 104, 105 that produce count values according to a preset rule; an adder 106 that adds the count values respectively produced by the plurality of address counters 103, 104, 105 to produce a write address for writing the image data into a memory; a writing means for writing the image data into an area specified by the writing address; a read address production part 107 that produces a read address for reading the image data from the memory in the address order of the memory; and a reading means that reads the image data from the memory according to the read address.

Description

  The present invention relates to a writing control device that controls a writing light source of an image forming apparatus.

  2. Description of the Related Art Conventionally, in an image forming apparatus using an electrophotographic system, a light emitting element array system in which light emitting elements such as LEDs (Light Emitting Diode) are arranged in an array as a writing light source is known. Thus, as an image forming apparatus using an LED head having a plurality of LEDs, for example, a control circuit capable of lighting an LED element row 2m times (for example, 2 × 4 times) in the sub-scanning direction for each scanning line. In order to realize the above, a technique for writing image data in a memory (SRAM) in accordance with an address generated by an address counter is disclosed (for example, see Patent Document 1).

  However, the array conversion of image data transferred to an LED head composed of a plurality of LED elements is complicated, and there is a problem that the circuit scale for performing the conversion array increases, leading to an increase in cost.

  The present invention has been made in view of the above, and an object of the present invention is to provide a writing control apparatus capable of reducing the circuit scale for array conversion of image data.

  In order to solve the above-described problems and achieve the object, the present invention provides a writing control device that controls a writing light source of an image forming apparatus, and generates a plurality of count values according to a preset rule. An address counter, a write address generating means for generating a write address for writing the image data to the memory by adding the count values generated by each of the plurality of address counters, and the image data in an area specified by the write address , Writing means for writing, address generating means for generating a read address for reading the image data from the memory in order of addresses of the memory, and reading means for reading the image data from the memory according to the read address. It is characterized by that.

  According to another aspect of the present invention, there is provided a writing control apparatus for controlling a writing light source of an image forming apparatus, and writing means for writing image data into the memory in the order of memory addresses, in accordance with a preset rule. A plurality of address counters for generating a count value, a read address generating means for generating a read address for reading the image data from the memory by adding the count values generated by each of the plurality of address counters, and the read And a reading means for reading the image data from an area specified by an address.

  According to the present invention, it is possible to reduce the circuit scale for array conversion of image data.

FIG. 1 is a block diagram illustrating a configuration of an image forming apparatus 20 according to the first embodiment. FIG. 2 is a diagram illustrating a functional configuration of the image writing control unit 100. FIG. 3 is a diagram showing an address array generated by the adder 106. FIG. 4 is a diagram for explaining the count value generated by the first address counter 103. FIG. 5 is a diagram for explaining the count value generated by the second address counter 104. FIG. 6 is a diagram for explaining the count value generated by the third address counter 105. FIG. 7 is a block diagram illustrating a functional configuration of the image writing control unit 120 according to the second embodiment. FIG. 8 is a block diagram illustrating a functional configuration of the image writing control unit 140 according to the third embodiment. FIG. 9 is a block diagram illustrating a functional configuration of the image writing control unit 200 according to the fourth embodiment. FIG. 10 is a block diagram illustrating a functional configuration of the image writing control unit 220 according to the fifth embodiment.

  Hereinafter, an embodiment of a writing control apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an image forming apparatus 20 provided with a writing control apparatus according to the first embodiment of the present invention. The image forming units for each color are arranged along the transfer belt 5 and are called a tandem type. That is, a plurality of image forming units 6BK, 6M, 6C, and 6Y are arranged along the transfer belt 5 in order from the upstream side in the traveling direction of the transfer belt 5. The plurality of image forming units 6BK, 6M, 6C, and 6Y have the same internal configuration except that the colors of the toner images to be formed are different. The image forming unit 6BK forms a black image, the image forming unit 6M forms a magenta image, the image forming unit 6C forms a cyan image, and the image forming unit 6Y forms a yellow image.

  Hereinafter, the configuration of the image forming unit 6BK will be specifically described, but the configurations of the other image forming units 6M, 6C, and 6Y are the same as those of the image forming unit 6BK.

  The transfer belt 5 is a belt wound around a driving roller 7 and a driven roller 15 that are driven to rotate. The drive roller 7 is rotationally driven by a drive motor (not shown), and the drive motor, the drive roller 7, and the driven roller 15 function as drive means for moving the transfer belt 5.

  The image forming unit 6BK includes a photosensitive drum 8BK as a photosensitive member, a charger 9BK disposed around the photosensitive drum 8BK, an LED (Light Emitting Diode) head 10BK, a developing unit 11BK, and a photosensitive cleaner (not shown). And a static eliminator 12BK. The LED head 10BK emits light corresponding to the image color formed by each image forming unit 6BK, that is, black.

  In image formation, the outer peripheral surface of the photosensitive drum 8BK is uniformly charged in the dark by the charger 9BK, and then exposed from the LED head 10BK with light corresponding to a black image, thereby forming an electrostatic latent image. The The developing device 11BK visualizes the electrostatic latent image with black toner, and forms a black toner image on the photosensitive drum 8BK. The toner image is transferred to the transfer belt 5 at a position where the photosensitive drum 8BK and the transfer belt 5 are in contact with each other. After the transfer of the toner image is completed, unnecessary toner remaining on the outer peripheral surface of the photosensitive drum 8BK is wiped off by the photosensitive cleaner, and then the charge is removed by the charge eliminator 12BK, and waits for the next image formation.

  The transfer belt 5 moves to the next image forming unit 6M in order to form the next image on the belt. The image forming unit 6M forms a magenta toner image on the photosensitive drum 8M by a process similar to the image forming process in the image forming unit 6BK. The formed toner image is superimposed and transferred onto the black image formed on the transfer belt 5.

  The transfer belt 5 further moves to the next image forming units 6C and 6Y, and the cyan toner image formed on the photosensitive drum 8C and the yellow toner formed on the photosensitive drum 8Y are moved by the same operation. The toner image is transferred while being superimposed on the transfer belt 5. Thus, a full-color image is formed on the transfer belt 5.

  The full color toner image on the transfer belt 5 is transferred from the paper feed tray 1 to the paper 4 separated and fed by the paper feed roller 2 and the separation roller 3 at the portion where the transfer belt 5 and the paper 4 are in contact with each other. A full color toner image is formed. The sheet 4 on which the full-color superimposed image is formed is discharged to the outside of the image forming apparatus 20 after the image is fixed by the fixing device 14.

  FIG. 2 is a diagram illustrating a functional configuration of the image writing control unit 100. The image writing control unit 100 controls image writing by the LED head 10BK. The LED head 10BK has a plurality of LED elements arranged in an array. For this reason, in order to transmit the input image data such as video data to each LED element, it is necessary to convert the arrangement of the image data. The image writing control unit 100 performs array conversion of the image data.

  The image writing control unit 100 shown in FIG. 2 is provided for each of the LED heads 10BK, 10M, 10C, and 10Y. The image writing control unit 100 includes a speed conversion unit 101, an SRAM control unit 102, and an array conversion SRAM 110. The SRAM control unit 102 includes a first address counter 103, a second address counter 104, a third address counter 105, an adder 106, a read address generation unit 107, and a WE (Write Enable) generation unit 108. is doing.

  Video data as image data output from a controller unit (not shown) is frequency-converted by the speed conversion unit 101 and output to the array conversion SRA 110 as image data (write data). Image data (read data) after array conversion is output from the array conversion SRAM 110 and sent to the LED head 10BK.

  The array conversion SRAM 110 has a write address terminal 111 and a read address terminal 112, and the write address and the read address can be designated by separate signal lines. The SRAM control unit 102 designates the write address and the read address.

  The three address counters 103, 104, and 105 of the SRAM control unit 102 generate count values according to predetermined rules and output the count values to the adder 106. The adder 106 adds the three count values input from the three address counters 103, 104, and 105 to generate the write address of the array conversion SRAM 110.

  FIG. 3 is a diagram showing an address array generated by the adder 106. As described above, the address array generated by the adder 106 is an address corresponding to 4992 counts that are changed every clock according to a specific rule, starting from 24 of “start” to 26 of “end”. Note that one line of image data is stored at addresses 1 to 4992 included in this address array.

  The read address generation unit 107 in FIG. 2 generates a read address that counts up from addresses 1 to 4992. Note that the read address generation unit 107 generates a read address in accordance with the timing of the control signal of another LED head. The WE generator 108 generates a WE signal.

  In the above configuration, the image data is stored in the area specified by the write address by the write address and WE signal generated in the SRAM control unit 102. When the image data for one line is stored, the image data in the array conversion SRAM 110 is read from the array conversion SRAM 110 to be output to the LED head 10BK. At the time of reading, image data is read sequentially from the area specified by the read address generated by the read address generation unit 107. That is, image data is read in order from the area from address 1 to address 4992.

  The image data is array-converted when writing to the array-conversion SRAM 110, and read when reading. Thereby, the array conversion SRAM 110 can output the array-converted image data to the LED 10BK.

  In this manner, the array-converted image data is output to the LED head 10BK, so that the driver circuit of the LED head 10BK can normally light the LED elements with respect to the array-converted image data.

  FIG. 4 is a diagram for explaining the count value generated by the first address counter 103. The first address counter 103 changes the count value every 192 clocks. The count value starts from 0, increments +384 every 192 clocks, and counts up to 4608. When it reaches 4608, it continues to -384 and counts down to 0. The above operation is for one line, and this operation is repeated for each line.

  FIG. 5 is a diagram for explaining the count value generated by the second address counter 104. The second address counter 104 changes the count value every 8 clocks. The count value starts at 24, decreases to -2 every 8 clocks, and counts down to 2. When 2 is reached, it changes to 1, then +2 and counts up to 23. When it reaches 23, it continues to -2 and counts down to 1. When 1 is reached, it changes to 2, then +2 and counts up to 24.

  The above operation is repeated 6 sets as 1 set. After 6 sets, it changes to 24, goes from 24 to -2 and counts down to 2. When 2 is reached, it changes to 1, then +2 and counts up to 23.

  Next, it starts from 25 and increments by 2 until it reaches 47. When it reaches 47, it changes to 48, continues to -2, and counts down to 26. When it reaches 26, it increases by +2 and counts up to 48. When it reaches 48, it changes to 47, then -2 and counts down to 25. The above operation is repeated 6 sets as 1 set.

  After 6 sets, it changes to 25, increments from 25 and counts up to 47. When it reaches 47, it changes to 48, continues to -2, and counts down to 26. One line is completed by the above operation.

  FIG. 6 is a diagram for explaining the count value generated by the third address counter 105. The third address counter 105 changes the count value every clock. The count value starts from 0 and increments by 48 every clock and counts up to 336. When it reaches 336, it continues to -48 and counts down to zero. Such an operation is repeated as 312 sets as one set. One line is completed by the above operation.

  The arrangement conversion of image data corresponding to a predetermined LED head follows a predetermined rule. Therefore, in order to realize this rule, a plurality of address counters are prepared, and the count values generated by the respective address counters are added. Thereby, it is possible to realize a complicated array conversion. In other words, the image writing control unit 100 according to the present embodiment generates the write address by adding the count values generated by the plurality of address counters, thereby efficiently image data with a relatively small circuit scale. Array conversion can be performed.

(Second Embodiment)
FIG. 7 is a block diagram illustrating a functional configuration of the image writing control unit 120 according to the second embodiment. The SRAM control unit 122 of the image writing control unit 120 includes a selector 123. The array conversion SRAM 124 can designate a write address and a read address by the same signal line. The write address output from the adder 106 and the read address output from the read address generation unit 107 are switched by the selector 123 according to the write and read timings, respectively, and output to the array conversion SRAM 124.

  The remaining configuration and processing of the image forming apparatus including the image writing control unit 120 according to the second embodiment are the same as the configuration and processing of the image forming apparatus 20 according to the first embodiment. .

(Third embodiment)
FIG. 8 is a block diagram illustrating a functional configuration of the image writing control unit 140 according to the third embodiment. The image writing control unit 140 does not include the array conversion SRAM, and the array conversion SRAM 142 is provided independently of the image writing control unit 140. Also in this case, the array conversion SRAM 142 receives the image data from the speed conversion unit 101 and the write address, read address, and WE signal from the SRAM control unit 102. Further, the image data is sent from the array conversion SRAM 142 to the LED head 10BK.

  Other configurations and processes of the image forming apparatus including the image writing control unit 140 according to the third embodiment are the same as the configurations and processes of the image forming apparatus according to the other embodiments.

  As another example, also in the image writing control unit 140 according to the third embodiment, the SRAM control unit 102 further includes a selector, and designates a write address and a read address by the same signal line. May be.

(Fourth embodiment)
FIG. 9 is a block diagram illustrating a functional configuration of the image writing control unit 200 according to the fourth embodiment. The SRAM control unit 202 of the image writing control unit 200 generates a read address by using three address counters 203, 204, 205 and an adder 206.

  The configuration and processing of the three address counters 203, 204, 205 and the adder 206 are the same as the configuration and processing of the three address counters 103, 104, 105 and the adder 106 according to the other embodiments. That is, the count value generated by each address counter 203, 204, 205 is the same as the count value described with reference to FIGS. 4 to 6 in the first embodiment, and is generated by the adder 206. The address arrangement is the same as the address arrangement shown in FIG. This address array is output to the array conversion SRAM 110 as a read address. The read address is generated in accordance with the timing of the control signal to other LED heads. On the other hand, the write address generation unit 207 generates a write address that counts up from addresses 1 to 4992.

  With the above configuration, the image writing control unit 200 according to the fourth embodiment follows the addresses 1 to 4992 of the array conversion SRAM 110 when writing the image data output from the speed converter 101 to the array conversion SRAM 110. The image data is stored in order, and at the time of reading, the image data stored in each address of the array conversion SRAM 110 is output along the address array shown in FIG. Thereby, the address-converted image data can be sent to the LED head 10BK.

  The other configurations and processes of the image forming apparatus including the image writing control unit 200 according to the fourth embodiment are the same as the configurations and processes of the image forming apparatus according to the other embodiments.

(Fifth embodiment)
FIG. 10 is a block diagram illustrating a functional configuration of the image writing control unit 220 according to the fifth embodiment. The SRAM control unit 222 of the image writing device 220 includes a selector 223. The array conversion SRAM 224 can designate a write address and a read address by the same signal line. The write address output from the adder 206 and the read address output from the write address generation unit 207 are switched by the selector 223 according to the write and read timings, respectively, and output to the array conversion SRAM 224.

  The other configurations and processes of the image forming apparatus including the image writing control unit 220 according to the fifth embodiment are the same as the configurations and processes of the image forming apparatus according to the other embodiments.

  As another example, in the image forming apparatuses according to the fourth and fifth embodiments, as described in the third embodiment, the array conversion SRAM is independent of the image writing control unit. It may be provided.

  Note that the image forming apparatus according to the above embodiment may be a multi-function machine having at least two functions among a copy function, a printer function, a scanner function, and a facsimile function, such as a copier, a printer, a scanner apparatus, and a facsimile apparatus. The present invention can be applied to any image forming apparatus.

DESCRIPTION OF SYMBOLS 20 Image forming apparatus 100 Image writing control part 101 Speed conversion part 102 SRAM control part 103 1st address counter 104 2nd address counter 105 3rd address counter 106 Adder 107 Read address generation part 108 WE generation part 110 Array conversion SRAM
111 Write address terminal 112 Read address terminal

Japanese Patent Laid-Open No. 7-89128

Claims (5)

A writing control device for controlling a writing light source of an image forming apparatus,
A plurality of address counters that generate count values according to preset rules;
A write address generating means for adding a count value generated by each of the plurality of address counters to generate a write address for writing image data to a memory;
Writing means for writing the image data in an area specified by the write address;
Address generating means for generating a read address for reading the image data from the memory in the order of addresses of the memory;
A writing control device comprising reading means for reading the image data from the memory in accordance with the read address. A writing control device for controlling a writing light source of an image forming apparatus,
Writing means for writing image data into the memory in the order of addresses of the memory;
A plurality of address counters that generate count values according to preset rules;
A read address generating means for adding a count value generated by each of the plurality of address counters to generate a read address for reading the image data from the memory;
A writing control device comprising reading means for reading the image data from an area specified by the read address.   The write control apparatus according to claim 1, further comprising the memory. The memory has a write address terminal and a read address terminal,
The write address is input from the write address terminal,
The write control apparatus according to claim 3, wherein the read address is input from the read address terminal. A selector for selecting the write address or the read address;
The write control apparatus according to claim 3, wherein the write address or the read address selected by the selector is input to the memory.

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