JP2011193242A - Communication controller and communication control method - Google Patents

Abstract

To reduce a load on a CPU during communication.
A main memory section records a descriptor chain that associates a plurality of received data areas with a plurality of descriptors. When the received write data received via the network is accumulated in the packet buffer 7, the communication control unit 10 stores the descriptor corresponding to the write received data area in the write received data area. The write reception data is recorded, and an interrupt signal is output when the descriptor indicates that recording is impossible. When the interrupt signal is output, the CPU 2 reads the received data from the read received data area and updates the descriptor chain so that the descriptor corresponding to the read received data area can be recorded. At this time, the interrupt signal is not output for each packet, and the burden on the CPU can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a communication control device and a communication control method, and more particularly to a communication control device and a communication control method used when receiving reception data in communication exemplified by Ethernet (registered trademark).

  With the popularization of home routers, printers and disk systems are being shared by connecting a plurality of personal computers via a LAN (Local Area Network) at home. For example, when printing from a personal computer to a printer, the amount of data to be transmitted has increased because monochrome printing has changed to color printing, and a large amount of data such as image data has been transferred to Ethernet (registered trademark). ) Can be left in the disk system via. In this flow, communication devices such as Ethernet (registered trademark) transmit large data in a plurality of packets, but the number of packets to be transmitted increases due to the large capacity of the transmission target data. ing. As described above, in order to perform large-capacity data communication from a plurality of personal computers, it is necessary to improve communication efficiency.

  Japanese Patent Laying-Open No. 2003-85129 discloses a data communication controller that can easily detect the end of data reception and transfer data. The data communication controller includes a receive FIFO (First-In First-Out) memory that temporarily holds received data, and a data empty that is output from the receive FIFO memory when all the data held in the receive FIFO memory is transferred. A reception end signal generating means for generating a reception end signal by a signal is provided.

  Japanese Patent Application Laid-Open No. 2001-147875 discloses a data communication system that reduces the number of occurrences of an interrupt signal indicating that communication data transmitted in units of packets through a network has been received, thereby reducing the load on the processing device. ing. The data communication system includes a MAC (Media Access Control) that receives and transmits communication data through a network, a packet buffer that temporarily holds communication data, a main memory unit that stores communication data, and a transfer from a transmission / reception unit MAC A DMA (Direct Memory Access) controller that controls the storage of the received communication data in the main memory unit, a memory interface unit with the main memory unit, and a CPU (Central Processing Unit) that controls the data communication system Yes. Communication data received through the network is temporarily stored in a MAC packet buffer. At this time, the communication data is received by being divided into two blocks of communication data continuously received and communication data received thereafter. The communication data is then transferred from the MAC 31 to the main memory unit 3 via the memory interface unit 5. A descriptor indicating information about the communication data is added to the head portion of each communication data. In the descriptor, a status flag indicating whether or not subsequent communication data is ready for transfer is provided. If the status flag indicates that transfer is possible, the subsequent communication data is continuously transferred to the main memory unit without generating an interrupt signal. Therefore, the data communication system can handle the communication data of a plurality of packets received continuously as a single piece of communication data, and can control data transfer by one interrupt signal.

JP 2003-85129 A JP 2001-147875 A

  In the technique disclosed in Japanese Patent Laid-Open No. 2001-147875, the CPU can perform continuous packet processing with one interrupt when the transmission source and the transmission destination are one-to-one. However, when receiving data from a plurality of transmission sources, as in the case of a plurality of personal computers and one printer, the MAC must receive data in which data from a plurality of transmission sources are mixed. When a plurality of transmission source data are mixed, it is determined that there is no subsequent data, and an interrupt is issued for each packet. That is, in the technique of Japanese Patent Laid-Open No. 2001-147875, when the transmission source and the transmission destination are many-to-one, the data of a plurality of transmission sources are mixed, so that continuous packet processing cannot be performed and the number of interrupts increases, and the CPU processing There is a problem that the burden increases.

  In the technique disclosed in Japanese Patent Laid-Open No. 2001-147875, the CPU reads the received data in the main memory unit, so that the received data storage location in the main memory unit can store new received data. (Hereinafter referred to as reuse.) In order to reuse the received data storage location, the CPU temporarily stops the MAC and DMA controller, and the CPU resets the received data storage address set in the DMA controller. Then, it is necessary to reinitialize the DMA controller and MAC. For this reason, the burden on the CPU has increased. Since it is a system in which the DMA controller constructs descriptors and stores received data, the MAC that issues the storage start signal has no means of knowing the end of reading the received data by the CPU, and when the received data storage location is reused I can't know if I can do it. Therefore, the CPU cannot reuse the received data storage location unless the operation of the MAC and the DMA controller is stopped.

  An example in which the CPU stops the MAC will be described by taking an example in which one printer and a plurality of personal computers are connected. At this time, the data to be printed by the personal computer is transmitted to the printer, and the printer receives the transmission data from the personal computer. Since the printer does not issue a data transmission request, the data transmission timing can be controlled by the personal computer on the data transmission side. When the MAC is operating, data is received from the personal computer. For this reason, the MAC stores received data in the packet buffer. When the data storage location cannot be prepared, the DMA controller does not transfer the received data in the packet buffer to the main memory unit. Therefore, if the MAC continues to receive data, the received data cannot be stored in the packet buffer, and an overflow error occurs. Become. As described above, when the printer cannot receive data in order to prevent an overflow error from occurring, the MAC must be stopped and control must be performed so that transmission data from the personal computer is not received.

  The subject of this invention is providing the communication control apparatus and the communication control method which reduce the burden of CPU at the time of communication.

  In the following, means for solving the problems will be described using the reference numerals used in the modes and examples for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the modes and embodiments for carrying out the invention. Do not use to interpret the technical scope.

  The communication control apparatus according to the present invention includes a main memory unit (3), a communication control unit (10), and a CPU (2). The main memory unit (3) includes a plurality of reception data areas (20 to 24), and records a descriptor chain (12) that associates the plurality of reception data areas (20 to 24) with a plurality of descriptors (13 to 18). The communication control unit (10) refers to the descriptor chain (12) when the received write data received via the network is accumulated in the packet buffer (7), and includes the plurality of descriptors (13 to 18). When the descriptor corresponding to the write reception data area indicates that recording is possible, the write reception data is recorded in the write reception data area, and when the descriptor indicates that recording is impossible, an interrupt signal is output. When the interrupt signal is output, the CPU (2) reads the received data from the read received data area of the plurality of received data areas (20 to 24), and reads the read of the plurality of descriptors (13 to 18). The descriptor chain is updated so that the descriptor corresponding to the received data area indicates that recording is possible.

The communication control method according to the present invention includes:
When the write reception data received via the network is accumulated in the packet buffer (7), the plurality of reception data areas (20 to 24) included in the main memory unit (3) are set to a plurality of descriptors (13 to 18). Referring to the descriptor chain (12) associated with the write reception data area when the descriptor corresponding to the write reception data area of the plurality of reception data areas (20 to 24) indicates that recording is possible. A step of recording data and outputting an interrupt signal when a descriptor corresponding to the write reception data area indicates that recording is impossible;
When the interrupt signal is output, the received data is read from the read received data area of the plurality of received data areas (20 to 24) to the CPU (2), and the descriptor corresponding to the read received data area can be recorded. As shown, it comprises the step of updating the descriptor chain.

  In the communication control apparatus and the communication control method according to the present invention, when the information amount of the writable received data area in the main memory unit is larger than the information amount of one packet, the interrupt signal is not output to the CPU for each packet. Thus, the burden on the CPU during communication can be reduced.

FIG. 1 is a block diagram showing a communication control apparatus according to the present invention. FIG. 2 is a block diagram showing a communication control apparatus according to the present invention. FIG. 3 is a block diagram showing the main memory unit. FIG. 4 is a diagram illustrating a descriptor. FIG. 5 is a flowchart showing the operation of the CPU. FIG. 6 is a flowchart showing the operation of the communication control unit. FIG. 7 is a flowchart showing an operation in which the CPU prepares a descriptor chain in the main memory unit. FIG. 8 is a diagram showing another descriptor chain recorded in the main memory unit.

  An embodiment of a communication control device according to the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, the communication control apparatus includes a communication control unit 10, a CPU 2, a main memory unit 3, and a memory interface unit 5. The memory interface unit 5 is connected to the communication control unit 10 via the internal bus 6 so as to be able to transmit information bidirectionally, and is connected to the CPU 2 so as to be able to transmit information bidirectionally. The CPU 2 is connected to the communication control unit 10 through the interrupt signal line 11 so that information can be transmitted.

  The main memory unit 3 records data that can be written and read by the memory interface unit 5. The memory interface unit 5 is controlled by the communication control unit 10 and records data output from the communication control unit 10 in the main memory unit 3. The memory interface unit 5 is further controlled by the CPU 2 to read data recorded in the main memory unit 3 and output the data to the CPU 2. The communication control unit 10 is connected to a network and receives received data from other communication devices via the network, or transmits communication data to other communication devices via the network. When the CPU 2 receives an interrupt signal from the communication control unit 10 via the interrupt signal line 11, the CPU 2 reads the received data recorded in the main memory unit 3 via the memory interface unit 5 and converts the received data into data To process.

  The communication control unit 10 includes a MAC 1, a DMA controller 4, and a FIFO control 9. The FIFO control 9 includes a packet buffer 7 and a buffer control 8. The buffer control 8 records a restart flag 34. The resume flag 34 is used to determine whether or not to issue an interrupt when the communication control unit 10 resumes from the paused state. The MAC 1 is connected to the network and is connected to the packet buffer 7 and the buffer control 8. The MAC 1 receives communication data from other communication devices via the network and records the communication data in the packet buffer 7. MAC1 transmits communication data to other communication devices via the network. The DMA controller 4 is connected to the packet buffer 7 and the buffer control 8 and controls data input / output. The DMA controller 4 is further connected to the internal bus 6 and exchanges data with the memory interface unit 5.

  FIG. 3 shows the main memory unit 3. The main memory unit 3 includes a descriptor chain area 12 and a MAC reception data area 19. A descriptor chain is recorded in the descriptor chain area 12. The descriptor chain is formed from a plurality of descriptors 13-18. The MAC reception data area 19 includes a plurality of reception data areas 20 to 24. In the plurality of received data areas 20 to 24, received data received from other communication devices by the communication control unit 10 is recorded.

  FIG. 4 shows one descriptor 13 among the plurality of descriptors 13 to 18. The descriptor 13 has a T bit 25, a U bit 26, and a pointer 27. The pointer 27 is used as either a reception data pointer or a link pointer. The reception data pointer indicates the address of any one of the plurality of reception data areas 20-24. The link pointer indicates the address of the area in the descriptor chain area 12 where the descriptor 13 is recorded. The T bit 25 indicates either 0 or 1. The T bit 25 indicates that the pointer 27 indicates the reception data pointer when indicating 0, and indicates that the pointer 27 indicates the link pointer when indicating 1. The U bit 26 indicates either 0 or 1. When the U bit 26 indicates 0, it indicates that the received data is not recorded in the area indicated by the pointer 27, and indicates that the CPU 2 cannot read the received data. When the U bit 26 indicates 1, it indicates that received data is recorded in an area indicated by the pointer 27, and indicates that the CPU 2 can read the received data.

  Other descriptors 14 to 18, which are different from the descriptor 13 among the plurality of descriptors 13 to 18, have a T bit 25, a U bit 26, and a pointer 27 in the same manner as the descriptor 13.

  FIG. 5 shows the operation of the CPU 2. When the communication control device according to the present invention is activated, the CPU 2 first secures the MAC reception data area 19 in the main memory unit 3 and then in the descriptor chain area 12 of the main memory unit 3 via the memory interface unit 5. Is prepared (step S101). Next, the CPU 2 initializes the DMA controller 4 and MAC1 of the communication control unit 10 and activates the communication control unit 10 (step S102). The CPU 2 monitors the communication control unit 10 and outputs an interrupt signal from the communication control unit 10 through the interrupt signal line 11 until the communication control unit 10 finishes storing received data in the main memory unit 3. (Step S103).

  When the interrupt signal is output from the communication control unit 10 (step S103, YES), the CPU 2 reads the descriptor 13 and determines whether or not the U bit 26 of the descriptor 13 is 1, that is, the CPU 2 receives the received data. Whether or not can be read (step S104). When the U bit 26 is 1, the CPU 2 reads the received data stored in the area indicated by the pointer 27 of the descriptor 13 in the main memory unit 3 (step S105). Similarly, the CPU 2 reads the received data indicated by the descriptor 14, the descriptor 15, the descriptor 16 and the descriptor 17. When the CPU 2 has finished reading the reception data recorded in the reception data area 20, the reception data area 21, the reception data area 22, the reception data area 23, and the reception data area 24, the descriptor 13, the descriptor 14, the descriptor 15, and the descriptor 16 The U bit 26 of the descriptor 17 and the descriptor 18 is cleared to 0 (step S106).

  After executing step S106, the CPU 2 monitors the communication control unit 10 again and waits until an interrupt signal is output from the communication control unit 10 via the interrupt signal line 11 (step S103). Each time the CPU 2 outputs an interrupt signal from the communication control unit 10 (step S103, YES), the CPU 2 repeatedly executes the operations of steps S104 to S106.

  FIG. 7 shows the operation of the communication control unit 10. The communication control unit 10 is activated when the CPU 2 executes step S102. When the communication control unit 10 is activated, the DMA controller 4 first reads the descriptor 13 from the main memory unit 3 via the memory interface unit 5 (step S201).

  When the T bit 25 of the read descriptor indicates 0 (step S202, NO) and the U bit 26 of the read descriptor indicates 0 (step S203, NO), the DMA controller 4 The restart flag 34 is cleared with 0 (step S204). After clearing the resume flag 34, the MAC 1 waits until received data is accumulated in the packet buffer 7 (step S205).

  When the received data is accumulated in the packet buffer 7 (YES in step S205), the buffer control 8 instructs the DMA controller 4 to read the received data. In response to the instruction, the DMA controller 4 stores the reception data of the packet buffer 7 in the reception data area 20 of the MAC reception data area 19 indicated by the pointer 27 of the read descriptor (step S206). The buffer control 8 instructs the DMA controller 4 to read the received data again when the DMA controller 4 has not yet stored the received data for one packet in the main memory unit 3 (step S207, NO). Step S205). When the DMA controller 4 finishes storing the received data for one packet (step S207, YES), it writes 1 in the U bit 26 of the read descriptor (step S208).

  When the T bit 25 of the descriptor read in step S201 is 1 (YES in step S202), the DMA controller 4 writes 1 in the U bit 26 of the read descriptor (step S208).

  When the T bit 25 of the descriptor read in step S201 is 0 (NO in step S202) and the U bit 26 of the read descriptor indicates 1 (step S203, YES), it is confirmed whether or not the restart flag 34 is 1 (step S209).

  When the restart flag 34 is 0 (step S209, NO), the DMA controller 4 outputs an interrupt signal to the CPU 2 via the interrupt signal line 11 (step S210). The DMA controller 4 sets the restart flag 34 to 1 after outputting the interrupt signal to the CPU 2 (step S211). The DMA controller 4 waits until received data is accumulated in the packet buffer 7 when the restart flag 34 is 1 (YES in step S209) or after the restart flag 34 is set to 1 (step S212). ).

  The buffer control 8 transfers the received data after step S208 is executed or when the received data is accumulated in the packet buffer 7 after the restart flag 34 is set to 1 (step S212, YES). To the DMA controller 4. In response to the instruction, the DMA controller 4 reads the descriptor next to the descriptor previously read in step S201 (step S201). The descriptor is a descriptor indicated by the link pointer indicated by the pointer 27 of the descriptor read last time when the T bit 25 of the descriptor read last time is 1.

  FIG. 6 shows step S101 of FIG. 5, that is, an operation of preparing a descriptor chain in the descriptor chain area 12 of the main memory unit 3. First, the DMA controller 4 sets the U bit 26 of the descriptor 13 to 0, sets the T bit 25 of the descriptor 13 to 0, and stores the storage address of the reception data area 20 of the MAC reception data area 19 in the pointer 27 of the descriptor 13. Is set (step S301). The DMA controller 4 sets the U bit 26 of the descriptor 14 to 0, sets the T bit 25 of the descriptor 14 to 0, and indicates the storage address of the reception data area 21 of the MAC reception data area 19 in the pointer 27 of the descriptor 14. A reception data pointer is set (step S302). The DMA controller 4 sets the U bit 26 of the descriptor 15 to 0, sets the T bit 25 of the descriptor 15 to 0, and indicates the storage address of the reception data area 22 of the MAC reception data area 19 in the pointer 27 of the descriptor 15. A reception data pointer is set (step S303). The DMA controller 4 sets the U bit 26 of the descriptor 16 to 0, sets the T bit 25 of the descriptor 16 to 0, and indicates the storage address of the reception data area 23 of the MAC reception data area 19 in the pointer 27 of the descriptor 16. A reception data pointer is set (step S304). The DMA controller 4 sets the U bit 26 of the descriptor 17 to 0, sets the T bit 25 of the descriptor 17 to 0, and indicates the storage address of the reception data area 24 of the MAC reception data area 19 in the pointer 27 of the descriptor 17. A reception data pointer is set (step S305). The DMA controller 4 sets the U bit 26 of the descriptor 18 to 0, sets the T bit 25 of the descriptor 18 to 1, and sets a link pointer indicating the address of the next descriptor 13 to the pointer 27 of the descriptor 18 (step) S306).

  According to such an operation, since the descriptor 18 is an arrangement address of the descriptor 13, a plurality of descriptors 13 to 18 are configured in a ring shape in the descriptor chain.

  According to such an operation, the communication control device according to the present invention interrupts the CPU 2 from the communication control unit 10 after the reception data of a predetermined amount of information is accumulated even when transmission data is received from a plurality of personal computers. A signal is output once. For this reason, the CPU 2 can read the received data at a timing other than every packet, and the burden on the CPU 2 is reduced. When the communication control unit 10 receives the received data and cancels the pause state, the communication control unit 10 can re-read the descriptor and check whether the CPU 2 has finished reading the received data in the state of the U bit of the descriptor. Therefore, the CPU 2 does not need to reinitialize the DMA controller 4 and the MAC 1, and the burden on the CPU 2 is further reduced.

  In the communication control apparatus according to the present invention, the communication control unit 10 detects the presence or absence of the U bit 26 in the descriptors 13 to 18, and outputs an interrupt signal to the CPU 2 when receiving the U bit 26 and receives it via the memory interface unit 5. The process of storing the data in the main memory unit 3 is changed to the temporary stop state. When the communication control device according to the present invention receives the received data, the communication control device releases the pause state, re-reads the descriptor, and if the U bit of the descriptor is set, sets the pause state again. When the U bit is cleared, the pause state is canceled and an interrupt is output when the pause state is entered again. That is, the communication control unit 10 can output an interrupt to the CPU in the U bit state when reading the descriptor. For this reason, since the CPU can collectively read the received data with a single interrupt, the communication control device according to the present invention can reduce the burden on the CPU.

  The communication control device according to the present invention can further resume the reception operation in the state of the U bit when the descriptor is read. That is, the communication control apparatus according to the present invention does not require the CPU to operate the MAC and DMA controller in order to reuse the received data storage location, and only sets the descriptor. For this reason, the communication control apparatus according to the present invention can reduce the burden on the CPU.

  The descriptor has a T bit, a U bit, and a received data pointer or a link pointer, and the descriptor chain can be set in a ring state by designating the arrangement address of the first descriptor in the link pointer. For this reason, the communication control apparatus according to the present invention can further re-use the received data storage area, eliminating the need for a large-capacity RAM.

  FIG. 8 shows a CPU-generated descriptor set by another operation different from step S101 or step S106. In the CPU-generated descriptor chain 28, the descriptor 17 is replaced with another descriptor 29 as compared with the descriptor chain 12 in the above-described embodiment. The descriptor 29 has the T bit 25 set to 0 and the U bit 26 set to 1. At this time, the communication control unit 10 reads the descriptor 29, confirms that the U bit 26 is 1, outputs an interrupt, sets a resume flag, enters a pause state, and waits for received data.

  That is, the CPU 2 can make another setting different from the setting of the descriptor chain 12 in the above-described embodiment, and can design the setting based on a desired frequency, for example. At this time, the communication control apparatus according to the present invention can output a single interrupt at the timing when the CPU 2 wants to read the received data by setting the U bit of the descriptor for which the received data is to be read at once. .

1: MAC
2: CPU
3: Main memory unit 4: DMA controller 5: Memory interface unit 6: Internal bus 7: Packet buffer 8: Buffer control 9: FIFO control 10: Communication control unit 11: Interrupt signal line 12: Descriptor chain area 13-18: Descriptor 19: MAC reception data area 20-24: Reception data area 25: T bit 26: U bit 27: Pointer 34: Resume flag

Claims (10)

A main memory unit that includes a plurality of reception data areas, and that records a descriptor chain that associates the plurality of reception data areas with a plurality of descriptors;
When write reception data received via the network is accumulated in a packet buffer, referring to the descriptor chain, when the descriptor corresponding to the write reception data area of the plurality of descriptors indicates recordable A communication control unit that records the write reception data in a write reception data area and outputs an interrupt signal when the descriptor indicates that recording is impossible;
When the interrupt signal is output, the received data is read from the read received data area of the plurality of received data areas, and the descriptor corresponding to the read received data area of the plurality of descriptors is recordable. , CPU for updating the descriptor chain
A communication control device comprising: In claim 1,
The communication control unit is configured so that, when the write reception data is recorded in the write reception data area, the descriptor chain corresponding to the write reception data area of the plurality of descriptors indicates that recording cannot be performed. Update communication control device. In claim 2,
The communication control unit clears a restart flag when the descriptor indicates that recording is impossible, sets the restart flag when the interrupt signal is output,
The interrupt signal is output when the restart flag is cleared. In any one of Claims 1-3,
Each of the plurality of descriptors corresponds to either reusable or non-reusable,
The non-reusable descriptor corresponding to the non-reusable of the plurality of descriptors indicates another descriptor different from the non-reusable descriptor of the plurality of descriptors,
The communication control unit, when the write reception data is recorded in the write reception data area, and another write reception data received via the network is accumulated in the packet buffer. When the next descriptor corresponding to the next received data area of the write received data area in the area indicates reusability, the other received received data is recorded in the next received data area, and the next descriptor is recorded. A communication control device that records the other received write data in a receive data area corresponding to a descriptor indicated by the next descriptor when indicates that reuse is not possible. In claim 4,
The CPU updates the descriptor chain so that one descriptor selected from the plurality of descriptors indicates that recording is impossible based on the frequency of reading received data. When the write reception data received via the network is accumulated in the packet buffer, the write of the plurality of reception data areas is referred to by referring to the descriptor chain that associates the plurality of reception data areas of the main memory unit with the plurality of descriptors. The write reception data is recorded in the write reception data area when the descriptor corresponding to the reception data area indicates recordable, and an interrupt signal is output when the descriptor corresponding to the write reception data area indicates unrecordable. Steps,
When the interrupt signal is output, the descriptor chain is configured to read the received data from the read received data area of the plurality of received data areas to the CPU and indicate that the descriptor corresponding to the read received data area can be recorded. A communication control method comprising the steps of: In claim 6,
Updating the descriptor chain such that when the write reception data is recorded in the write reception data area, the descriptor corresponding to the write reception data area of the plurality of descriptors indicates that recording is not possible. Communication control method. In claim 7,
Clearing a resume flag when the descriptor indicates unrecordable;
Further comprising setting the restart flag when the interrupt signal is output;
The communication control method, wherein the interrupt signal is output when the restart flag is cleared. In any one of Claims 6-8,
Each of the plurality of descriptors corresponds to either reusable or non-reusable,
The non-reusable descriptor corresponding to the non-reusable of the plurality of descriptors indicates another descriptor different from the non-reusable descriptor of the plurality of descriptors,
further,
After the write reception data is recorded in the write reception data area, when other write reception data received via the network is accumulated in the packet buffer, the write reception of the plurality of reception data areas When the next descriptor corresponding to the next received data area of the data area indicates that the next descriptor can be reused, the other received received data is recorded in the next received data area, and the next descriptor cannot be reused. A communication control method comprising: recording the other received write data in a received data area corresponding to the descriptor indicated by the next descriptor. In claim 9,
A communication control method, further comprising: updating the descriptor chain so that one descriptor selected from the plurality of descriptors indicates that recording is not possible based on a frequency of reading received data.

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