JP2011192690A - Transistor substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor substrate having a thin film transistor whose deterioration in gate voltage-drain current characteristics (Vg-Id characteristics) in an off region is suppressed, and to provide a method of manufacturing the transistor substrate. <P>SOLUTION: A region (and a neighboring region thereof) having a sidewall portion exposed between source-drain electrodes 17, of a semiconductor layer 14 formed in a lower layer of a channel protection layer 15 provided in the thin film transistor TFT is subjected to oxidation processing by oxygen plasma processing. Consequently, an oxide film 20 is formed in the region to make the region non-conductive or high in resistance. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a transistor substrate and a manufacturing method thereof, and more particularly to a transistor substrate including a thin film transistor having a channel protection layer on an insulating substrate and a manufacturing method thereof.

  2. Description of the Related Art In recent years, thin displays such as liquid crystal display devices, organic electroluminescence displays, and plasma displays are widely used as displays and monitors for electronic devices such as mobile phones and digital cameras, as well as televisions and personal computers. In a display panel and a driver for such a thin display, a panel structure including a thin film transistor element using a silicon thin film as a channel layer on an insulating substrate such as glass is generally used.

  Various element structures are known as thin film transistors provided on an insulating substrate. For example, in a thin film transistor with an inverted stagger structure, when patterning the source and drain electrodes, a channel stopper type device structure having a channel protective layer covering a semiconductor layer to be a channel layer, and channel etching without a channel protective layer A type element structure is known. With regard to thin film transistors having a channel stopper type or channel etching type element structure, for example, Patent Documents 1 and 2 describe examples of the structure and manufacturing process thereof.

JP-A-10-289910 JP 2009-290168 A

  As a result of verification by the inventors on the thin film transistor having the element structure as described above, it has been found that transistor characteristics may be deteriorated which may be caused by the manufacturing process. Although details will be described later, in a thin film transistor manufactured by forming a channel protective layer on a semiconductor layer, forming source and drain electrodes, and etching the lower semiconductor layer using the source and drain electrodes as a mask, A phenomenon was observed in which the voltage-drain current characteristics (Vg-Id characteristics) deteriorated significantly in the off region. Specifically, it has been found that the off characteristics of the thin film transistor become unstable, and a leakage current (off current) larger than expected may flow during the off operation. For this reason, when such a thin film transistor is applied as a display panel for a thin display or a switching element or a driving element for a driving driver, there is a problem that the yield of the product is remarkably lowered or the display image quality is deteriorated. is doing.

  Therefore, in view of the above-described problems, the present invention has an object to provide a transistor substrate including a thin film transistor in which deterioration of gate voltage-drain current characteristics (Vg-Id characteristics) in an off region is suppressed, and a manufacturing method thereof. To do.

The transistor substrate according to claim 1 sandwiches a substrate, a gate electrode, a semiconductor layer facing the gate electrode through an insulating film, and a channel region formed in the semiconductor layer on the substrate. And a source electrode and a drain electrode having a film stress of 700 MPa or less facing each other, and at least a side wall portion of the semiconductor layer between the source electrode and the drain electrode is oxidized to be non-conductive And.
According to a second aspect of the present invention, in the transistor substrate according to the first aspect, the substrate further comprises a light emitting element and a light emission driving circuit for driving the light emitting element on the substrate. A transistor is provided.

According to a third aspect of the present invention, there is provided a method of manufacturing a transistor substrate, comprising: forming a gate electrode on the substrate; forming a semiconductor film facing the gate electrode through an insulating film; Forming a metal layer on the substrate, patterning the metal layer, and forming a source electrode and a drain electrode having a film stress of 700 MPa or less facing each other across the channel region, and using the source electrode and the drain electrode as a mask And patterning the semiconductor film to form a semiconductor layer, and oxidizing the substrate to render at least a sidewall portion of the semiconductor layer non-conductive.
According to a fourth aspect of the present invention, in the method for manufacturing a transistor substrate according to the third aspect, the step of patterning the semiconductor layer is performed using a dry etching method, and the step of oxidizing the substrate is performed by an oxygen plasma treatment. Is executed.

  According to the present invention, it is possible to suppress the deterioration of the Vg-Id characteristics in the off region of the thin film transistor. Further, according to the present invention, the yield of products can be improved and a display with good image quality can be realized.

1 is a schematic cross-sectional view showing a first embodiment of a transistor substrate according to the present invention. It is a process flow which shows an example of the manufacturing method of the transistor substrate which concerns on 1st Embodiment. It is a schematic process drawing (the 1) which shows an example of the manufacturing method of the transistor substrate which concerns on 1st Embodiment. It is a schematic process figure (the 2) which shows an example of the manufacturing method of the transistor substrate which concerns on 1st Embodiment. It is a figure which shows the measurement result of the element characteristic (Vg-Id characteristic) of the thin-film transistor which concerns on 1st Embodiment. It is a process flow which shows the manufacturing method of the transistor substrate used as a comparative example for demonstrating the effect in the thin-film transistor which concerns on 1st Embodiment, and its manufacturing method. It is a figure which shows the measurement result of the element characteristic (Vg-Id characteristic) of the thin-film transistor which concerns on a comparative example. It is a conceptual diagram which shows the ideal behavior of the element characteristic (Vg-Id characteristic) of a thin-film transistor. It is a schematic block diagram for demonstrating the presumed cause of the difference in the element characteristic in the thin-film transistor concerning 1st Embodiment and a comparative example. It is a schematic sectional drawing which shows 2nd Embodiment of the transistor substrate which concerns on this invention. It is a process flow which shows an example of the manufacturing method of the transistor substrate which concerns on 2nd Embodiment. It is a figure which shows the measurement result of the element characteristic (Vg-Id characteristic) of the thin-film transistor which concerns on 2nd Embodiment. It is a process flow which shows an example of the manufacturing method of the transistor substrate which concerns on 3rd Embodiment. It is a schematic block diagram which shows the 1st structural example of the display apparatus with which the transistor substrate which concerns on this invention is applied. It is a schematic block diagram which shows the 2nd structural example of the display apparatus with which the transistor substrate which concerns on this invention is applied. It is a perspective view which shows the structural example of the digital camera to which the light-emitting device which concerns on this invention is applied. It is a perspective view which shows the structural example of the thin-type television to which the light-emitting device based on this invention is applied. 1 is a perspective view illustrating a configuration example of a mobile personal computer to which a light emitting device according to the present invention is applied. It is a figure which shows the structural example of the mobile telephone to which the light-emitting device which concerns on this invention is applied.

Hereinafter, a transistor substrate and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
(Transistor substrate)
FIG. 1 is a schematic cross-sectional view showing a first embodiment of a transistor substrate according to the present invention. Here, FIG. 1 shows a configuration in which only one thin film transistor is provided over a substrate for the sake of simplicity.

  As shown in FIG. 1, the transistor substrate according to the first embodiment has an inverted staggered structure having a channel stopper type element structure on one surface (upper surface in the drawing) side of an insulating substrate 11 such as glass or plastic. A thin film transistor TFT is provided.

  Specifically, as shown in FIG. 1, the thin film transistor TFT according to this embodiment includes a gate electrode 13, a gate insulating film 12, a semiconductor layer 14, a channel protective layer 15, a highly doped semiconductor layer (impurity semiconductor). Layer) 16 and source and drain electrodes (hereinafter collectively referred to as “source and drain electrodes”) 17. The gate electrode 13 is provided on the surface on the one surface side of the insulating substrate 11 and is covered with the gate insulating film 12. The semiconductor layer 14 is provided in a region corresponding to the gate electrode 13 through the gate insulating film 12. The semiconductor layer 14 is made of, for example, polysilicon or amorphous silicon. The channel protective layer 15 is provided on the semiconductor layer 14 in which the channel region is formed, and has a predetermined planar shape. The source and drain electrodes 17 are opposed to each other with the channel protective layer 15 interposed therebetween, and are provided so as to extend from both ends of the channel protective layer 15 onto the semiconductor layer 14. A highly doped semiconductor layer 16 is provided between the channel protective layer 15 and the semiconductor layer 14 and the source and drain electrodes 17.

  1 shows a state in which the source and drain electrodes 17 of the thin film transistor TFT provided on the substrate 11 are exposed, but in the actual product, the upper surface of the substrate 11 including the thin film transistor TFT is not shown. It is covered with a protective insulating film or the like (see FIG. 4). In addition, a structure in which a display element, an upper wiring layer, and the like are formed via an interlayer insulating film, a planarizing film, or the like on the structure shown in FIG.

  In the transistor substrate having the above-described configuration, particularly in the present embodiment, the sidewall is exposed between the source and drain electrodes 17 and is formed below the channel protection layer 15 in the semiconductor layer 14 of the thin film transistor TFT. The region to be (and the vicinity thereof) is characterized by being oxidized by oxygen plasma treatment.

(Production method)
Next, a method for manufacturing the transistor substrate as described above will be described with reference to the drawings.
FIG. 2 is a process flow showing an example of a method for manufacturing a transistor substrate according to the first embodiment. 3 and 4 are schematic process diagrams showing an example of a method for manufacturing a transistor substrate according to the first embodiment. 3 and 4 are schematic plan views of the transistor substrate in each manufacturing process, and the diagram shown on the right side is a transistor along the XA-XA line of the plan view shown on the left side. It is a schematic sectional drawing of a board | substrate. Here, in the plan views shown in FIGS. 3 and 4, for the sake of clarity, the same hatching as that of each component shown in the cross-sectional view is given for the sake of clarity. For convenience of illustration, only the hatching of the uppermost protective insulating film is omitted.

  First, in the gate electrode formation step S101 of FIG. 2, as shown in FIG. 3A, a PVD method (Physical Vapor Deposition: physical vapor phase) such as vapor deposition or sputtering is performed on an insulating substrate 11 such as glass. A gate metal layer is formed using a growth method. Thereafter, a resist having a desired planar pattern is formed by using a photolithography method, and the gate metal layer is patterned by using a wet etching method or a dry etching method to form the gate electrode 13 of the thin film transistor TFT. Here, as the gate metal layer to be the gate electrode 13, for example, aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), niobium (Nb), molybdenum (Mo), A metal simple substance such as silver (Ag), tantalum (Ta), tungsten (W) or the like, a metal material made of an alloy thereof, or a compound material containing any of these can be used. The gate electrode 13 is formed to a thickness of about 100 nm (1000 mm), for example.

  Next, in the gate insulating film forming step S102, the semiconductor layer forming step S103, and the etching stopper film forming step S104, as shown in FIG. 3B, for example, plasma CVD is performed on the substrate 11 on which the gate electrode 13 is formed. The gate insulating film 12, the amorphous silicon semiconductor layer 14x, and the insulating layer 15x are continuously formed using a method. As a result, the gate electrode 13 on the substrate 11 is covered with the gate insulating film 12. Here, as the gate insulating film 12, for example, a silicon nitride film or a silicon oxide film is used, and the gate insulating film 12 is formed to a thickness of, for example, about 400 nm (4000 mm). The amorphous silicon semiconductor layer 14x is formed to a thickness of about 50 nm (500 mm), for example, and the insulating layer 15x is a silicon nitride film or a silicon oxide film, for example, about 120 nm (1200 mm). Formed.

  Next, in the etching stopper forming step S105, as shown in FIG. 3C, the insulating layer 15x is patterned by using a photolithography method to form a channel protective layer (etching stopper layer) 15 having a desired planar shape. Form. Specifically, a photoresist (not shown) is patterned so as to remain only in a region that becomes a channel layer of the thin film transistor TFT (semiconductor layer 14) and that corresponds to the formation region of the gate electrode 13, The insulating layer 15x is dry etched using the photoresist. Thereby, the channel protective layer 15 is formed on the amorphous silicon semiconductor layer 14x.

Next, in the highly doped semiconductor layer forming step S106 and the source / drain metal film forming step S107, as shown in FIG. 3D, for example, a plasma CVD method is performed on the substrate 11 on which the channel protective layer 15 is formed. Then, a highly doped semiconductor layer (impurity layer) 16x is formed over the entire region of the substrate 11. Thereafter, the source / drain metal layer 17x is formed over the entire region of the substrate 11 on the highly doped semiconductor layer 16x by using, for example, the PVD method. Here, the highly doped semiconductor layer 16x is a silicon layer (p ⁺ -Si layer or n ⁺ -Si layer) mixed with p-type or n-type impurities. The highly doped semiconductor layer 16x is formed to a thickness of about 25 nm (250 mm), for example. For the source / drain metal layer 17x, for example, a single metal such as chromium (Cr), aluminum (Al), titanium (Ti), niobium (Nb), or a metal material made of these alloys can be used. The source / drain metal layer 17x is formed to a thickness of about 100 nm (1000 mm), for example.

  Next, in the source and drain electrode formation step S108, as shown in FIG. 4A, a resist having a desired plane pattern is formed using a photolithography method, and a wet etching method or a dry etching method is used. The source / drain metal layer 17x is patterned to form the source / drain electrodes 17 of the thin film transistor TFT. Thereafter, in the highly doped semiconductor layer / semiconductor layer forming step S109, as shown in FIG. 4B, the source and drain electrodes 17 are used as a mask by using a dry etching method, and the underlying highly doped semiconductor layer 16x and amorphous layer are formed. The silicon semiconductor layer 14x is continuously etched. At this time, the highly doped semiconductor layer 16x is patterned into a planar shape matching the source and drain electrodes 17 to form the highly doped semiconductor layer 16, and at the same time, the channel protective layer 15 is exposed. The amorphous silicon semiconductor layer 14 x is patterned into a planar shape that matches the source, drain electrode 17 and channel protective layer 15 to form the semiconductor layer 14. Thus, the highly doped semiconductor layer 16 and the source / drain electrodes 17 are opposed to the formation region of the thin film transistor TFT with the channel protective layer 15 interposed therebetween and extend from both ends of the channel protective layer 15 onto the semiconductor layer 14. Is formed.

  Next, in the oxygen plasma treatment step S110, the substrate 11 on which the source and drain electrodes 17 are formed is subjected to oxygen plasma treatment, and the side wall portion of the semiconductor layer 14 formed below the channel protective layer 15 and its vicinity. The region is inactivated (non-conductive or high resistance). Thereby, the thin film transistor TFT according to this embodiment shown in FIG. 1 is completed.

  Next, in the overcoat insulating film forming step S111, as shown in FIG. 4C, a protective insulating film (overcoat insulating film) is formed on the substrate 11 on which the thin film transistor TFT is formed by using, for example, a plasma CVD method. 18 is deposited. Thereby, the thin film transistor TFT on the substrate 11 is covered with the protective insulating film 18. Here, as the protective insulating film 18, for example, a silicon nitride film or a silicon oxide film is used, and is formed to a thickness of about 200 nm (2000 mm), for example.

  Next, in the terminal hole forming step S112, as shown in FIG. 4D, a resist having a desired plane pattern is formed using a photolithography method, and protective insulation is formed using a wet etching method or a dry etching method. The film 18 is patterned to form contact holes (terminal holes) HLg and HLsd in which desired regions of the gate electrode 13 and the source and drain electrodes 17 of the thin film transistor TFT are exposed. Thereafter, individual wiring layers having a desired planar pattern (not shown) are formed and individually connected to the gate electrode 13 and the source and drain electrodes 17 of the thin film transistor TFT via the contact holes HLg and HLsd. .

  In the thin film transistor TFT according to this embodiment, the element structure in which the source and drain electrodes 17 are directly provided on the semiconductor layer 14 via the highly doped semiconductor layer 16 is shown. However, the present invention is not limited to this. Instead, a buffer layer made of chromium silicide may be provided between the highly doped semiconductor layer 16 and the source / drain electrodes 17. In this case, the following manufacturing method can be applied. That is, after the channel protective layer 15 is formed on the amorphous silicon semiconductor layer 14x in the semiconductor layer forming step S103 and the etching stopper film forming step S104 shown in the above-described process flow (see FIG. 2), a high level is formed on the substrate 11. A doped semiconductor layer 16x, a chromium silicide layer, and a source and drain metal layer 17x are sequentially formed. Next, the source and drain metal layers 17x are patterned to form the source and drain electrodes 17. Using the dry etching method, the source and drain electrodes 17 are used as a mask, and the underlying chromium silicide layer, highly doped semiconductor layer 16x, and The amorphous silicon semiconductor layer 14x is continuously etched. Thus, the highly doped semiconductor layer 16, the chromium silicide layer and the source and drain electrodes 17 are formed so as to face each other with the channel protective layer 15 interposed therebetween and extend from both ends of the channel protective layer 15 onto the semiconductor layer 14. The completed thin film transistor TFT is completed.

Next, element characteristics of the above-described thin film transistor will be specifically described.
FIG. 5 is a diagram illustrating measurement results of element characteristics (Vg-Id characteristics) of the thin film transistor according to the first embodiment. Here, in a plurality of n-channel type amorphous silicon thin film transistors (n-ch TFTs) manufactured by using the above-described manufacturing method, the channel ratio W / L = 10 and the drain-source voltage Vds = 10 V are set. Vg-Id characteristics are shown.

  As shown in FIG. 5, the Vg-Id characteristic of the thin film transistor TFT according to this embodiment is that the drain current Id is approximately 1.0E-12A or 1.0E in the off region where the gate voltage Vg is lower than 0V. A current value of about −14 A was shown. On the other hand, in the ON region where the gate voltage Vg is higher than 0V, the drain current Id showed a current value of about 1.0E-06A. In addition, the drain current Id tended to change sharply in the switching region from the off region to the on region of the thin film transistor TFT (that is, the gate voltage Vg was near 0 V).

  That is, according to the thin film transistor TFT according to the present embodiment, a substantially constant (stable) minute leakage current (off current) of approximately 1.0E-12A flows during the off operation, and approximately 1.0E− during the on operation. It was found that a substantially constant and relatively high drain current Id of about 06 A flows. It has also been found that the drain current Id flow (current value) switches quickly between the off region and the on region. And the tendency of such Vg-Id characteristic was observed substantially equally in the some thin film transistor TFT to which the manufacturing method concerning this embodiment was applied.

(Verification of effects)
Next, the advantages of the operational effects of the transistor substrate having the thin film transistor according to the present embodiment and the manufacturing method thereof will be described in detail with reference to a comparative example.

  FIG. 6 is a process flow showing a method for manufacturing a transistor substrate to be compared (hereinafter, referred to as “comparative example”) for explaining the operational effects of the thin film transistor and the method for manufacturing the same according to the first embodiment. . Here, the description of the manufacturing process equivalent to that of the first embodiment will be simplified. FIG. 7 is a graph showing measurement results of element characteristics (Vg-Id characteristics) of the thin film transistor according to the comparative example. FIG. 8 is a conceptual diagram showing an ideal behavior of element characteristics (Vg-Id characteristics) of a thin film transistor. Here, as in the first embodiment described above, in a plurality of n-channel amorphous silicon thin film transistors (n-ch TFTs) manufactured using the manufacturing method according to the comparative example, the channel ratio W / L = 10, The Vg-Id characteristic when the drain-source voltage Vds is set to 10 V is shown. In FIG. 8, the drain current Id on the vertical axis is shown on a log scale in order to clarify the behavior of device characteristics.

  In the thin film transistor manufacturing method in the comparative example, as shown in the process flow of FIG. 6, after the source / drain electrode forming step S508 and the highly doped semiconductor layer / semiconductor layer forming step S509, an overcoat insulating film forming step S510 is performed. Executed. That is, in the comparative example, the source, drain electrode 17 and channel protective layer 15 of the thin film transistor TFT are covered without performing the oxygen plasma processing step S110 shown in the first embodiment (see FIG. 2). A protective insulating film 18 is formed.

  In the thin film transistor TFT manufactured by such a manufacturing method, as shown in FIG. 7, the drain current Id is about 1.0E-12 to 1.0E-09A in the off region where the gate voltage Vg is lower than 0V. The current value was shown. On the other hand, in the ON region where the gate voltage Vg is higher than 0V, the drain current Id showed a current value of about 1.0E-09 to 1.0E-05A. Further, the drain current Id tended to change slowly in the switching region from the off region to the on region of the thin film transistor TFT (that is, the gate voltage Vg was near 0 V).

  That is, in the thin film transistor according to the comparative example, an unstable and relatively large leakage current (off current) of approximately 1.0E-12 to 1.0E-09A flows during the off operation, and approximately 1.0E− during the on operation. It was found that an unstable drain current Id of about 09 to 1.0E-05A flows. It has also been found that the drain current Id flow (current value) does not quickly switch between the off region and the on region.

  Here, the ideal behavior of the element characteristics of the thin film transistor is, for example, as shown by the characteristic line SP1 in FIG. 8, where the drain current Id is in the ON region on the positive voltage side with the gate voltage Vg = 0V as a boundary. For example, it is desirable to show a stable current value of about 1.0E-06A, and to show a stable current value of about 1.0E-12A in the off region on the negative voltage side. In addition, it is desirable that the drain current Id changes steeply (rapidly) when the gate voltage Vg is in the vicinity of 0V.

  However, the device characteristics of the thin film transistor according to the comparative example are roughly as shown by the characteristic line SP2 in FIG. 8, and the drain current Id is unstable particularly in the off region on the negative voltage side, and the characteristic line SP1. The current value tended to increase compared to. Therefore, as shown in the problem to be solved by the present invention, when such a thin film transistor is applied to a display panel or a driver, there is a problem that the yield of the product is remarkably lowered.

  On the other hand, in the thin film transistor TFT according to the first embodiment described above, the element characteristic (Vg-Id characteristic) showed a good behavior that approximated the characteristic line 1 in FIG. Such a difference in device characteristics between the present embodiment and the comparative example is considered to be due to the following reason.

  FIG. 9 is a schematic configuration diagram for explaining an estimation cause of a difference in element characteristics in the thin film transistor according to the first embodiment and the comparative example. Here, FIGS. 9A to 9C show the case where the highly doped semiconductor layer 16x and the amorphous silicon semiconductor layer 14x are continuously etched in the source and drain electrode forming step and the highly doped semiconductor layer and semiconductor layer forming step. It is a schematic plan view and a schematic cross-sectional view. 9D and 9E are a schematic plan view and a schematic cross-sectional view when the oxygen plasma processing according to the present embodiment is performed. In addition, about the structure equivalent to the schematic process drawing shown to embodiment mentioned above, the same code | symbol is attached | subjected and the description is simplified.

  In the manufacturing method shown in the first embodiment and the comparative example described above (see the process flow of FIGS. 2 and 6 and the schematic process diagrams of FIGS. 3 and 4), in the source and drain electrode formation steps S108 and S508, After the source and drain metal layers 17x formed on the substrate 11 are wet-etched to pattern the source and drain electrodes 17, the source and drain electrodes 17 are formed in the highly doped semiconductor layer and semiconductor layer forming steps S109 and S509. As a mask, the lower highly doped semiconductor layer 16x and amorphous silicon semiconductor layer 14x are continuously etched. As a result, as shown in FIG. 4B, the highly doped semiconductor layer 16x is patterned into a planar shape matching the source and drain electrodes 17 to form the highly doped semiconductor layer 16, and at the same time, the channel protective layer. 15 is exposed. The amorphous silicon semiconductor layer 14 x is patterned into a planar shape that matches the source, drain electrode 17 and channel protective layer 15 to form the semiconductor layer 14.

  Here, when the highly doped semiconductor layer 16x and the amorphous silicon semiconductor layer 14x are continuously etched using the source and drain electrodes 17 as a mask, as shown in FIGS. 9A to 9C, channel protection is performed. Of the semiconductor layer 14 formed below the layer 15, the region where the side wall is exposed between the source and drain electrodes 17 and the vicinity thereof (the step region indicated by the arrow DT in FIGS. 9A and 9C). In addition, it is presumed that a film 19 of silicon hydrate (Si hydrate) is formed. Since the Si hydrate film 19 is not uniform in thickness and has a certain conductivity, as shown in FIG. 7, the Si hydrate film is turned off when the thin film transistor TFT is turned off. It is considered that the drain current Id is unstable and relatively flows through the film 19. Further, due to this, it is considered that the drain current Id flow (current value) does not quickly switch between the off region and the on region of the thin film transistor TFT. Such a phenomenon is remarkable when a dry etching method is applied as a method for continuously etching the highly doped semiconductor layer 16x and the amorphous silicon semiconductor layer 14x.

  Therefore, in the present invention, a highly doped semiconductor layer having a planar shape that matches the source and drain electrodes 17 using a dry etching method in the highly doped semiconductor layer and semiconductor layer forming step S109 after the source and drain electrode forming step S108. 16 and a planar semiconductor layer 14 aligned with the source and drain electrodes 17 and the channel protective layer 15 are formed, and thereafter, in the oxygen plasma treatment step S110, the substrate surface is oxidized by oxygen plasma treatment. As a result, as shown in FIGS. 9D and 9E, the oxide film 20 is formed on the surface of the substrate 11 including the thin film transistor TFT. At this time, the Si hydrate film 19 formed (presumed to be formed) on the side wall portion of the semiconductor layer 14 formed in the lower layer of the channel protective layer 15 and in the vicinity thereof is oxidized to be inactivated ( Non-conductor or high resistance).

  Therefore, in the thin film transistor TFT according to the present embodiment, the drain current Id does not flow (presumed to disappear) through the Si hydrate film 19 described above during the off operation, and as shown in FIG. In addition, only a substantially constant (stable) minute leakage current (off-state current) flows, and it is estimated that the off-characteristic is improved. Also, due to this, it is presumed that the drain current Id is quickly switched between the off region and the on region of the thin film transistor TFT, and the characteristics are improved. Therefore, even when the thin film transistor (transistor substrate) according to this embodiment is applied as a switching element or a driving element of a display panel or a driving driver, it is possible to improve the product yield and display a good image quality. An apparatus can be realized.

<Second Embodiment>
Next, a second embodiment of the transistor substrate and the manufacturing method thereof according to the present invention will be described.
FIG. 10 is a schematic sectional view showing a second embodiment of the transistor substrate according to the present invention. FIG. 11 is a process flow showing an example of a method for manufacturing a transistor substrate according to the second embodiment. Here, the description of the same configuration and manufacturing process as those of the first embodiment will be simplified. FIG. 12 is a diagram showing measurement results of element characteristics (Vg-Id characteristics) of the thin film transistor according to the second embodiment. Here, as in the first embodiment described above, in a plurality of n-channel amorphous silicon thin film transistors (n-ch TFTs) manufactured using the manufacturing method according to the second embodiment, the channel ratio W / L = Vg-Id characteristics when the drain-source voltage Vds is set to 10V.

  As shown in FIG. 10, the thin film transistor TFT according to the second embodiment has an element structure equivalent to that of the first embodiment described above, and the source and drain electrodes 17 are formed of a metal layer having low film stress. It is characterized by being. Specifically, as shown in the process flow of FIG. 11, for example, chromium (Cr) is applied as the source and drain metal layers constituting the source and drain electrodes 17 in the low stress source and drain metal film forming step S207. When the film is formed with a film thickness of 100 nm (1000 mm), the film stress is set to 700 MPa or less, preferably 500 to 300 MPa. Usually, the film stress of the source and drain metal layers to which chromium (Cr) is applied is set to 1500 MPa or more.

  As shown in the process flow of FIG. 11, the method for manufacturing the thin film transistor TFT according to the second embodiment performs the same manufacturing steps (S201 to S206) as those in the first embodiment, and then forms a channel on the amorphous silicon semiconductor layer 14x. After forming the protective layer 15, a highly doped semiconductor layer 16 x is formed on the substrate 11.

  Next, in a low stress source / drain metal film forming step S <b> 207, a source / drain metal layer having a low film stress is formed on the substrate 11. Specifically, for example, the gas pressure in the chamber is set to 20 mTorr, and the PVD method is used to form the source and drain metal layers 17x made of chromium (Cr) with a film thickness of about 100 nm (1000 Å). According to such manufacturing conditions, the film stress of the source / drain metal layer 17x can be set to a relatively low value of about 700 MPa.

  Then, in the source / drain electrode forming step S208, the source / drain electrode 17 of the thin film transistor TFT is formed by patterning the source / drain metal layer 17x into a desired planar shape.

  As shown in FIG. 12, the Vg-Id characteristics of the thin film transistor TFT manufactured by such a manufacturing method are as follows. In the off region, the drain current Id is about 1.0E-12A or about 1.0E-14A. The value is shown. On the other hand, in the ON region, the drain current Id showed a current value of about 1.0E-06A. In addition, the drain current Id tended to change sharply in the switching region from the off region to the on region of the thin film transistor TFT (that is, the gate voltage Vg was near 0 V).

  That is, according to the thin film transistor TFT according to the present embodiment, a substantially constant (stable) minute leakage current (off current) of approximately 1.0E-12A flows during the off operation, and approximately 1.0E− during the on operation. It was found that a substantially constant and relatively high drain current Id of about 06 A flows. It has also been found that the drain current Id flow (current value) switches quickly between the off region and the on region. And the tendency of such Vg-Id characteristic was observed substantially equally in the some thin film transistor TFT to which the manufacturing method concerning this embodiment was applied.

Here, the device characteristics of the thin film transistor manufacturing method (see FIG. 6) according to the comparative example described above and the thin film transistor according to this embodiment are compared and verified.
As shown in the process flow of FIG. 6, in the source / drain metal film forming step S507 of the thin film transistor manufacturing method according to the comparative example described above, the source / drain metal layer 17x having normal film stress is formed. Here, the normal source-drain metal layer 17x is set to have a relatively high film stress. Specifically, for example, the gas pressure in the chamber is set to 3 mTorr, and the PVD method is used to form the source and drain metal layers 17x made of chromium (Cr) with a film thickness of about 100 nm (1000 Å). When the source / drain metal layer 17x made of chromium is formed under such a low gas pressure condition, the film stress becomes a relatively high value of about 1700 MPa.

  When such a metal layer having a relatively high film stress is applied to the source and drain electrodes 17, peeling and cracking between adjacent layers are likely to occur due to heat treatment during manufacturing, heat generation during operation, and the like, resulting in an increase in product yield. As a characteristic line SP2 shown in FIG. 8, there is a problem that the drain current Id becomes unstable and the device characteristics are deteriorated.

  As a result of intensive studies by the inventors through various experiments, as shown in the second embodiment, the film stress of the metal layer applied to the source and drain electrodes 17 of the thin film transistor TFT depends on the element characteristics of the thin film transistor TFT. It was found to be closely related to (Vg-Id characteristics).

  Therefore, in the thin film transistor according to the second embodiment, the film stress of the source and drain electrodes 17 is set to a value lower than usual. As a result, peeling of the source and drain electrodes 17 from adjacent layers and generation of cracks can be suppressed to improve the product yield, and as shown in FIG. 12, the characteristic line SP1 is shown in FIG. Furthermore, device characteristics that approximate the ideal behavior of the Vg-Id characteristics can be obtained. Therefore, even when the thin film transistor (transistor substrate) according to this embodiment is applied as a switching element or a driving element of a display panel or a driving driver, it is possible to improve the product yield and display a good image quality. An apparatus can be realized.

  In the present embodiment, the comparative verification is performed for the case where chromium (Cr) is applied as the source and drain electrodes 17, but the present invention is not limited to this. That is, the present invention applies other conductive materials and film forming conditions as long as the source and drain electrodes of the thin film transistor are formed using a metal layer or conductive layer having a lower film stress than usual. It goes without saying.

<Third Embodiment>
Next, a third embodiment of the transistor substrate and the manufacturing method thereof according to the present invention will be described.
FIG. 13 is a process flow showing an example of a method for manufacturing a transistor substrate according to the third embodiment. Here, the description of the manufacturing steps equivalent to those of the first and second embodiments described above will be simplified.

  The transistor substrate according to the third embodiment has an element structure having the characteristics of both the first and second embodiments described above. That is, the thin film transistor TFT according to this embodiment is formed in the lower layer of the channel protective layer 15 in the semiconductor layer 14 of the thin film transistor TFT and between the source and drain electrodes 17 as shown in the first embodiment. The region where the side wall portion is exposed (and the vicinity thereof) is oxidized by oxygen plasma treatment. In the thin film transistor TFT according to this embodiment, as shown in the second embodiment, the source and drain electrodes 17 of the thin film transistor TFT are formed of a metal layer having low film stress.

  Then, as shown in FIG. 13, the manufacturing method of the thin film transistor having such an element structure is similar to the first and second embodiments described above, and after the manufacturing steps S301 to S306, the low stress source, drain metal The film forming step S307 and the source / drain electrode forming step S308 are executed to pattern and form the source / drain electrodes 17 made of a low stress metal layer. In addition, as shown in FIG. 13, the manufacturing method according to the present embodiment performs the oxygen plasma treatment step S310 after the source / drain electrode formation step S308 and the highly doped semiconductor layer / semiconductor layer formation step S309, The side wall portion of the patterned semiconductor layer 14 is oxidized using the drain electrode 17 as a mask.

  Thus, since the transistor substrate and the manufacturing method thereof according to the third embodiment have the characteristics of the first and second embodiments described above, the device characteristics of the thin film transistor can be improved. Therefore, even when the thin film transistor (transistor substrate) according to this embodiment is applied as a switching element or a driving element of a display panel or a driving driver, it is possible to improve the product yield and display a good image quality. An apparatus can be realized.

  In the first to third embodiments described above, a specific element structure and manufacturing method of a channel stopper type thin film transistor having a channel protective layer on a semiconductor layer as a transistor substrate according to the present invention will be described. did. The present invention is not limited to this, and the yield of products can be improved by applying the same element structure and manufacturing method to a channel etching type thin film transistor that does not include a channel protective layer on a semiconductor layer. In addition, a display device with good image quality can be realized.

<Application example to light emitting device>
Next, a light emitting device (display device) and a pixel to which the transistor substrate according to each embodiment described above can be applied will be described. Here, in the application examples shown below, the display panel has a configuration in which a plurality of pixels each having an organic electroluminescence element (organic EL element) are two-dimensionally arranged, and each pixel has a luminance gradation corresponding to image data. A case where the transistor substrate of the present invention is applied to an organic EL display panel that displays image information by performing a light emitting operation will be described. The present invention is not limited to this application example, and may be applied to a display panel that displays image information by another display method such as a liquid crystal display panel.

  FIG. 14 is a schematic configuration diagram showing a first configuration example of a display device to which the transistor substrate according to the present invention is applied, and FIG. 15 shows a second configuration of the display device to which the transistor substrate according to the present invention is applied. It is a schematic block diagram which shows a structural example. 14A and 15A are schematic configuration diagrams of the display device according to each configuration example, and FIGS. 14B and 15B are applied to the display device according to each configuration example. 2 is an equivalent circuit diagram of a pixel. In the second configuration example, the description of the same configuration as the first configuration example will be simplified.

(First configuration example)
As shown in FIG. 14A, the display device 100 according to the first configuration example includes at least a display panel 110 in which a plurality of pixels PIX are two-dimensionally arranged, and each pixel PIX in a selected state. A selection driver (selection drive circuit) 120 and a data driver (signal drive circuit) 130 for supplying gradation signals corresponding to image data to each pixel PIX are provided. Here, the selection driver 120 and the data driver 130 for driving the display panel 110 have a circuit configuration to which a thin film transistor is applied, and the elements shown in the first to third embodiments described above as the thin film transistor. A structure (or an element structure manufactured using a manufacturing method) can be applied.

  For example, as shown in FIG. 14B, the pixels PIX arranged in the display panel according to this configuration example include a light emission drive circuit DC and an organic EL element OEL, and a current corresponding to image data by the light emission drive circuit DC. A light emission driving current having a value is generated and supplied to the organic EL element OEL, thereby causing the organic EL element OEL to emit light at a predetermined luminance gradation corresponding to the image data.

  For example, as shown in FIG. 14B, the light emission drive circuit DC includes transistors Tr11 and Tr12 and a capacitor Cs. The transistor Tr11 has a gate terminal connected to the selection line Ls, a drain terminal connected to the data line Ld, and a source terminal connected to the contact N11. The transistor Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the high-potential power supply voltage Vsa, and a source terminal connected to the contact N12. The capacitor Cs is connected to the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr12.

  Here, an n-channel thin film transistor is applied to each of the transistors Tr11 and Tr12, and an element structure (or an element structure manufactured using a manufacturing method) as described in the first to third embodiments described above is used. Can be applied. Note that if the transistors Tr11 and Tr12 are p-channel transistors, the source terminal and the drain terminal are opposite to each other. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. It is.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N12 of the light emission drive circuit DC, and a cathode terminal (cathode electrode) connected to a low potential reference voltage Vsc (for example, the ground voltage Vgnd). Yes.

  The selection line Ls connected to the pixel PIX is connected to the selection driver 120 described above, and the selection voltage Vsel of the selection level or the non-selection level is applied at a predetermined timing. The data line Ld is connected to the data driver 130 described above, and a gradation signal (gradation voltage) Vdata corresponding to the image data is applied to the pixel PIX set to the selected state by the selection voltage Vsel. Is done.

  In the display driving operation of the display device including the pixel PIX having such a circuit configuration, first, a selection voltage Vsel of a selection level (high level) is applied from the selection driver 120 to the selection line Ls in the selection period. As a result, the transistor Tr11 is turned on to set the pixel PIX to the selected state. In synchronization with this timing, the gradation voltage Vdata having a voltage value corresponding to the image data is applied from the data driver 130 to the data line Ld, so that the potential corresponding to the gradation voltage Vdata is obtained via the transistor Tr11. The voltage is applied to the contact N11 (gate terminal of the transistor Tr12).

  As a result, the transistor Tr12 is turned on in a conductive state corresponding to the gradation voltage Vdata, a light emission driving current having a predetermined current value flows between the drain and the source, and the organic EL element OEL has the gradation voltage Vdata (that is, the image). Light emission at a luminance gradation corresponding to the data. At this time, charges are stored (charged) in the capacitor Cs connected between the gate and source of the transistor Tr12 based on the gradation voltage Vdata applied to the contact N11.

  Next, in the non-selection period, by applying the selection voltage Vsel of the non-selection level (low level) from the selection driver 120 to the selection line Ls, the transistor Tr11 is turned off and the pixel PIX is set to the non-selection state. To do. As a result, the charge accumulated in the capacitor Cs (that is, the potential difference between the gate and the source) is held, and a voltage corresponding to the gradation voltage Vdata is applied to the gate terminal of the transistor Tr12. Therefore, a light emission drive current having a current value equivalent to that in the light emission operation state flows between the drain and source of the transistor Tr12, and the organic EL element OEL continues to emit light. Then, the desired image information is displayed by sequentially executing such a display driving operation for every pixel PIX two-dimensionally arranged on the display panel 110, for example, for each row.

(Second configuration example)
As illustrated in FIG. 15A, the display device 100 according to the second configuration example includes at least a display panel 110, a selection driver 120, a data driver 130, and a power supply driver 140. That is, the display device 100 according to this configuration example includes a power supply driver 140 in addition to the configuration shown in the first configuration example. Here, similarly to the first configuration example described above, the selection driver 120, the data driver 130, and the power supply driver 140 for driving the display panel 110 have a circuit configuration to which a thin film transistor is applied. The element structure as shown in the first to third embodiments (or an element structure manufactured using a manufacturing method) can be applied.

  The light emission drive circuit DC provided in the pixels PIX arranged in the display panel according to this configuration example includes transistors Tr21 to Tr23 and a capacitor Cs as shown in FIG. 15B, for example. The transistor Tr21 has a gate terminal connected to the selection line Ls, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N21. The transistor Tr22 has a gate terminal connected to the selection line Ls, a source terminal connected to the data line Ld, and a drain terminal connected to the contact N22. The transistor Tr23 has a gate terminal connected to the contact N21, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N22. The capacitor Cs is connected to the gate terminal (contact N21) and the source terminal (contact N22) of the transistor Tr23.

  Here, also in this configuration example, the n-channel type thin film transistor is applied to each of the transistors Tr21 to Tr23, and the element structure (or manufacturing method) as shown in the first to third embodiments is used. The manufactured element structure) can be applied. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr23, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. It is.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N22 of the light emission drive circuit DC, and a cathode terminal (cathode electrode) connected to a low potential reference voltage Vsc (for example, ground voltage Vgnd). Yes. The power supply line La connected to the pixel PIX is connected to the power supply driver 140 described above, and the power supply voltage Vsa of the light emission level or the non-light emission level is applied at a predetermined timing.

  In the display drive operation of the display device including the pixel PIX having such a circuit configuration, first, the selection driver 120 applies the selection voltage Vsel of the selection level (high level) to the selection line Ls in the selection period. At the same time, when the power supply driver 140 applies the power supply voltage Vsa of the non-light emission level (voltage level equal to or lower than the reference voltage Vsc; for example, negative voltage) to the power supply line La, the transistors Tr21 and Tr22 are turned on to select the pixel PIX Set to state. In synchronization with this timing, the gradation voltage Vdata having a negative voltage value corresponding to the image data is applied from the data driver 130 to the data line Ld, so that the gradation voltage Vdata is determined via the transistor Tr22. The potential is applied to the contact N22 (the source terminal of the transistor Tr23).

  As a result, the transistor Tr23 is turned on, and the write current corresponding to the potential difference generated between the gate and the source of the transistor Tr23 is transferred from the power supply line La to the data line Ld via the transistor Tr23, the contact N22, and the transistor Tr22. Flowing. At this time, a charge corresponding to the potential difference generated between the contacts N21 and N22 is accumulated in the capacitor Cs.

  Here, the power supply line La is set so that the power supply voltage Vsa equal to or lower than the reference voltage Vsc is applied and the write current is drawn from the pixel PIX in the direction of the data line Ld. As a result, the potential applied to the anode (contact N22) of the organic EL element OEL is lower than the cathode potential (reference voltage Vsc). Therefore, no current flows through the organic EL element OEL, and the organic EL element OEL Does not emit light (non-emission operation). Such a writing operation is sequentially executed for each row for all the pixels PIX two-dimensionally arranged on the display panel 110.

  Next, in the non-selection period, by applying the selection voltage Vsel of the non-selection level (low level) from the selection driver 120 to the selection line Ls, the transistors Tr21 and Tr22 are turned off and the pixel PIX is not selected. Set to. As a result, the charge accumulated in the selection period is held in the capacitor Cs, so that the transistor Tr23 is kept on. Then, by applying a power supply voltage Vsa of a light emission level (a voltage level higher than the reference voltage Vsc) from the power supply driver 140 to the organic EL element OEL from the power supply line La via the transistor Tr23 and the contact N22. A predetermined light emission drive current flows.

  At this time, the charge (voltage component) accumulated in the capacitor Cs corresponds to a potential difference in the case where a write current corresponding to the gradation voltage Vdata is caused to flow in the transistor Tr23. Therefore, the light emission drive current flowing in the organic EL element OEL is The current value is substantially equal to the write current. As a result, the organic EL element OEL of each pixel PIX emits light with a luminance gradation corresponding to the image data (gradation voltage Vdata) written during the writing operation, and desired image information is displayed on the display panel 110. .

  As described above, the transistor substrate (thin film transistor) described in each of the above-described embodiments is applied as a driving driver that constitutes a display device, or a switching element or a driving element of a plurality of pixels (light emission driving circuits) arranged in a display panel. As a result, the yield of the product can be improved and a good display image quality can be realized.

  The light emission drive circuit DC shown in the first and second configuration examples (FIGS. 14 and 15) described above applies the gradation voltage Vdata having a voltage value corresponding to the image data to each pixel PIX. A circuit corresponding to a voltage designation type gradation control method in which a light emission driving current corresponding to image data is supplied to a light emitting element (organic EL element OEL) of each pixel PIX to perform light emission operation (display operation) at a desired luminance gradation. The case where the configuration is provided has been described. The display device to which the transistor substrate according to the present invention is applicable is not limited to this. For example, by supplying a gradation current having a current value corresponding to image data to each pixel PIX, Even if it has a light emission drive circuit having a circuit configuration corresponding to a current designation type gradation control method in which a light emission drive current corresponding to image data is supplied to a light emitting element to perform light emission operation at a desired luminance gradation Good. Note that the light emission drive circuit DC shown in the second configuration example has a circuit configuration corresponding to both the voltage designation type and current designation type gradation control methods.

<Application examples to electronic devices>
Next, electronic devices to which the light-emitting device (display device) including the transistor substrate (thin film transistor) according to each embodiment described above is applied will be described with reference to the drawings.

  The display device 100 including the display panel 110 and the driving drivers (the selection driver 120, the data driver 130, and the power supply driver 140) as described above includes various types such as a digital camera, a thin television, a mobile personal computer, and a mobile phone. It can be favorably applied as a display device for electronic equipment.

  FIG. 16 is a perspective view illustrating a configuration example of a digital camera to which the light emitting device according to the present invention is applied, and FIG. 17 is a perspective view illustrating a configuration example of a thin television to which the light emitting device according to the present invention is applied. 18 is a perspective view showing a configuration example of a mobile personal computer to which the light emitting device according to the present invention is applied, and FIG. 19 is a diagram showing a configuration example of a mobile phone to which the light emitting device according to the present invention is applied. It is.

  In FIG. 16, a digital camera 210 is roughly divided into a main body 211, a lens unit 212, an operation unit 213, and a display unit 214 to which the display device 100 including the transistor substrate described in each of the above embodiments is applied. And a shutter button 215. According to this, the element characteristics of the thin film transistor in the display unit 214 can be improved, the yield of products can be improved, and a good display image quality can be realized.

  In FIG. 17, the thin television 220 is roughly divided into a main body 221, a display unit 222 to which the display device 100 including the transistor substrate described in each of the above embodiments is applied, and an operation controller (remote controller). 223. According to this, the device characteristics of the thin film transistor in the display unit 222 can be improved, the yield of the product can be improved, and a good display image quality can be realized.

  In FIG. 18, the personal computer 230 roughly includes a main body 231, a keyboard 232, and a display unit 233 to which the display device 100 including the transistor substrate described in each of the above embodiments is applied. . Even in this case, the element characteristics of the thin film transistor in the display portion 233 can be improved, the yield of products can be improved, and a good display image quality can be realized.

  In FIG. 19, the mobile phone 240 is roughly divided into a display to which the display unit 100 including the operation unit 241, the earpiece 242, the mouthpiece 243, and the transistor substrate described in each of the above embodiments is applied. Part 244. Even in this case, the element characteristics of the thin film transistor in the display portion 244 can be improved, the yield of products can be improved, and a good display image quality can be realized.

  In each of the electronic devices described above, the case where the light emitting device including the transistor substrate according to the present invention is applied as a display device (display device) has been described. However, the present invention is not limited to this. A light emitting device including a transistor substrate according to the present invention includes, for example, a light emitting element array in which a plurality of pixels having light emitting elements are arranged in one direction, and light emitted from the light emitting element array according to image data on a photosensitive drum. It may be applied to an exposure apparatus that performs exposure by irradiating.

DESCRIPTION OF SYMBOLS 11 Substrate 12 Insulating film 13 Gate electrode 14 Semiconductor layer 15 Channel protective layer 16 Highly doped semiconductor layer 17 Source and drain electrode 100 Display device 110 Display panel 120 Selection driver 130 Data driver 140 Power driver TFT Thin film transistor PIX Pixel DC Light emission drive circuit OEL Organic EL element Tr11, Tr12, Tr21 to Tr23 Transistor

Claims (4)

A substrate,
On the substrate, a gate electrode, a semiconductor layer facing the gate electrode through an insulating film, and a source electrode and a drain electrode facing each other across a channel region formed in the semiconductor layer with a film stress of 700 MPa or less A transistor in which at least a side wall portion of the semiconductor layer between the source electrode and the drain electrode is oxidized to be non-conductive, and
A transistor substrate comprising: The transistor substrate further comprises a light emitting element and a light emission driving circuit for driving the light emitting element on the substrate,
The transistor substrate according to claim 1, wherein the light emission driving circuit includes the transistor. Forming a gate electrode on the substrate;
Forming a semiconductor film facing the gate electrode through an insulating film;
Forming a metal layer on the semiconductor layer, patterning the metal layer, and forming a source electrode and a drain electrode having a film stress of 700 MPa or less opposed to each other across the channel region;
Patterning the semiconductor film using the source and drain electrodes as a mask to form a semiconductor layer;
Oxidizing the substrate to render at least the sidewall portion of the semiconductor layer non-conductive;
A method for manufacturing a transistor substrate, comprising: The step of patterning the semiconductor layer is performed using a dry etching method,
4. The method of manufacturing a transistor substrate according to claim 3, wherein the step of oxidizing the substrate is performed by oxygen plasma treatment.

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