JP2011191883A - Method for designing semiconductor device, and standard cell to be used for the method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve wiring properties and reduce a layout size. <P>SOLUTION: A standard cell 1 is a cell having a rectangular area and is composed of a signal wiring area 3 in which an input terminal 6 and an output terminal 7 for a logical circuit exist, and power supply wiring areas 2 which exist on both sides in the longitudinal direction of the standard cell 1 through the signal wiring area 3, respectively, and in which power supply terminals 8 for the logical circuit are extended from the signal wiring area 3 and included. The power supply wiring areas 2 respectively include areas 9 capable of removing parts of the power supply terminals 8 located on both sides in the longitudinal direction of the standard cell 1. When a plurality of standard cells 1 are arrayed adjacently in vertical and horizontal directions like rows, a power supply wiring 10 can be moved within a range X in which two adjacent power supply wiring areas 2 are combined in the longitudinal direction of the standard cell 1. The length of the power supply terminal 8 can be changed by removing the area 9 according to the position of the power supply wiring 10. A range Y of the signal wiring area 3 in the longitudinal direction of the standard cell 1 can be expanded/reduced according to congestion prediction of signal wirings. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor device, and more particularly to a method for designing a semiconductor device using a standard cell (standard cell) such as a logic cell.

  With the recent miniaturization and enlargement of semiconductor devices, the design techniques have become more complex. Cell-based design techniques are often used for large-scale circuit design. In cell-based design, basic gates and frequently used logic circuit patterns are registered in advance as standard cells, and a plurality of standard cells are arranged in rows and wiring is performed between the standard cells.

  In such cell-based layout design, various methods have been proposed in order to improve yield and reduce costs.

  In the method described in Patent Document 1, a standard cell including a pair of parallel power supply lines is arranged. For this standard cell, a region where no inter-element wiring exists in the same wiring layer as the power supply wiring between a pair of power supply wirings is defined as a wiring channel, and this region is set in a predetermined range in a direction perpendicular to the pair of power supply wirings. It can be extended and retracted. The wiring channel region is expanded and contracted based on the number of wiring tracks passing through the wiring channel in a direction parallel to the power supply wiring. Therefore, after arranging the standard cells, the standard cells are roughly wired without specifically determining the wiring route. Depending on the number of inter-cell connection wires at this time, the power supply wires are moved to the outside of the cells to increase the cell size, or the power supply wires are moved to the inside of the cells to reduce the cell size. Thereafter, the schematic wiring is changed to detailed wiring in consideration of a specific wiring route.

  As described above, in Patent Document 1, the position of the power supply wiring of the standard cell is changed to expand and contract the wiring region in the cell, thereby improving the wiring property.

  Further, in the first method described in Patent Document 2, signal line wiring is performed after a logic cell including power supply wiring is arranged on a cell shelf. At this stage, the density of the wiring is grasped and the wiring congestion point is specified. Next, the power supply wiring of the upper layer is generated, but in the portion where the signal line wiring is dense, the power supply wiring that is sparse is generated so that the wiring congestion is not deteriorated by the power supply wiring of the upper layer. . In addition, since there is a margin in the wiring area at the portion where the signal line wiring is sparse, a higher-level power supply wiring is generated so as to reinforce the power supply wiring. As described above, the higher-level power supply wiring is generated by increasing or decreasing the density according to the congestion state of the signal line wiring.

  Further, Patent Document 2 proposes the following second method. First, a plurality of hierarchies of power supply lines are generated in the cell shelf. Subsequently, the location of the logic cell is predicted avoiding the power supply wiring of each hierarchy. Further, the signal line congestion is predicted from the connection information between the logic cells predicted to be arranged. The logic cell arrangement is changed at the location where wiring is predicted to occur. This change widens the arrangement interval between the logic cells, and avoids wiring congestion. That is, the cell arrangement is optimized by distributing the logic cells at the locations where the signal line wiring is expected to be concentrated.

JP-A-6-85062 (see FIGS. 1-2, paragraphs [0033]-[0038]) JP 2006-294744 A (see FIGS. 1-8, paragraphs [0023]-[0039])

  In a layout in which standard cells are arranged in a row, the wiring region is partitioned by the power supply wiring provided in the standard cell, so that wiring cannot be performed or a dead space is created due to a part of the wiring congestion. The present inventors considered whether this could be alleviated.

  However, in Patent Document 1 described above, since the power supply wiring included in the standard cell is moved, the power supply position can be adjusted only for each cell shelf or wiring channel in which the standard cell is arranged. Therefore, local wiring congestion is alleviated, but at the same time, a sparse part of the wiring area (dead space or the like) occurs in the entire layout. Further, since the cell size changes due to the movement of the power supply wiring, the cell size correction and rewiring are required when the standard cell is moved to another cell shelf.

  On the other hand, the second method described in Patent Document 2 is a method of distributing logic cells (standard cells) at locations where signal line wiring is expected to be concentrated. Occurs, and there is a problem in that the number of relocation steps and the layout size increase. In the first method, the power supply wiring to be adjusted is not the power supply wiring in the lowermost wiring layer but the power supply wiring in the upper layer. Since the area of the logic cell is regulated by the power supply position of the lowest wiring layer, this method cannot reduce the area of the logic cell itself.

  One aspect according to the present invention is a standard cell having a rectangular area, where a signal wiring area in which an input terminal and an output terminal of a logic circuit are present, and both sides in the longitudinal direction of the standard cell across the signal wiring area Each of the power supply terminals of the logic circuit extends from the signal wiring area and includes a power supply wiring area, and each of the power supply wiring areas is located at both ends in the longitudinal direction of the standard cell. Provided is a method for designing a semiconductor device using a standard cell including a region where a part of a terminal can be removed.

This method includes a first step of preparing the standard cell, and
A second step of arranging a plurality of the standard cells adjacent to each other in the longitudinal direction of the standard cells and in the direction intersecting the longitudinal direction,
A third step of virtually wiring a signal line in the signal wiring region of each standard cell and confirming the wiring congestion degree of each standard cell at this time,
A fourth step of comparing the degree of wiring congestion between adjacent standard cells in the longitudinal direction of the standard cells;
According to the result of comparing the degree of wiring congestion, the range in the longitudinal direction of the signal wiring area of each standard cell adjacent to the standard cell in the longitudinal direction is adjusted, and only the signal line is applied to this adjusted range. A fifth step of determining as a prohibited area where wiring of wiring is prohibited;
A sixth step of inserting the power supply wiring of the first wiring layer between the standard cells adjacent to each other in the longitudinal direction of the standard cell, excluding the determined prohibited region;
And a seventh step of performing signal line wiring between standard cells using the determined prohibited area.

  According to such a method, the sizes of the power supply wiring area and the signal wiring area can be adjusted according to the wiring congestion degree of each standard cell, so that local wiring congestion can be reduced. For this reason, the wiring property is improved and the wiring limit can be relaxed.

  Furthermore, the power supply wiring can be bent by adjusting the power supply wiring region between cells adjacent in the longitudinal direction of the standard cell. Thereby, the wiring density is improved and the wiring dead space can be reduced.

  Furthermore, since the cell configuration is such that a part of the power supply terminals provided in the standard cell can be removed, the power supply terminals can be reduced in the standard cell with a low wiring congestion degree. Thereby, the cell size can be varied, and the layout area can be easily reduced.

According to the present invention, the wiring property can be improved and the layout size can be reduced.

1 is a schematic diagram of a standard cell used in a semiconductor device design method according to an embodiment of the present invention. The image figure when arrange | positioning the standard cell shown in FIG. 1 in a line form. FIG. 3 is a diagram for explaining a wiring design procedure (that is, a layout design method for a semiconductor device) using the standard cell shown in FIG. The figure which represented typically the design method in step S23 and S24 of FIG. The figure which showed typically the design method in step S24 and S25 of FIG. The figure which showed typically another example of the design method in step S24 and S25 of FIG. The figure explaining another example of the design method in step S24 and S25 of FIG. The typical top view which shows the case where the some standard cell by this invention is arranged so that it may cross | intersect a horizontal direction and a vertical direction (cross layout). The figure which shows a mode that the location which can isolate | separate a power supply terminal was deleted from the layout shape of the standard cell as shown in FIG. 2 in the cross layout of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram of a standard cell used in a method for designing a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 1, the standard cell 1 of the present embodiment defines a rectangular cell region. The cell region includes a power supply wiring region 2 positioned at both ends in the longitudinal direction of the cell region, and a signal wiring region 3 positioned between the power supply wiring regions 2. In the signal wiring region 3, there are an input terminal 6 and an output terminal 7 that can be connected to the P-type diffusion layer 4 and the N-type diffusion layer 5 constituting the CMOS transistor. Further, in each power supply wiring region 2, a power supply terminal 8 exists along the longitudinal direction of the standard cell 1, and the power supply terminal 8 extends into the signal wiring region 3 and is connected to the P-type diffusion layer 4 or the N-type diffusion. Connection with layer 5 is possible.

  The input terminal 6, the output terminal 7, and the power supply terminal 8 exist in the same wiring layer. In particular, the standard cell proposed by the present application uses the second wiring layer directly above the lowermost layer (first wiring layer) among the multilayer wiring layers formed on the semiconductor substrate.

  The power supply wiring region 2 is provided with a power terminal separable portion 9. The power terminal separable portion 9 is an area in which a part of the power terminal 8 existing on the extreme end side in the longitudinal direction of the standard cell 1 can be separated with respect to the longitudinal direction of the standard cell 1.

  FIG. 2 is an image diagram when the standard cells 1 shown in FIG. 1 are arranged in a line.

  In the first wiring layer on the semiconductor substrate, a plurality of power supply wirings 10 extending in parallel along a direction orthogonal to the longitudinal direction of the standard cell 1 (lateral direction in FIG. 2) are arranged. Further, in the second wiring layer, A large number of standard cells 1 having the same configuration are arranged in the horizontal direction between adjacent power supply wirings 10. Further, the power supply wiring 10 extending in the horizontal direction is connected to the power supply terminal 8 in each standard cell 1.

  When the standard cells 1 are arranged in two horizontal rows on the second wiring layer, as shown in FIG. 2, the two standard cells 1 are arranged adjacent to each other in the longitudinal direction of the standard cell 1. At this time, since the power supply wiring regions 2 in the standard cells 1 are adjacent to each other with the cell boundary 11 in between, the power supply terminals 8 in the two adjacent power supply wiring regions 2 can be connected at the cell boundary 11. . Further, the power supply wiring 10 is movable within a range in which two adjacent power supply wiring regions 2 are combined with respect to the longitudinal direction of the standard cell 1 (power supply wiring movable range X in FIG. 2). It is possible to change the length of the power terminal 8 by removing the power terminal separable portion 9 according to the position of the power wiring 10.

  Further, the range of the signal wiring region 3 in the longitudinal direction of the standard cell 1 (signal wiring possible range Y in FIG. 2) is determined with a minimum width necessary and sufficient to constitute a CMOS transistor. Can be expanded according to Simultaneously with this expansion, the input terminal 6 and the output terminal 7 are also extended.

  Next, a wiring design procedure (that is, a layout design procedure for a semiconductor device) using the standard cell 1 as described above will be described with reference to FIGS. This wiring is performed using an automatic placement and routing tool that determines the placement of standard cells and the wiring path between terminals. The automatic placement and routing tool is composed of a program for executing the arithmetic processing by a computer, and is used after being previously installed in a computer for designing a semiconductor device. The standard cell 1 configured as described above is also stored in the computer in which the automatic placement and routing tool is installed.

  Using such an automatic tool, first, the standard cells 1 shown in FIG. 1 are arranged side by side in a direction orthogonal to the longitudinal direction of the standard cells 1. A plurality of columns of standard cells 1 arranged in the horizontal direction in FIG. 1 are provided in parallel. At this time, as shown in FIG. 2, the two standard cells 1 are arranged adjacent to each other in the longitudinal direction of the standard cell 1.

  When the arrangement of the standard cells (step S21 in FIG. 3) is completed in this way, wiring connected between the signal wiring areas 3 of the arranged standard cells 1 is temporarily generated. And the wiring congestion degree of each standard cell 1 at this time is confirmed and stored (step S22 in FIG. 3). The wiring congestion level is, for example, the area of wiring that is planarly occupied in the initially set signal wiring possible range Y in the standard cell 1, that is, wiring density.

  Subsequently, the wiring congestion degree is compared between two standard cells 1 adjacent in the longitudinal direction of the standard cell 1 (step S23 in FIG. 3). The surface portion of the semiconductor substrate in which standard cells 1 are arranged in a horizontal row is called a cell shelf, and a frame defined by a plurality of standard cells 1 arranged in a horizontal row is called a shelf frame (Row).

  The signal wiring possible range Y is adjusted according to the comparison result in step S23, and this adjusted range is determined as a wiring channel region where only the inter-cell signal wiring is performed. In other words, the inside of the determined wiring channel region is a region where wiring of the power supply wiring 10 is prohibited (step S24 in FIG. 3). In the adjustment of the signal wiring possible range Y, the signal wiring possible range Y of the standard cell 1 on the side where the wiring congestion is dense is widened, and the signal wiring possible range Y of the standard cell 1 on the side where the wiring congestion is sparse is The initial minimum width is used. When the signal wiring possible range Y is expanded because the wiring congestion degree is high, the original design size of the standard cell 1 is removed by removing the power terminal separable portion 9 and extending the remaining power terminal 8 to the cell boundary 11. Can be handled without increasing the size.

  Thereafter, the power supply wiring 10 of the first wiring layer is inserted between the standard cells 1 adjacent to each other in the longitudinal direction of the standard cell 1 at a location excluding the determined wiring channel region (step S25 in FIG. 3).

  Finally, wiring connection is made between the standard cells 1 using the wiring channel region determined as described above (step S26 in FIG. 3).

  FIG. 4 schematically shows the design method in steps S23 and S24 of FIG.

  As shown in the left side view of FIG. 4A, it is assumed that the wiring congestion degree of one standard cell 1 is sparse and the wiring congestion degree of the other standard cell 1 is dense in adjacent cell shelves. In this case, as shown in the right side view of FIG. 4A, for the signal wiring region 3 of one standard cell, the signal wiring possible range Y is set to the minimum width that is initially set narrow, and the other standard cell In the signal wiring region 3, the signal wiring possible range Y is widened by removing the power terminal separation point 9 on the cell boundary side. Further, in the power wiring region 2 on the side opposite to the cell boundary in the signal wiring region 3 of one standard cell, it is possible to delete the power supply terminal separable portion 9. The power supply wiring region 2 on the side opposite to the cell boundary 11 of the signal wiring region 3 of the other standard cell is defined so as to be in contact with the region where the power supply wiring 10 is arranged.

  As shown in the left side view of FIG. 4B, it is assumed that the wiring congestion degrees of both standard cells 1 are dense in adjacent cell shelves. In this case, as shown in the right side view of FIG. 4B, the signal wiring possible range Y is increased by removing the power terminal separation point 9 on the cell boundary side in the signal wiring regions 3 of both standard cells. Widened. In addition, the power supply wiring region 2 on the side opposite to the cell boundary 11 of the signal wiring region 3 of each standard cell is defined so as to be in contact with the region where the power supply wiring 10 is arranged.

  As shown in the left side view of FIG. 4C, it is assumed that the wiring congestion degree of both standard cells 1 is sparse in adjacent cell shelves. In this case, as shown in the right side view of FIG. 4C, the signal wiring possible range Y is set to the minimum width that remains narrow at the beginning of setting for the signal wiring regions 3 of both standard cells. Further, in the power wiring region 2 on the side opposite to the cell boundary 11 in the signal wiring region 3 of each standard cell, it is possible to delete the power terminal separable portion 9.

  Further, FIGS. 5 and 6 schematically show examples of design methods in steps S24 and S25 of FIG.

  As described above, in step S24, the signal wiring possible range Y is adjusted according to the density of the virtual wiring provided in each standard cell 1, and the wiring channel region, that is, the power supply wiring prohibited region is determined. At this time, in the example of FIG. 5, the power supply of the first wiring layer is provided at a location excluding the wiring area determination frame 12 prior to wiring to the determined wiring channel area (hereinafter referred to as the wiring area determination frame 12). The wiring 10 is disposed. Thereafter, the empty area after the power supply wiring 10 is arranged is reset as a wiring channel area to which the signal wiring can be connected. Alternatively, after the signal wiring is arranged in the wiring area determination frame 12, the power supply wiring 10 may be arranged in a place excluding the wiring area determination frame 12.

  On the other hand, as in the example shown in FIG. 6, the entire area obtained by subtracting the wiring area determination frame 12 from the shelf frame 13 may be defined as the power supply wiring 10. In this case, after signal wirings other than the power supply wiring are arranged in the wiring area determination frame 12, the entire area other than the wiring area determination frame 12 becomes the power supply wiring 10, so that the power supply arrangement can be omitted at the time of wiring with the automatic arrangement and wiring tool. .

  Moreover, wiring as shown in FIG. 7 can also be implemented. As shown in this figure, in the second wiring layer, two standard cells 1 are arranged adjacent to each other in the longitudinal direction of the standard cell 1. Thus, the power supply terminals 8 in the adjacent standard cells 1 are connected at the cell boundary 11. In the case of this example, as shown in FIG. 5, if there is a wiring free area near the cell boundary 11, the input terminal 6 and the output terminal 7 in each adjacent standard cell 1 are brought close to the cell boundary 11. I'll extend it. Further, the position of the power supply wiring 10 is changed to the signal wiring possible range Y side in each of the power supply wiring areas 2 adjacent to each other with the cell boundary 11 in between, and the end of the input terminal 6 or the output terminal 7 located near the cell boundary 11 The input signal line 14 or the output signal line 15 is disposed at the portion.

  In this way, the signal line that can be connected to the input terminal 6 or the output terminal 7 while extending the input terminal 6 or the output terminal 7 to an area vacated near the cell boundary 11 by reducing the signal wiring possible range Y. When the is provided, the wiring property is improved.

  FIG. 8 is a schematic plan view in the case where a plurality of standard cells 1 are arranged so as to intersect the horizontal direction and the vertical direction (cross layout). As shown in this figure, in the cross layout, the area where the signal lines wired vertically and horizontally cross has a dense wiring, and the wiring density tends to become sparse as the distance from the center crossing area increases. In this case, in the region where the wiring density is sparse, the layout area can be reduced (compaction) by arranging the standard cell 1 from which the power source terminal separable portion 9 is deleted.

  FIG. 9 shows a state where the power supply terminal separable portion 9 is deleted from the layout shape of the standard cell 1 as shown in FIG. FIG. 9A shows a simplified form of the cell layout shown in FIG. 2, but if the power source terminal separable portion 9 of each standard cell 1 is deleted and then combined, FIG. 9B is obtained. As shown, the area occupied by the two standard cells 1 is reduced. The layout area can be reduced by using the standard cell 1 thus resized in a region where the wiring density is sparse in the cross layout or the like as shown in FIG.

  The above-described invention of the present application is particularly effective for improving the wiring property and reducing the layout size in a product that performs an automatic wiring design with a rectangular layout, such as a memory product.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

DESCRIPTION OF SYMBOLS 1 Standard cell 2 Power supply wiring area 3 Signal wiring area 4 P-type diffusion layer 5 N-type diffusion layer 6 Input terminal 7 Output terminal 8 Power supply terminal 9 Power supply terminal separable part 10 Power supply wiring (first wiring layer)
11 Cell boundary 12 Wiring area determination frame 13 Shelf frame 14 Input signal line 15 Output signal line X Power supply wiring movable range Y Signal wiring possible range

Claims (6)

A standard cell having a rectangular region, wherein a signal wiring region in which an input terminal and an output terminal for a logic circuit are present, and the both sides of the standard cell across the signal wiring region, A power supply terminal for a logic circuit includes a power supply wiring area that extends from the signal wiring area, and each of the power supply wiring areas is a part of the power supply terminal located at both ends in the longitudinal direction of the standard cell. A first step of preparing a standard cell including a removable area;
A second step of arranging a plurality of the standard cells adjacent to each other in the longitudinal direction and a direction intersecting the longitudinal direction,
A third step of virtually wiring a signal line to the signal wiring region of each standard cell and confirming the wiring congestion degree of each standard cell at this time,
A fourth step of comparing the wiring congestion degree between the standard cells adjacent in the longitudinal direction of the standard cell;
In accordance with the result of comparing the wiring congestion degree, the range in the longitudinal direction of the signal wiring region of each of the standard cells adjacent to the longitudinal direction of the standard cell is adjusted, and the adjusted range is used as a signal line. A fifth step that is determined as a prohibited area where only the power supply wiring is prohibited and the placement of the power supply wiring is prohibited,
A sixth step of inserting the power wiring of the first wiring layer at a location excluding the determined prohibited area between the standard cells adjacent in the longitudinal direction of the standard cell;
A seventh step of performing signal line wiring between the standard cells using the determined prohibited region;
A method for designing a semiconductor device comprising:   In the fifth step, when adjusting a range in the longitudinal direction of the signal wiring region of each of the standard cells adjacent to the longitudinal direction of the standard cell, the standard cell on the side where the wiring congestion degree is dense is adjusted. The range in the longitudinal direction of the signal wiring region is widened, and the range in the longitudinal direction of the signal wiring region of the standard cell on the side where the wiring congestion degree is sparse is set to an initially set minimum width. Item 2. A method for designing a semiconductor device according to Item 1.   In the fifth step, when the range of the signal wiring region of the standard cell in the longitudinal direction is expanded, the region of the power supply wiring region is removed by removing a region where the part of the power supply terminal can be removed. Item 3. A method for designing a semiconductor device according to Item 2.   3. The design of a semiconductor device according to claim 2, wherein, in the fifth step, a region in the power supply wiring region where a part of the power supply terminal can be removed is removed from the standard cell on the sparse wiring congestion side. Method.   2. The method of designing a semiconductor device according to claim 1, wherein in the sixth step, all of the regions excluding the determined prohibited region are used as power supply wirings.   A standard cell having a rectangular region, wherein the logic circuit is located on both sides in the longitudinal direction of the standard cell, with the signal wiring region where the input terminal and the output terminal of the logic circuit exist, The power supply terminals extend from the signal wiring area and have an inherent power supply wiring area, and each of the power supply wiring areas can remove a part of the power supply terminal located at both ends in the longitudinal direction of the standard cell. A standard cell that contains a region.

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