JP2011186731A - Electronic circuit, control method thereof and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit including an internal memory and capable of improving processing efficiency and power saving during an operation request in a stand-by state. <P>SOLUTION: The electronic circuit 31 includes: a control part 41 capable of accessing an external memory 34 in a normal mode; an internal memory 44 whose power consumption is less than that of the external memory 34; a network I/F 67; second access routes G2, F2 capable of accessing the internal memory 44 from the network I/F 67; and a route switching part 65. In switching from the normal mode to a power saving mode, the route switching part 65 switches a first access route G1 to the external memory 34 to the second access routes G2, F2 in accordance with control of the control part 41 to switch an address space in which an address for the external memory 34 is mapped in the normal mode to an address space for the internal memory 44. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic circuit, a method for controlling the electronic circuit, and an image forming apparatus including the electronic circuit, and more particularly, a technique for reducing power consumption and improving processing efficiency in an electronic circuit having an internal memory in a standby state. About.

  Conventionally, as a technique for reducing power consumption in a standby state of an electronic circuit, for example, in Patent Document 1, when shifting to a standby state, data stored in an external memory connected to the electronic circuit is transferred to the inside of the electronic circuit. A technology for saving power in a memory and reducing power consumption and improving processing efficiency is disclosed.

JP 2007-011449 A

  However, in Patent Document 1, when shifting the state as described above, although a predetermined amount of power consumption can be reduced, there is still room for further power saving in the standby state (power saving mode). Further, there is a need to operate in response to a request from an external network even in a standby state, and it has been desired to improve the processing efficiency at that time.

  The present invention provides a technique for improving processing efficiency and power saving when an operation request is made in a standby state in an electronic circuit having an internal memory.

  An electronic circuit according to a first aspect of the present invention is an electronic circuit that operates in a normal mode and a power saving mode that consumes less power than the normal mode, the controller being capable of accessing an external memory in the normal mode, An internal memory with less power consumption than the external memory, accessed by the control unit in the normal mode and the power saving mode, a network I / F connected to an external network, and in the normal mode, the network I / F A first access path that enables access to the external memory from the network, a second access path that enables access to the internal memory from the network I / F in the power saving mode, and At the time of switching to the power saving mode, the first access is performed according to the control of the control unit. By switching the road to the second access path, and a said address space address for the external memory is mapped in the normal mode, the internal memory toggle its path switching unit to the address space for.

  According to this configuration, in the power saving mode, an internal memory that consumes less power than the external memory can be accessed from the network via the network I / F (interface) instead of the external memory. At this time, since the address space (logical address space) for internal memory is arranged in the address map area (logical address space) for external memory, it is not necessary to change the DMA address of the network I / F. Therefore, it is possible to improve the processing efficiency and power saving when the network requests access to the internal memory (operation request) in the power saving mode (standby state).

According to a second invention, in the electronic circuit of the first invention, the first access path includes a first path selector and an external memory I / F, and the second access path is the first path selector, the path A switching unit and a second path selector, wherein the first path selector is connected to the network I / F, the second path selector is connected to the internal memory, and the path switching unit is When switching to the power saving mode, the switching of the first path selector and the second path selector is controlled to switch the first access path to the second access path.
According to this configuration, the first route selector and the second route selector can be configured with simple circuits.

According to a third invention, in the electronic circuit of the first or second invention, the supply of the clock signal to the external memory I / F is stopped in the power saving mode.
According to this configuration, it is possible to reliably reduce power consumption when data is received in the internal memory via the network I / F in the power saving mode.

A fourth invention is the electronic circuit according to any one of the first to third inventions, wherein the control unit accesses the internal memory in the normal mode, and the internal memory I / O A third access path including F, and a fourth access path for the control unit to access the internal memory in the power saving mode, wherein the low power internal memory I consumes less power than the internal memory I / F. And the fourth access path including / F, and the path switching unit switches the third access path to the third access path according to the control of the control unit when switching from the normal mode to the power saving mode. Switch to 4 access paths.
According to this configuration, in the power saving mode, when the control unit accesses the internal memory, the low power internal memory I / F that consumes less power than the internal memory I / F is used. be able to.

According to a fifth invention, in the electronic circuit of the fourth invention, the fourth access path includes a third path selector, and the third path selector includes the internal memory I / F, the low power internal memory I / F and connected to the internal memory, and selects connection between the internal memory and the internal memory I / F or the low power internal memory I / F, and the path switching unit switches from the normal mode to the power saving mode. When switching to, the low-power internal memory I / F and the third path selector are controlled to switch the third access path to the fourth access path.
According to this configuration, the low-power internal memory I / F and the third path selector can be configured with a simple circuit.

According to a sixth invention, in the electronic circuit of the fifth invention, the second route selector and the third route selector are constituted by a single route selector.
According to this configuration, the configuration of the electronic circuit can be simplified.

According to a seventh aspect, in the electronic circuit according to any one of the fourth to sixth aspects, the supply of the clock signal to the internal memory I / F is stopped in the power saving mode.
According to this configuration, it is possible to further reduce power consumption in the power saving mode.

An eighth invention is the electronic circuit according to any one of the first to seventh inventions, wherein the control unit includes a first control unit that operates in the normal mode and a second control unit that operates in the power saving mode. The first control unit reads the program for the second control unit from the external memory and stores the program in the internal memory when switching from the normal mode to the power saving mode. Start the operation, and then stop its own operation.
According to this configuration, in the power saving mode, the second control unit suitable for the application in the power saving mode can be used, and further power saving can be achieved.

An image forming apparatus according to a ninth aspect is an image forming apparatus that forms an image on a recording medium, and the electronic circuit according to any one of claims 1 to 8 and the control of the electronic circuit. The internal memory I / F is an image processing I / F for processing image data, and the internal memory stores the image data. This is an image processing memory.
According to this configuration, it is possible to improve the processing efficiency at the time of requesting access to the image processing memory of the image forming apparatus from the network in the power saving mode (at the time of requesting operation) and the power saving of the image forming apparatus. it can.

  A control method for an electronic circuit according to a tenth aspect of the present invention is a control method for mode switching of an electronic circuit that operates in a normal mode and a power saving mode that consumes less power than the normal mode. Including a network I / F connected to an external network and an internal memory that consumes less power than an external memory, and accessing the external memory from the network I / F via a first access path in the normal mode; At the time of switching from the normal mode to the power saving mode, by switching from the first access path to a second access path that allows access to the internal memory from the network I / F in the power saving mode. In the normal mode, the address to which the address for the external memory is mapped The less space, and a first path switching step for switching the address space for the internal memory.

  According to this configuration, when switching from the normal mode to the power saving mode, the address space for the internal memory is arranged in the address map area (address space) for the external memory, so the DMA address of the network I / F is changed. There is no need to do. Therefore, it is possible to improve the processing efficiency and power saving when the network requests access to the internal memory (operation request) in the power saving mode (standby state).

An eleventh invention is the electronic circuit control method according to the tenth invention, wherein the electronic circuit includes a first control unit that operates in the normal mode and a second control unit that operates in the power saving mode, At the time of switching from the normal mode to the power saving mode, the third access path including the internal memory I / F includes the fourth low power internal memory I / F that consumes less power than the internal memory I / F. A path switching step of switching to an access path, a step of reading the program for the second control unit from the external memory by the first control unit, and storing the program in the internal memory via the fourth access path; The first control unit further includes a step of starting the second control unit and stopping the operation of the first control unit. Thereafter, the first path switching step includes It is executed according to the control of the second control unit.
According to this configuration, in the power saving mode, the second control unit suitable for the application in the power saving mode can be used, and further power saving can be achieved.

A twelfth aspect of the invention is the electronic circuit control method according to the tenth or eleventh aspect of the invention, wherein the electronic circuit is disposed in an image forming apparatus that forms an image on a recording medium and is used for controlling image formation. The internal memory I / F is an image processing I / F for processing image data, and the internal memory is an image processing memory in which the image data is stored.
According to this configuration, it is possible to improve the processing efficiency at the time of requesting access to the image processing memory of the image forming apparatus from the network in the power saving mode (at the time of requesting operation) and the power saving of the image forming apparatus. it can.

  According to the present invention, in an electronic circuit having an internal memory, it is possible to improve processing efficiency and power saving when an operation request is made in a standby state.

1 is a block diagram showing a schematic electrical configuration of a printer according to an embodiment of the present invention. Block diagram showing schematic electrical configuration of electronic circuit of printer Flow chart showing operation of main and sub CPU at mode switching Explanatory drawing showing change of address map related to mode change Explanatory drawing which shows the change of the address map which concerns on another mode change

<Embodiment>
An embodiment of the present invention will be described with reference to FIGS.
1. FIG. 1 is a block diagram illustrating an electrical configuration of a printing system including a computer 10 and a printer 30 (an example of an image forming apparatus).

  The computer 10 includes a CPU 11, a ROM 12, a RAM 13, a hard disk drive 14, an operation unit 15 having a keyboard and a pointing device, a display unit 16 having a liquid crystal display, and a network interface connected to a network 20 such as a LAN (local area network). 17 etc. are included. The hard disk drive 14 stores various programs such as an OS, application software capable of creating printing data, and a printer driver for controlling the printer 30.

  The printer 30 includes an ASIC (application-specific integrated circuit) 31, an external ROM 32, a general-purpose external LSI 33, an SDRAM (synchronous dynamic RAM) 34, an operation unit 35, a display unit 36, an image forming unit 37, and the like. The ASIC 31 includes a main CPU 41, a sub CPU 42, a network interface (I / F) 67, and the like. The external ROM 32 includes parallel and serial ROM.

  Various programs for controlling the operation of the printer 30 are recorded in the external ROM 32. Normally, the main CPU 41 displays the processing result in the SDRAM according to the program read from the external ROM (an example of “external memory”) 32. (An example of “external memory”) 34 and the image processing SRAM 44 (see FIG. 2) inside the ASIC are stored, and the operation of the printer 30 is controlled. The network I / F 67 is connected to the external computer 10 or the like via the network 20, and mutual data communication is possible.

  The printer 30 has a normal mode (normal mode) in which a normal operation such as a printing process is performed and a sleep mode, which is a power saving mode in which the normal operation is not performed, as operation states.

  The operation unit 35 includes a plurality of buttons, and various input operations such as a print start instruction and an operation mode instruction can be performed by the user. The display unit 36 includes a liquid crystal display, a lamp, and the like, and can display various setting screens, operation states, and the like. The image forming unit 37 has a function of performing printing on both front and back surfaces of a recording medium such as paper.

2. Configuration of ASIC (Electronic Circuit) Next, the configuration of the ASIC 31 will be described with reference to FIG. FIG. 2 is a block diagram showing a schematic configuration of the ASIC 31.

  The ASIC 31 operates in a normal mode (normal mode) and a power saving mode (sleep mode) that consumes less power than the normal mode according to the operation mode of the printer 30.

  As shown in FIG. 2, the ASIC 31 includes a main CPU (CPU 0) 41, a sub CPU (CPU 1) 42, an external device access setting register 43, and an image processing SRAM (static RAM; an example of “internal memory”) 44. Including. The image processing SRAM 44 is accessed by the main CPU 41 in the normal mode, and is accessed by the main CPU 41 or the sub CPU 42 in the power saving mode, and consumes less power than the SDRAM 34 (external memory).

  The ASIC 31 includes bus bridges 51 and 52, a low speed BUS arbiter 53, a high speed BUS arbiter 54, and an external bus arbitration circuit 55 as various bus connection circuits.

  The ASIC 31 includes, as various interface (I / F) circuits, an external ROM-I / F 61, an external LSI-I / F 62, a register I / F 63, a first sleep SRAM-I / F 64, and a second sleep SRAM-I /. F65, SDRAM-I / F66, and network I / F67 are included.

  The ASIC 31 includes a selector 71, a first sleep SRAM selector 72, and a second sleep SRAM selector 73 as various selector circuits.

  Further, the ASIC 31 includes an image processing block 80, and the image processing block 80 includes an image processing memory I / F 81, an image processing control block 82, and the like.

  The main CPU (an example of “control unit” and “first control unit”) 41 can access the external ROM 32 and the SDRAM 34 in the normal mode. Further, when switching from the normal mode to the power saving mode, the main CPU 41 reads the program for the sub CPU 42 from the external memory, specifically, the external ROM 32, and the first sleep SRAM-I / F 64 and the first sleep SRAM selector 72 ( The program is stored in the image processing SRAM 44 via the fourth access path). Then, the main CPU 41 activates the sub CPU 42 and stops its own operation.

  When activated by the main CPU 41, the sub CPU 42 fetches (fetches) a control program in the power saving mode stored in the image processing SRAM 44, and performs control in the power saving mode in accordance with the control program.

2-1. Configuration of Access Path A second access SRAM selector (an example of “first path selector”) 73 and an SDRAM-I / F (an example of “external memory I / F”) 66 constitute a first access path. By the first access path, the SDRAM (external memory) 34 can be accessed from the network I / F 67 in the normal mode.

  The second sleep SRAM selector 73, the second sleep SRAM-I / F 65, and the first sleep SRAM selector (an example of “second path selector” and “third path selector”) 72 constitute a second access path. The With the second access path, the image processing SRAM (internal memory) 44 can be accessed from the network I / F 67 in the power saving mode.

  In the present embodiment, the second sleep SRAM-I / F (an example of the “path switching unit”) 65 sets the first access path to the first access path according to the control of the sub CPU 42 when switching from the normal mode to the power saving mode. Switch to 2 access path. Note that the first access path may be switched to the second access path in accordance with the control of the main CPU 41.

  The register I / F 63, the image processing memory I / F (an example of “internal memory I / F”) 81, and the first sleep SRAM selector 72 constitute a third access path. In the normal mode, the main CPU 41 accesses the image processing SRAM (internal memory) 44 via the third access path.

  Further, the first sleep SRAM-I / F 64 and the first sleep SRAM selector 72 constitute a fourth access path. Here, the first sleep SRAM-I / F (an example of “low power internal memory I / F”) 64 consumes less power than the image processing memory I / F 81. That is, since the image processing memory I / F 81 is used for processing image data, the circuit scale is large. On the other hand, the first sleep SRAM-I / F 64 has a small circuit scale and low power consumption.

  The first sleep SRAM selector 72 is connected to the image processing memory I / F 81, the first sleep SRAM-I / F 64, and the image processing SRAM 44. The image processing SRAM 44 and the image processing memory I / F 81 or the first sleep SRAM- Select connection with I / F64.

  In order to access the image processing SRAM 44, the fourth access path is used by the main CPU 41 and the sub CPU 42 when switching from the normal mode to the power saving mode, and is used by the sub CPU 42 in the power saving mode. .

In the present embodiment, the second sleep SRAM-I / F (an example of the “path switching unit”) 65 is configured to switch the first sleep SRAM according to the control of the main CPU 41 when switching from the normal mode to the power saving mode. The I / F 64 and the first sleep SRAM selector 72 are controlled to switch the third access path to the fourth access path (switching signals Sk2, Sk3). In the power saving mode, the supply of the clock signal to the SDRAM-I / F 66 and the image processing memory I / F 81 is stopped.
In this embodiment, the address decoding of the DMA address (logical address) from the network I / F 67 is performed by the high-speed BUS arbiter 54, for example. At this time, the DMA address from the network I / F 67 is supplied to the second sleep SRAM selector 73 as a common physical address to the SDRAM 34 and the image processing SRAM 44.

3. Operation of ASIC at Mode Switching Next, the operation of the ASIC 31 at the time of mode switching from the normal mode (normal mode) to the power saving mode (sleep mode) will be described with reference to FIGS. 3 and 4. FIG. 3 is a flowchart showing each process of the main CPU 41 and the sub CPU 42 at the time of mode switching, and FIG. 4 is an explanatory diagram showing transition of the memory address map (logical address map) of the ASIC (CPU) related to mode switching. is there. In the address map of FIG. 4, the address space that is the address space (address area) of the SDRAM 34 in the normal mode, that is, the address space after the address (0x2000_0000) is a space that can be accessed from the high-speed BUS arbiter 54. .

  When the power of the printer 30 is turned on, the main CPU (CPU0) 41 is reset (reset) (step S100), and the main CPU 41 operates normally in the normal mode (step S105). The normal operation is continued for a predetermined time until the sleep state entry condition such as no operation command is issued to the printer 30 (step S110: NO determination).

  When the sleep state entry conditions are met (step S110: YES determination), the main CPU 41 sets the access path (third access path) from the image processing memory I / F 81 to the image processing SRAM 44 as the second sleep SRAM-I / F 65. Then, the first sleep SRAM selector 72 is controlled to be turned off (step S115). That is, as shown in (2) mode switching (mode change preparation stage) in FIG. 4 in the “register IF”, the area of the memory map used as “image processing SRAM” in the normal mode is “not yet”. "Use".

  Also, the main CPU 41 stops the operation of the circuit blocks that are not used in the sleep state, including the image processing block 80 (step S120), and controls the switching operation of the second sleep SRAM-I / F 65 to control the first sleep SRAM. -Enable the operation of the I / F 64 (fourth access route) (step S125). Here, Step S115 and Step S125 correspond to a “second route switching step”.

  Then, the main CPU 41 reads a program for the sub CPU (CPU 1) 42 from the external ROM 32 or the SDRAM 34. Next, the main CPU 41 uses the route (fourth access route) of the first sleep SRAM-I / F 64 as shown in (2) “Image processing SRAM usage status” at the time of mode switching in FIG. 4. Then, the program for the sub CPU 42 is stored in a predetermined area of the image processing SRAM 44 (step S130).

  Next, the main CPU 41 cancels the reset of the sub CPU 42 and starts supplying the clock to the sub CPU 42 (step S135). Then, the sub CPU 42 receives the clock and starts the operation. That is, the sub CPU 42 starts reading (fetching) the program from the image processing SRAM 44 via the first sleep SRAM-I / F 64 path (fourth access path) (step S140).

  Next, the sub CPU 42 performs a predetermined initialization operation (step S145), and transmits a message regarding normal operation start such as the end of the initialization operation to the main CPU 41 (step S150). At this stage, the clock of the image processing block 80 can be stopped.

  When the main CPU 41 receives a message from the sub CPU 42 (step S155), the main CPU 41 stops the clock to itself, notifies the sub CPU 42 of clock stop information, and stops its own operation (steps S160 and S165). . The stopped main CPU 41 is canceled by an interrupt signal when an operation instruction is given to the printer 30. That is, the normal mode is restored.

  When the sub CPU 42 confirms that the clock of the main CPU 41 is stopped (step S170: YES determination), the sub CPU 42 controls the switching operation of the second sleep SRAM-I / F 65, invalidates the first access path, and also sets the second access path. Is enabled (corresponding to “step S175:“ first route switching step ”). That is, the second access path configured by the second sleep SRAM selector 73, the second sleep SRAM-I / F 65, and the first sleep SRAM selector 72 is enabled, and the network I / F (external I / F) is set in the power saving mode. / F) 67 can access the image processing SRAM 44.

  Further, the sub CPU 42 stops the supply of the clock signal to the image processing block 80 and the SDRAM-I / F 66, and stops the operations of the image processing block 80 and the SDRAM-I / F 66.

  When data is received from the network I / F 67 in the power saving mode (step S180: YES determination), the received data from the network I / F 67 is changed to the second sleep SRAM-I according to the control of the sub CPU 42. The data is written into a predetermined area of the image processing SRAM 44 via the / F65 path, that is, the second access path (step S185). This predetermined area corresponds to “DMA area” of “Image processing SRAM usage status” in (3) power saving mode of FIG. The “DMA area” is an address area (physical address area) used by the network I / F 67 in the normal mode.

  At this time, the sub CPU 42 controls the path switching by the second sleep SRAM-I / F 65 to perform image processing on the address space (logical address area) to which the address for the SDRAM 34 (external memory) is mapped in the normal mode. The address space for the SRAM 44 (internal memory) is switched. That is, for example, as shown in (3) “Memory Address Map” in the power saving mode in FIG. 4, the address space after the address (0x2000_0000) allocated for the SDRAM 34 in the normal mode is in the power saving mode. The address space for the image processing SRAM 44 is changed.

  Therefore, it is not necessary to change the DMA address of the network I / F when writing the received data from the network I / F 67 to the image processing SRAM 44 in the power saving mode, and the processing efficiency at that time is improved.

  As shown in FIG. 4, in the (1) normal mode of FIG. 4, the image processing SRAM 44 can be accessed by the main CPU 41 from, for example, the address for the register I / F 63 of the address (0x1C00_0000). It is.

  Further, in (2) mode switching (mode change preparation stage) in FIG. 4, the main CPU 41 or the sub CPU 42 enters the image processing SRAM 44 from, for example, the address for the image processing SRAM 44 at the address (0x1900_0000). Is accessible.

  In (3) power saving mode of FIG. 4, the image processing SRAM 44 can be accessed from the sub CPU 42 from, for example, the address for the image processing SRAM 44 at address (0x1900_0000) and address (0x2000_0000). is there. On the other hand, the network I / F 67 can be accessed from, for example, the address for the image processing SRAM 44 at the address (0x2000_0000).

3-1. Relationship between ASIC Path Switching Operation and Each Mode Next, the path switching operation of the ASIC 31 will be described in relation to (1) normal mode, (2) mode switching, and (3) power saving mode in FIG. To do.
3-1-1.
When the image processing is completed and the next operation command is not issued for a predetermined time, the printer 30 enters the standby mode before the sleep mode. In the standby mode, the main CPU 41 accesses the setting register in the second sleep SRAM-I / F 65 via the register I / F 63 to access the circuit for the first sleep SRAM selector 72 from the path F1 to the image processing SRAM 44 (third The access path) is blocked, and the path for accessing the image processing SRAM 44 from the paths F2 and F3 is enabled (switching signal Sk2). At this time, the mode is switched from (1) normal mode to (2) mode switching (mode change preparation stage) in FIG.

3-1-2.
The main CPU 41 reads the program of the sub CPU 42 from the external device (SDRAM 34 or external ROM 32), and writes the program of the sub CPU 42 to the image processing SRAM 44 via the low-speed BUS arbiter 53 and the first sleep SRAM-I / F 64. At this time, the state at the time of (2) mode switching of FIG. 4 remains.

3-1-3.
Next, when copying of the program of the sub CPU 42 is completed, the main CPU 41 activates the sub CPU 42. The sub CPU 42 fetches a program from the image processing SRAM 44 via the low-speed BUS arbiter 53 and the first sleep SRAM-I / F 64. At this time, the state at the time of (2) mode switching of FIG. 4 remains.

3-1-4.
The sub CPU 42 confirms that the access to the SDRAM 34 from the CPU 41 and other circuits connected to the high-speed BUS arbiter 54 is completed and the main CPU 41 enters the sleep mode. Thereafter, the sub CPU 42 sets a setting register in the second sleep SRAM-I / F 65, blocks the path from the second sleep SRAM selector 73 to the path G1, and enables the path to the path G2 (switching). Signal Sk1). At this time, the mode is switched from (2) mode switching to (3) power saving mode (sleep mode) in FIG.

3-1-5.
Thereby, the network I / F 67 sends data to the image processing SRAM 44 via the high-speed BUS arbiter 54, the second sleep SRAM selector 73, and the second sleep SRAM-I / F 65, that is, via the second access path. Can be sent. At this time, it remains in the state of (3) power saving mode in FIG.

  Here, in the sleep mode (power saving mode), the image processing SRAM 44 is accessed through the two routes of the route F2 and the route F3. The arbitration is performed by the second sleep SRAM-I / F 65. In the present embodiment, the path switching unit that switches various paths is configured by the second sleep SRAM-I / F 65, but is not limited thereto. Further, although the second sleep selector and the third route selector are configured by the first sleep SRAM selector 72, the second route selector and the third route selector may be configured by individual route selectors. Good.

  Here, the image processing SRAM 44 is a synchronous SRAM, and generates, for example, a clock signal having a frequency half that of the operation clock. Then, for example, the first sleep SRAM selector 72 controls the image processing SRAM 44 so that it can be accessed by the path F2 when the 1/2 frequency-divided clock signal is low (L) and by the path F3 when it is high (H). Is done.

  In this case, since the first and second sleep SRAM selectors 72 and 73 are simple switching (switches), the circuit scale can be reduced. Further, since the high-speed BUS arbiter 54 is used as it is as an arbitration circuit even in the sleep mode, the circuit scale of the second sleep SRAM-I / F 65 can be reduced.

4). Effects of the Embodiment In the present embodiment, in the power saving mode, the image processing SRAM (internal memory) 44 that consumes less power than the SDRAM (external memory) 34 is accessed from the network 20 via the network I / F 67. Can do. Further, in the power saving mode, the address space (logical address space) for the image processing SRAM is arranged in the address map area (logical address space) for the SDRAM by the path switching by the simple circuit configuration (65, 72, 73). Is done. Therefore, it is not necessary to change the DMA address of the network I / F 67 when accessing the image processing SRAM 44 via the network I / F 67 in the power saving mode. Therefore, it is possible to improve processing efficiency and power saving when requesting access to the image processing SRAM 44 from the network 20 in the power saving mode (standby state).

  Further, in the power saving mode, the supply of the clock signal to the image processing block 80 and the SDRAM-I / F 66 is stopped, so that the power consumption can be further reduced.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  (1) In the above embodiment, when accessing the image processing SRAM 44 from the sub CPU 42 in the power saving mode, an example of accessing via the fourth access path without passing through the image processing block 80 has been shown. Absent. When accessing the image processing SRAM 44 from the sub CPU 42, the image processing SRAM 44 may be accessed via the image processing block 80, that is, via the conventional third access path.

  In this case, the first sleep SRAM-I / F 64 is not necessary. An address map in this case is shown in FIG. As shown in FIG. 5, the address area related to the register I / F 63 is not changed. However, as in the above embodiment, the address space after the address (0x2000_0000) assigned to the SDRAM 34 in the normal mode is changed to the address space for the image processing SRAM 44 in the power saving mode. Therefore, even in this case, it is not necessary to change the DMA address of the network I / F 67 when accessing the image processing SRAM 44 via the network I / F 67 in the power saving mode.

  (2) In the above embodiment, the main CPU 41 and the sub CPU 42 are provided, the main CPU 41 is used in the normal mode, and the sub CPU 42 is used in the power saving mode. However, the present invention is not limited to this. One CPU (control unit) may be provided and controlled by one CPU in the normal mode and the power saving mode. That is, the operations of the main CPU 41 and the sub CPU 42 may be performed by a single CPU.

30 ... Printer 31 ... ASIC
41 ... Main CPU
42 ... Sub CPU
44 ... SRAM for image processing
64: First sleep SRAM-I / F
65. Second sleep SRAM-I / F
67 ... Network I / F
72 ... First sleep SRAM selector 73 ... Second sleep SRAM selector

Claims (12)

An electronic circuit that operates in a normal mode and a power saving mode that consumes less power than the normal mode,
A control unit accessible to the external memory in the normal mode;
An internal memory that is accessed by the control unit in the normal mode and the power saving mode and that consumes less power than the external memory;
A network I / F connected to an external network;
A first access path enabling access from the network I / F to the external memory in the normal mode;
A second access path enabling access from the network I / F to the internal memory in the power saving mode;
When switching from the normal mode to the power saving mode, the address for the external memory is mapped in the normal mode by switching the first access path to the second access path according to the control of the control unit. A path switching unit that switches the address space that has been changed to the address space for the internal memory;
With electronic circuit. The electronic circuit according to claim 1.
The first access path includes a first path selector and an external memory I / F,
The second access route includes the first route selector, the route switching unit, and a second route selector,
The first path selector is connected to the network I / F;
The second path selector is connected to the internal memory;
The path switching unit controls switching of the first path selector and the second path selector when switching from the normal mode to the power saving mode, and switches the first access path to the second access path. , Electronic circuit. The electronic circuit according to claim 1 or 2,
An electronic circuit in which supply of a clock signal to the external memory I / F is stopped in the power saving mode. The electronic circuit according to any one of claims 1 to 3,
A third access path for the control unit to access the internal memory in the normal mode, the third access path including an internal memory I / F;
The fourth access path including a low-power internal memory I / F that consumes less power than the internal memory I / F as a fourth access path for the control unit to access the internal memory in the power saving mode And further comprising
The path switching unit is an electronic circuit that switches the third access path to the fourth access path according to the control of the control unit when switching from the normal mode to the power saving mode. The electronic circuit according to claim 4.
The fourth access path includes a third path selector;
The third path selector is connected to the internal memory I / F, the low power internal memory I / F, and the internal memory, and the internal memory and the internal memory I / F or the low power internal memory I / F. Select the connection with
The path switching unit controls the low-power internal memory I / F and the third path selector to switch the third access path to the fourth access path when switching from the normal mode to the power saving mode. Switching electronic circuit. The electronic circuit according to claim 5,
An electronic circuit in which the second path selector and the third path selector are configured by a single path selector. The electronic circuit according to any one of claims 4 to 6,
An electronic circuit in which the supply of a clock signal to the internal memory I / F is stopped in the power saving mode. The electronic circuit according to any one of claims 1 to 7,
The control unit includes a first control unit that operates in the normal mode, and a second control unit that operates in the power saving mode,
The first control unit, when switching from the normal mode to the power saving mode,
An electronic circuit that reads a program for the second control unit from the external memory, stores the program in the internal memory, activates the second control unit, and then stops its own operation. An image forming apparatus for forming an image on a recording medium,
An electronic circuit according to any one of claims 1 to 8,
An image forming unit that forms an image based on the control of the electronic circuit;
The internal memory I / F is an image processing I / F for processing image data,
The image forming apparatus, wherein the internal memory is an image processing memory in which the image data is stored. A control method for mode switching of an electronic circuit that operates in a normal mode and a power-saving mode that consumes less power than the normal mode,
The electronic circuit includes a network I / F connected to an external network and an internal memory that consumes less power than the external memory,
Accessing the external memory from the network I / F via a first access path in the normal mode;
At the time of switching from the normal mode to the power saving mode, by switching from the first access path to a second access path that allows access to the internal memory from the network I / F in the power saving mode. A first path switching step of switching the address space in which the address for the external memory is mapped in the normal mode to the address space for the internal memory;
A method for controlling an electronic circuit. The method of claim 10, wherein
The electronic circuit includes a first control unit that operates in the normal mode, and a second control unit that operates in the power saving mode,
At the time of switching from the normal mode to the power saving mode,
A second path switching step of switching from a third access path including an internal memory I / F to a fourth access path including a low-power internal memory I / F that consumes less power than the internal memory I / F;
Reading the program for the second control unit from the external memory by the first control unit, and storing the program in the internal memory via the fourth access path;
Starting the second control unit by the first control unit and stopping the operation of the first control unit;
Further including
Thereafter, the electronic circuit control method, wherein the first path switching step is executed according to the control of the second control unit. 12. A method according to claim 10 or claim 11, wherein
The electronic circuit is an electronic circuit that is disposed in an image forming apparatus that forms an image on a recording medium and is used for image formation control.
The internal memory I / F is an image processing I / F for processing image data,
The internal memory is an image processing memory in which the image data is stored.
Electronic circuit control method.

Images