JP2011181157A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce data stored in a memory cell from being erroneously sensed. <P>SOLUTION: A nonvolatile semiconductor memory device 1 includes: memory cells storing data in accordance with a difference of threshold voltage; a word line WL connected to the gate of a memory cell; a bit line connected to one end of a current path of the memory cell; a sense amplifier SA detecting the data of the memory cell; an electric charge transfer transistor 20 provided between the bit line BL and the sense amplifier SA; and a voltage generating circuit 21 applying clamp voltage to the gate of the electric charge transfer transistor 20. In continuous sense operation, after the bit line BL is pre-charged, voltage of the word line WL is changed, and sense operation is performed every time the voltage is changed. In the continuous sense operation, the voltage generating circuit 21 changes clamp voltage by a first sense operation and a second sense operation after the first sense operation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, for example, a nonvolatile semiconductor memory device having electrically rewritable memory cells.

  A NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated. In addition, a charge transfer type sense amplifier used in a NAND flash memory or the like is known (for example, Patent Document 1).

  This NAND flash memory includes a clamp transistor between a bit line and a sense node, and controls the gate voltage of the clamp transistor to charge the bit line to a precharge voltage or sense the bit line voltage. Or

  Consider a case where a multilevel memory cell has a plurality of read levels. When sensing multi-levels in order from the erase side, it takes time to repeat precharge and discharge of the bit line for each level sensing operation. On the other hand, in the case of continuous sensing that requires only one precharge and discharge, the total readout time is shortened, which is effective for speeding up. However, if the voltage of the first precharged bit line is lowered by the leak current at the sense time of the subsequent stage, the off cell (cell storing “0” data) is turned on (“1” data is stored). Cell).

  The continuous sensing operation is based on the premise that the potential of the bit line connected to the off-cell is kept as much as possible with the original precharge voltage. However, since the premise is not maintained, the possibility of erroneous sensing increases. In particular, as the capacity increases and the number of cells connected to one bit line increases, the influence of off-leak components from unselected blocks increases. As a result, there is a problem that the continuous sensing operation becomes impossible and consequently the speed cannot be increased.

JP 2007-164891 A

  The present invention provides a nonvolatile semiconductor memory device capable of reducing the probability of erroneous sensing of data stored in a memory cell.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell that stores data according to a difference in threshold voltage, a word line connected to a gate of the memory cell, and one end of a current path of the memory cell. A bit line connected to the memory cell, a sense amplifier for detecting data of the memory cell, a charge transfer transistor provided between the bit line and the sense amplifier, and a clamp voltage applied to a gate of the charge transfer transistor In the continuous sensing operation in which the voltage of the word line is changed once after the bit line is precharged and the sensing operation is performed each time, the voltage generating circuit includes a first sensing circuit. The clamp voltage is changed between an operation and a second sense operation after the first sense operation.

  ADVANTAGE OF THE INVENTION According to this invention, the non-volatile semiconductor memory device which can reduce the probability that the data which a memory cell memorize | stores will be reduced can be provided.

1 is a block diagram showing a configuration of a NAND flash memory 1 according to a first embodiment. 2 is a circuit diagram showing a configuration of a memory cell array 10. FIG. 3 is a circuit diagram showing a configuration of a main part of a bit line control circuit 11. FIG. Schematic which shows the threshold voltage distribution of a memory cell. 4 is a timing chart of the NAND flash memory 1 in a read operation. The circuit diagram which shows the structure of BL clamp voltage generation circuit 21 which concerns on 2nd Embodiment. 4 is a timing chart of the NAND flash memory 1 in a read operation.

  Embodiments of the present invention will be described below with reference to the drawings. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a NAND flash memory 1 as a nonvolatile semiconductor memory device according to the first embodiment of the present invention. The memory cell array 10 is configured by arranging electrically rewritable flash memory cells in a matrix. In the memory cell array 10, a plurality of bit lines BL extending in the column direction, a plurality of word lines WL extending in the row direction, and a source line CELSRC extending in the row direction are arranged.

  A bit line control circuit 11 is connected to the bit line BL. The bit line control circuit 11 selects the bit line BL, controls the voltage of the bit line BL, and erases data from the memory cell, writes data to the memory cell, and reads data from the memory cell. The bit line control circuit 11 includes a column decoder, a sense amplifier SA, a page buffer, a data cache, and the like.

  A word line control circuit 12 is connected to the word line WL. The word line control circuit 12 selects the word line WL and applies a voltage necessary for erasing, writing, and reading to the word line WL. The word line control circuit 12 includes a row decoder, a word line driver, and the like.

  The source line control circuit 13 controls the voltage of the source line CELSRC. The P well control circuit 14 controls the voltage of the p-type well in which the memory cell array 10 is formed.

  The data input / output buffer 15 is connected to the external host controller 2 via an I / O line, and receives write data, outputs read data, and receives addresses and commands. The data input / output buffer 15 sends the received write data to the bit line control circuit 11 and receives read data read from the bit line control circuit 11. The data input / output buffer 15 sends an external address to the bit line control circuit 11 and the word line control circuit 12 via the control unit 17 in order to select a memory cell. Further, the data input / output buffer 15 sends a command from the host controller 2 to the command interface 16.

  The command interface 16 receives a control signal from the host controller 2, determines whether the data input to the data input / output buffer 15 is write data, a command, or an address. The signal is sent to the control unit 17 as a signal.

  The control unit 17 manages the entire NAND flash memory 1. The control unit 17 receives a command from the host controller 2 and performs read, write, erase, and data input / output management. Then, the control unit 17 sends control signals necessary for these operations to each circuit.

  FIG. 2 is a circuit diagram showing a configuration of the memory cell array 10. The memory cell array 10 includes j (j is an integer of 1 or more) blocks BLK0 to BLKj-1. The block BLK is a minimum unit for erasing data.

  Even-numbered bit lines BLe and odd-numbered bit lines BLo counted from 0 are written and read data independently of each other. Of 2m (m is an integer of 1 or more) memory cells connected to one word line WL, data is written and read simultaneously to m memory cells connected to the bit line BLe. 1-bit data stored in each memory cell is collected for m memory cells to form a unit called a page. A page is a minimum unit for writing and reading. When one memory cell stores 2-bit data, m memory cells store two pages of data. Similarly, another two pages are configured by m memory cells connected to the bit line BLo, and data is written into and read from the memory cells in the page at the same time.

  Each block BLK includes 2m NAND strings arranged in order along the row direction. The selection transistor ST1 included in the NAND string has a drain connected to the bit line BL and a gate commonly connected to the selection gate line SGD. In the select transistor ST2 included in the NAND string, the source is commonly connected to the source line CELSRC, and the gate is commonly connected to the select gate line SGS.

  Each memory cell transistor (also referred to as a memory cell) MT is configured by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a p-type well. The stacked gate structure includes a charge storage layer (floating gate electrode) formed on a p-type well with a gate insulating film interposed therebetween, and a control gate electrode formed on the floating gate electrode with an inter-gate insulating film interposed therebetween. Contains. In the memory cell transistor MT, the threshold voltage changes according to the number of electrons stored in the floating gate electrode, and data is stored according to the difference in threshold voltage. The memory cell transistor MT stores, for example, data of 2 bits or more (multi-value data).

  The memory cell transistor MT is not limited to a floating gate structure having a floating gate electrode, but is a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type threshold voltage by trapping electrons at a nitride film interface as a charge storage layer. May be an adjustable structure.

  In each NAND string, each of n (n is an integer of 1 or more) memory cell transistors MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. Has been placed. That is, n memory cell transistors MT are connected in series in the column direction so that adjacent ones share a diffusion region (source region or drain region).

  In each NAND string, the control gate electrodes are connected to the word lines WL0 to WLn−1 in order from the memory cell transistor MT located closest to the source. Accordingly, the drain of the memory cell transistor MT connected to the word line WLn−1 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WL0 is connected to the drain of the selection transistor ST2. Yes.

  The word lines WL0 to WLn-1 connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the block BLK. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL.

  In addition, the bit line BL commonly connects the drains of the selection transistors ST1 between the blocks BLK. That is, NAND strings in the same column in the blocks BLK0 to BLKj-1 are connected to the same bit line BL.

  The even-numbered bit line BLe0 and the odd-numbered bit line BLo0 are connected to the charge transfer transistor 20 via the selection circuit 18 included in the bit line control circuit 11. The same applies to other pairs of even-numbered bit lines BLe and odd-numbered bit lines BLo. The selection operation between the even-numbered bit lines BLe and the odd-numbered bit lines BLo is performed by the selection lines BLSe and BLSo.

  FIG. 2 shows a configuration example in which one sense amplifier SA is arranged for two bit lines, but one sense amplifier SA may be arranged for each bit line BL. In this case, the memory cell transistors MT connected to the common word line simultaneously write and read data.

  FIG. 3 is a circuit diagram showing a configuration of a main part of the bit line control circuit 11. The bit line control circuit 11 includes a BL clamp voltage generation circuit 21, a sense amplifier SA, and a charge transfer transistor 20. 3 shows the configuration of the BL clamp voltage generation circuit 21, the sense amplifier SA, and the charge transfer transistor 20 connected to one bit line. Therefore, the circuit in FIG. 3 has the number of bit lines. Minutes are prepared.

  The charge transfer transistor 20 is composed of, for example, an N channel MOSFET. One end of the current path of the charge transfer transistor 20 is connected to the bit line BL via a selection circuit 18 (not shown). The other end of the current path of the charge transfer transistor 20 is connected to the sense amplifier SA. The gate of the charge transfer transistor 20 is connected to the BL clamp voltage generation circuit 21.

  The BL clamp voltage generation circuit 21 generates a BL clamp voltage BLCLAMP for controlling the voltage of the bit line BL, and applies this BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. The BL clamp voltage generation circuit 21 includes a constant current source 24, N-channel MOSFETs (NMOSFET) 22 and 23 as switching elements, an NMOSFET (resistance component) 25 having the same threshold voltage as the charge transfer transistor 20, and a variable resistor 26. I have.

  The NMOSFET 25 is diode-connected, the drain to which the gate is connected corresponds to the anode, and the source corresponds to the cathode. The NMOSFET 25 plays a role of adding its own voltage drop (corresponding to the threshold voltage of the charge transfer transistor 20) to the voltage applied to the variable resistor 26. As the resistance component 25, a diode or the like may be used in addition to the NMOSFET.

  One end of the current path of the NMOSFET 22 is connected to the node OUT. The other end of the current path of the NMOSFET 22 is connected to the constant current source 24 and the drain of the NMOSFET 25. A signal SW 1 is supplied from the control unit 17 to the gate of the NMOSFET 22. The NMOSFET 22 is turned on / off in response to the signal SW1.

  One end of the variable resistor 26 is connected to the source of the NMOSFET 25. The other end of the variable resistor 26 is grounded (connected to the ground terminal VSS). The resistance value of the variable resistor 26 changes according to the signal DAC from the control unit 17.

  The drain of the NMOSFET 23 is connected to the node OUT. The source of the NMOSFET 23 is grounded. A signal SW 2 is supplied from the control unit 17 to the gate of the NMOSFET 23. The NMOSFET 23 is turned on / off in response to the signal SW2.

  The BL clamp voltage generation circuit 21 configured as described above outputs the bit line clamp voltage BLCLAMP from the node OUT. Specifically, the BL clamp voltage generation circuit 21 sets the BL clamp voltage BLCLAMP to “VR + Vth” when the NMOSFET 22 is on. VR is a voltage drop of the variable resistor 26 and can be arbitrarily set by changing the resistance of the variable resistor 26. Vth is a threshold voltage of the charge transfer transistor 20 and the NMOSFET 25. The BL clamp voltage generation circuit 21 sets the BL clamp voltage BLCLAMP to 0V when the NMOSFET 23 is on.

  The sense amplifier SA includes a capacitor 27, an NMOSFET 28, and a latch circuit 29. The drain of the NMOSFET 28 is connected to the power supply node VDD / VSS. The source of the NMOSFET 28 is connected to the sense node TDC. A signal PRE is supplied from the control unit 17 to the gate of the NMOSFET 28. The power supply node VDD / VSS is set to either the power supply voltage VDD or the ground voltage VSS by the control unit 17. Therefore, the NMOSFET 28 sets the sense node TDC to either the power supply voltage VDD or the ground voltage VSS.

  One electrode of the capacitor 27 is connected to the sense node TDC. The other electrode of the capacitor 27 is grounded. The sense node TDC is connected to the charge transfer transistor 20.

  The latch circuit 29 holds the voltage of the sense node TDC as data. The data held in the latch circuit 29 is sent to the data input / output buffer 15. The latch circuit 29 holds data sent from the data input / output buffer 15 and transfers the held data to the sense node TDC.

(Operation)
The operation of the NAND flash memory 1 configured as described above will be described. When reading data from a memory cell, a read voltage Vcgrv for determining data in the selected memory cell is applied to a selected word line connected to the memory cell (selected memory cell) to be read, and the read voltage Vcgrv On the other hand, it is determined whether the selected memory cell is turned on or off. The read voltage Vcgrv is generated by the word line control circuit 12.

  The memory cell can store multi-value data, and the threshold voltage of the memory cell is assumed to increase in order of A level, B level, C level, D level,. Each of the plurality of threshold voltages is assigned to data. FIG. 4 is a schematic diagram showing the threshold voltage distribution of the memory cell. The horizontal axis in FIG. 4 is the threshold voltage VTC of the memory cell, and the vertical axis is the number of memory cells (cell number). The A level is, for example, a threshold voltage of an erased memory cell. The read pass voltage Vread shown in FIG. 4 is a voltage that can turn on a memory cell regardless of stored data, and is higher than any threshold voltage. By appropriately setting the read voltage Vcgrv, data of the memory cell can be determined.

  FIG. 5 is a timing chart of the NAND flash memory 1 in the read operation. In the read operation, first, the bit line BL is charged to the precharge voltage VPRE by the BL clamp voltage generation circuit 21. Specifically, the signal SW1 becomes high level, the signal SW2 becomes low level, the NMOSFET 22 is turned on, and the NMOSFET 23 is turned off. The resistance value of the variable resistor 26 is set by the signal DAC so that the voltage drop becomes the precharge voltage VPRE. As a result, the BL clamp voltage generation circuit 21 applies “VPRE + Vth” as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. At this time, the sense node TDC corresponding to the drain of the charge transfer transistor 20 is charged to the power supply voltage VDD by the NMOSFET 28. The charge transfer transistor 20 is turned off when the bit line BL reaches the precharge voltage VPRE.

  Subsequently, the signal SW1 becomes low level, the signal SW2 becomes high level, the NMOSFET 22 is turned off, and the NMOSFET 23 is turned on. As a result, the BL clamp voltage generation circuit 21 applies 0 V as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. Therefore, the charge transfer transistor 20 is turned off and the bit line BL is in a floating state.

  Subsequently, as shown in FIG. 3, a read voltage Vcgrv for determining data of the selected memory cell is applied to the selected word line (Selected WL), and a read pass voltage Vread is applied to the non-selected word line. . For example, the power supply voltage VDD is applied to the selection gate lines SGD and SGS, and the selection transistors ST1 and ST2 are turned on. The source line CELSRC is 0V, for example.

  In this embodiment, after the bit line BL is charged once to the precharge voltage VPRE, a so-called continuous sensing operation is performed in which the read voltage Vcgrv is increased in order from the A level until the data of the selected memory cell is determined. .

  When the threshold voltage of the selected memory cell is higher than the read voltage Vcgrv, that is, when the selected memory cell stores “0” data, the selected memory cell is turned off and the bit line BL is not discharged. On the other hand, when the threshold voltage of the selected memory cell is smaller than the read voltage Vcgrv, that is, when the selected memory cell stores “1” data, the selected memory cell is turned on, and the cell current Icell flows through the NAND string. As a result, the bit line BL is discharged through the selected memory cell.

  Here, since a leak current is generated in the charged bit line BL, the voltage of the bit line BL gradually decreases from the precharge voltage VPRE during the continuous sensing operation. The cause of the leak current is a junction leak of the transistor. As a countermeasure, in this embodiment, as shown in FIG. 5, the sense voltage Vsen is gradually lowered as the number of stages of the sensing operation increases, that is, as the read voltage Vcgrv increases. The sense voltage Vsen is a voltage for determining whether the data stored in the selected memory cell is “1” data or “0” data. Ideally, the amount by which the sense voltage Vsen is lowered for each stage is equal to the amount of voltage drop due to the leakage current when the bit line BL is in the floating state. The sense voltage satisfies the following relationship.

VPRE>Vsen_A>Vsen_B> Vsen_C
Hereinafter, the threshold voltage of the selected memory cell is assumed to be C level, and the continuous sensing operation in this case will be described as an example. First, as shown in FIG. 5, the read voltage Vcgrv is set to a voltage for determining the A level. The BL clamp voltage generation circuit 21 generates a voltage “Vsen_A + Vth” as the BL clamp voltage BLCLAMP. This is realized by setting the voltage drop of the variable resistor 26 to the sense voltage Vsen_A. At this time, since the voltage of the bit line BL is higher than the sense voltage Vsen_A, the charge transfer transistor 20 is turned off, and no charge is transferred from the bit line BL to the sense node TDC.

  Subsequently, the read voltage Vcgrv is set to a voltage for determining the B level. The BL clamp voltage generation circuit 21 generates a voltage “Vsen_B + Vth” as the BL clamp voltage BLCLAMP. This is realized by setting the voltage drop of the variable resistor 26 to the sense voltage Vsen_B. At this time, since the voltage of the bit line BL is higher than the sense voltage Vsen_B, the charge transfer transistor 20 is turned off, and no charge is transferred from the bit line BL to the sense node TDC.

  Subsequently, the read voltage Vcgrv is set to a voltage for determining the C level. The BL clamp voltage generation circuit 21 generates a voltage “Vsen_C + Vth” as the BL clamp voltage BLCLAMP. This is realized by setting the voltage drop of the variable resistor 26 to the sense voltage Vsen_C. At this time, the selected memory cell is turned on and the bit line BL is discharged. Therefore, the voltage of the bit line BL becomes equal to or lower than the sense voltage Vsen_C, and the charge transfer transistor 20 is turned on. When the charge transfer transistor 20 is turned on, the sense node TDC charged to the power supply voltage VDD is discharged. Therefore, the sense amplifier SA determines that the data stored in the selected memory cell is “1” data. This determination result is held by the latch circuit 29.

  As a result, even when the voltage of the bit line BL is gradually lowered from the precharge voltage VPRE during the continuous sensing operation, the off cell (cell storing “0” data) is turned on cell (“1” data is stored). The probability of erroneous sensing as a cell) can be reduced.

  In the first embodiment, a read operation is described as an example. However, a verify operation for determining whether or not desired data is written in a memory cell after writing data in the memory cell is also described. The same applies.

(effect)
As described above in detail, in the first embodiment, after the bit line BL is once charged, a continuous sense operation is performed in which the read voltage Vcgrv applied to the selected word line is increased as it proceeds to the subsequent stage. During the continuous sensing operation, even if the voltage of the bit line BL decreases due to the leak current, the sense voltage Vsen for determining whether the memory cell is on or off is corrected accordingly. That is, in the continuous sense operation, the sense voltage Vsen is changed between an arbitrary first sense operation and a second sense operation after the first sense operation. More specifically, the sense voltage Vsen is gradually lowered as the sensing operation proceeds to the subsequent stage.

  Therefore, according to the first embodiment, it is possible to reduce the probability of erroneously sensing an off cell as an on cell in a continuous sense operation. As a result, the data stored in the NAND flash memory 1 can be accurately read, and as a result, the reliability of the data stored in the NAND flash memory 1 can be improved.

  Further, it is possible to achieve both a continuous sensing operation and a highly accurate data reading operation. For example, in the case where the charging and discharging of the bit line BL are repeated every sensing operation, the reading time and the verifying time become long. On the other hand, in this embodiment, since a continuous sensing operation that requires only one charge and discharge is adopted, it is possible to increase the speed of the read operation and the verify operation, thereby reducing the read time and the verify time. Can do.

(Second Embodiment)
In the second embodiment, the same phenomenon as the phenomenon in which the voltage of the bit line BL gradually decreases due to the leak current is simulated to improve the accuracy of the sense voltage Vsen.

  FIG. 6 is a circuit diagram showing a configuration of the BL clamp voltage generation circuit 21 according to the second embodiment of the present invention. The drain of the NMOSFET 30 as the switch element is connected to the constant current source 24. The source of the NMOSFET 30 is connected to the NMOSFETs 22 and 25 via the node N1. A signal SW 3 is supplied from the control unit 17 to the gate of the NMOSFET 30. The NMOSFET 30 is turned on / off in response to the signal SW3.

  The drain of the NMOSFET 32 as a switch element is connected to the constant current source 31. The source of the NMOSFET 32 is connected to the input of the voltage follower 33, one end of the variable resistor 26, and one end of the replica bit line Re_BL. A signal SW 4 is supplied from the control unit 17 to the gate of the NMOSFET 32. The NMOSFET 32 is turned on / off in response to the signal SW4.

  The output of the voltage follower 33 is connected to the NMOSFET 25. The other end of the variable resistor 26 is connected to the drain of the NMOSFET 34 as a switching element. The source of the NMOSFET 34 is grounded. A signal SW 5 is supplied from the control unit 17 to the gate of the NMOSFET 34. The NMOSFET 34 is turned on / off in response to the signal SW5.

  A capacitor 35 and a replica leak source (pseudo leak source) 36 are connected to the replica bit line Re_BL. The capacitor 35 is added so that the capacity of the replica bit line Re_BL is the same as the capacity of one bit line BL. Therefore, the combined capacity of the capacitor 35 and the replica bit line Re_BL is one bit. It has the same capacity as the line BL. The replica leak source 36 plays a role of reproducing the leak current of the bit line BL in a pseudo manner, and has the same configuration as the leak source of the bit line BL. For example, a MOSFET junction is used as the replica leak source 36. Alternatively, a replica leak source can be configured with a constant current circuit or a resistance element.

(Operation)
The operation of the NAND flash memory 1 configured as described above will be described. FIG. 5 is a timing chart of the NAND flash memory 1 in the read operation.

  In the read operation, first, the bit line BL is charged to the precharge voltage VPRE by the BL clamp voltage generation circuit 21. Specifically, the signals SW4 and SW5 become high level, and the NMOSFETs 32 and 34 are turned on. The resistance value of the variable resistor 26 is set by the signal DAC so that the voltage drop becomes the precharge voltage VPRE. As a result, the output of the voltage follower 33 becomes the precharge voltage VPRE. Therefore, the BL clamp voltage generation circuit 21 applies “VPRE + Vth” as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20.

  The sense node TDC corresponding to the drain of the charge transfer transistor 20 is charged to the power supply voltage VDD by the NMOSFET 28. The charge transfer transistor 20 is turned off when the bit line BL reaches the precharge voltage VPRE. Thereafter, the BL clamp voltage generation circuit 21 applies 0 V as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. Therefore, the charge transfer transistor 20 is turned off and the bit line BL is in a floating state.

  Subsequently, a voltage for determining the A level is applied to the selected word line (Selected WL) as the read voltage Vcgrv, and a read pass voltage Vread is applied to the unselected word lines. For example, the power supply voltage VDD is applied to the selection gate lines SGD and SGS, and the selection transistors ST1 and ST2 are turned on. The source line CELSRC is 0V, for example.

  Similar to the first embodiment, the sense voltage satisfies the following relationship.

VPRE>Vsen_A>Vsen_B> Vsen_C
The threshold voltage of the selected memory cell is assumed to be C level. First, the resistance value of the variable resistor 26 is set by the signal DAC so that the voltage drop becomes the sense voltage Vsen_A. As a result, the output of the voltage follower 33 becomes the sense voltage Vsen_A. Therefore, the BL clamp voltage generation circuit 21 applies “Vsen_A + Vth” as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. The replica bit line Re_BL is charged to the sense voltage Vsen_A. At this time, since the voltage of the bit line BL is higher than the sense voltage Vsen_A, the charge transfer transistor 20 is turned off, and no charge is transferred from the bit line BL to the sense node TDC.

  Subsequently, the signals SW4 and SW5 become low level, and the NMOSFETs 32 and 34 are turned off. Thereafter, a leak current is generated in the replica bit line Re_BL by the replica leak source 36. As a result, the voltage of the replica bit line Re_BL gradually decreases at substantially the same rate as the bit line BL.

  Subsequently, the read voltage Vcgrv is set to a voltage for determining the B level. The BL clamp voltage generation circuit 21 applies “Vsen_B + Vth” as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. The sense voltage Vsen_B corresponds to the voltage of the replica bit line Re_BL at this time. At this time, since the voltage of the bit line BL is higher than the sense voltage Vsen_B, the charge transfer transistor 20 is turned off, and no charge is transferred from the bit line BL to the sense node TDC.

  Subsequently, the read voltage Vcgrv is set to a voltage for determining the C level. The BL clamp voltage generation circuit 21 applies “Vsen_C + Vth” as the BL clamp voltage BLCLAMP to the gate of the charge transfer transistor 20. The sense voltage Vsen_C corresponds to the voltage of the replica bit line Re_BL at this time. At this time, the selected memory cell is turned on and the bit line BL is discharged. Therefore, the voltage of the bit line BL becomes lower than the sense voltage Vsen_C, and the charge transfer transistor 20 is turned on. When the charge transfer transistor 20 is turned on, the sense node TDC charged to the power supply voltage VDD is discharged. Therefore, the sense amplifier SA determines that the data stored in the selected memory cell is “1” data. This determination result is held by the latch circuit 29.

  As a result, even when the voltage of the bit line BL is gradually lowered from the precharge voltage VPRE during the continuous sensing operation, the off cell (cell storing “0” data) is turned on cell (“1” data is stored). The probability of erroneous determination as a cell) can be reduced.

(effect)
As described above in detail, in the second embodiment, the phenomenon in which the voltage of the bit line BL gradually decreases due to the leak current is reproduced in a pseudo manner using the replica bit line Re_BL. Then, the continuous sense operation is performed using the voltage of the replica bit line Re_BL as the sense voltage. The sense voltage Vsen is gradually lowered as the sense operation proceeds to the subsequent stage.

  Therefore, according to the second embodiment, the same effect as the first embodiment can be obtained. In addition, the sense voltage Vsen can be automatically generated in the BL clamp voltage generation circuit 21 during the continuous sensing operation. This eliminates the need to set the resistance value of the variable resistor 26 for each sensing operation, and facilitates circuit design.

  In addition, the optimum sense voltage Vsen can be generated according to the characteristics of the bit line BL that changes for each specification. Thereby, it is possible to further reduce the probability that an off cell is erroneously sensed as an on cell in a continuous sensing operation.

  In the second embodiment, the read operation has been described as an example, but the same applies to the verify operation.

  The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

  BL ... bit line, WL ... word line, CELSRC ... source line, SGD ... selection gate line, SGS ... selection gate line, selection line ... BLS, BLK ... block, MT ... memory cell transistor, ST1, ST2 ... selection transistor, SA Sense amplifier, TDC Sense node, Re_BL Replica bit line, 1 NAND flash memory, 2 Host controller, 10 Memory cell array, 11 Bit line control circuit, 12 Word line control circuit, 13 Source line control Circuit, 14 ... P well control circuit, 15 ... Data input / output buffer, 16 ... Command interface, 17 ... Control unit, 18 ... Selection circuit, 20 ... Charge transfer transistor, 21 ... BL clamp voltage generation circuit, 21 ... Constant current source , 22, 23, 25, 28, 30, 32, 34 ... N-channel MOS FET, 24, 31 ... constant current source, 26 ... variable resistor, 27, 35 ... capacitor, 29 ... latch circuit, 33 ... voltage follower, 36 ... replica leak source.

Claims (7)

A memory cell for storing data according to a difference in threshold voltage;
A word line connected to the gate of the memory cell;
A bit line connected to one end of the current path of the memory cell;
A sense amplifier for detecting data in the memory cell;
A charge transfer transistor provided between the bit line and the sense amplifier;
A voltage generation circuit for applying a clamp voltage to the gate of the charge transfer transistor;
Comprising
In the continuous sensing operation in which the voltage of the word line is changed once after the bit line is precharged and the sensing operation is performed each time, the voltage generation circuit includes the first sensing operation and the first sensing operation. A non-volatile semiconductor memory device, characterized in that the clamp voltage is changed in the second sense operation after.   2. The nonvolatile semiconductor memory device according to claim 1, wherein a clamp voltage during the second sense operation is lower than a clamp voltage during the first sense operation. The voltage generation circuit includes:
A constant current source;
One end of which is connected to the constant current source via an output node, and a resistance component that adds the same voltage as the threshold voltage of the charge transfer transistor to the output node;
A variable resistor having one end connected to the other end of the resistance component and the other end grounded;
Including
The nonvolatile semiconductor memory device according to claim 1, wherein the clamp voltage changes according to a resistance value of the variable resistor.   2. The voltage generation circuit includes a replica bit line and a replica leak source connected to the replica bit line, and generates the clamp voltage based on a voltage of the replica bit line. Or the nonvolatile semiconductor memory device according to 2; The voltage generation circuit includes:
First and second constant current sources;
A variable resistor having one end connected to the first constant current source and the replica bit line and the other end grounded;
One end connected to the second constant current source via an output node, the other end connected to the replica bit line, and a resistance component for adding a voltage equal to the threshold voltage of the charge transfer transistor to the output node;
The nonvolatile semiconductor memory device according to claim 4, comprising: A first switch connected between the output node and the resistance component;
A second switch connected between the output node and a ground terminal;
The nonvolatile semiconductor memory device according to claim 3, further comprising: A third switch connected between the first constant current source and the variable resistor;
A fourth switch connected between the variable resistor and a ground terminal;
The nonvolatile semiconductor memory device according to claim 5, further comprising:

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