JP2011180680A - Multiprocessor system and program for multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve efficiency of calculation processing of a multiprocessor system. <P>SOLUTION: A multiprocessor system is provided with: a first memory; and a processing part connected to the first memory for executing processing by using data stored in the first memory. The processing part is provided with: a second memory; a first processor for executing data transfer to transfer at least one of data or processing data as the result of processing between the first memory and the second memory; a second processor for executing the data transfer and the processing between the first memory and the second memory so that they can be switched; and a third processor for executing the processing by using the data transferred to the second memory. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a multiprocessor system and a program for the multiprocessor system.

  In a system that requires high processing performance, a multiprocessor system using a plurality of processors is used (see, for example, Patent Documents 1-4). For example, a multiprocessor system such as an accelerator that supports computer processing has a memory that stores data transferred between the multiprocessor system and the computer. Generally, a low-speed memory having a large storage capacity is used for this type of memory.

  Each processor performs a calculation process using input data transferred from a computer to a memory of a multiprocessor system, for example. Then, each processor transfers output data as a result of the calculation process to the memory. As described above, each processor accesses a low-speed memory each time a calculation process is performed.

  In a multiprocessor system having a large-capacity memory having a large storage capacity and a high-speed memory that can be accessed at a higher speed than the large-capacity memory, each processor accesses the high-speed memory and performs calculation processing. In general, the storage capacity of the high-speed memory is smaller than the storage capacity of the large-capacity memory. In this type of multiprocessor system, data transfer is not directly performed between the high-speed memory and the computer, and input data necessary for calculation processing of each processor is temporarily stored in a large-capacity memory.

  For example, each processor transfers input data stored in a large-capacity memory to a high-speed memory, and performs calculation processing using the input data stored in the high-speed memory. Each processor temporarily stores the output data as a result of the calculation process in the high-speed memory, and transfers the output data stored in the high-speed memory to the large-capacity memory.

  As described above, each processor accesses a low-speed large-capacity memory each time it performs a calculation process. As the number of accesses to the large-capacity memory increases, the memory access time increases.

JP 56-164464 A JP-A 63-156268 JP-A-1-134657 JP-A-2-184958

  An object of the present invention is to adjust the calculation processing capability of a multiprocessor system and the processing capability of data transfer between the multiprocessor and the memory.

  In one embodiment of the present invention, a multiprocessor system includes a first memory and a processing unit that is connected to the first memory and performs processing using data stored in the first memory. The processing unit includes a second memory, a first processor that performs data transfer for transferring at least one of data and processing data as a result of the processing between the first memory and the second memory, the first memory, A second processor that can switch between data transfer and processing between the two memories and a third processor that performs processing using the data transferred to the second memory.

  The efficiency of calculation processing of the multiprocessor system can be improved.

1 illustrates an example of a multiprocessor system in one embodiment. 2 shows an example of the operation of the multiprocessor system shown in FIG. 6 shows another example of the operation of the multiprocessor system shown in FIG. An example of the operation of the multiprocessor system when the processing of the processor PU2 shown in FIG. 1 is switched is shown. 6 shows another example of the operation of the multiprocessor system when the processing of the processor PU2 shown in FIG. 1 is switched. An example of the operation of the processor PU1 shown in FIG. 1 is shown. An example of the operation of the processor PU2 shown in FIG. 1 is shown. An example of the operation of processors PU other than the processors PU1 and PU2 shown in FIG. 1 is shown. 3 illustrates an example of a multiprocessor system in another embodiment. 6 illustrates an example of the operation of a multiprocessor system in another embodiment. The example of the system by which the multiprocessor system of embodiment mentioned above is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a multiprocessor system PSYS in one embodiment. In addition, the broken line in a figure has shown an example of the flow of data. The multiprocessor system PSYS has an external memory MEM and a processing unit MP connected to the external memory MEM. The external memory MEM is a memory formed by, for example, a DRAM (Dynamic RAM) or the like, and stores data transferred between an external device such as a computer and the multiprocessor system PSYS. In this embodiment, the storage capacity of the external memory MEM is larger than the storage capacity of the internal memory IMEM described later.

  The processing unit MP performs a calculation process using data stored in the external memory MEM. The processing unit MP includes an internal memory IMEM and a plurality of processors PU (PU1, PU2, PU3, PU4,...) Connected to the internal memory IMEM. The internal memory IMEM is accessed from each processor PU and operates faster than the external memory MEM.

  Each processor PU is connected to the external memory MEM, and operates based on, for example, a program stored in the external memory MEM. For example, when the processing unit MP performs a calculation process using data stored in the external memory MEM, one of the processors PU (processor PU1 in FIG. 1) transfers data between the external memory MEM and the internal memory IMEM. (Fig. 1 (a, b)). For example, when the processing unit MP performs calculation processing using data stored in the external memory MEM, the processor PU1 repeatedly performs data transfer between the external memory MEM and the internal memory IMEM without performing calculation processing. To do. The processor PU1 performs data transfer for transferring at least one of input data and output data for calculation processing between the external memory MEM and the internal memory IMEM. For example, the input data is data used for calculation processing, and the output data is the result of calculation processing.

  Further, when the processing unit MP performs a calculation process using data stored in the external memory MEM, one of the processors PU (processor PU2 in FIG. 1) transfers data between the external memory MEM and the internal memory IMEM. (FIG. 1 (c)) and calculation processing are performed in a switchable manner. In other words, the processor PU2 switches between data transfer and calculation processing so as to adjust the calculation processing capability of the processing unit MP and the data transfer capability between the processing unit MP and the external memory MEM.

  For example, when the time required for the calculation process is relatively longer than the time required for the data transfer, the processor PU2 accesses the internal memory IMEM (FIG. 1 (d)) and performs the calculation process. For example, when the time required for the calculation process is relatively short with respect to the time required for data transfer, the processor PU2 transfers data from the external memory MEM to the internal memory IMEM instead of the processor PU1 ( FIG. 1 (c)).

  When the processing unit MP performs a calculation process using data stored in the external memory MEM, the processors PU (PU3, PU4,... In FIG. 1) other than the processors PU1 and PU2 access the internal memory IMEM. Then, the calculation process is performed (FIG. 1D). That is, the processors PU (in FIG. 1, PU3, PU4,...) Other than the processors PU1 and PU2 perform calculation processing using the input data stored in the internal memory IMEM. The processor PU3 and the like perform the calculation process without accessing the low-speed external memory MEM, for example, so that the calculation process can be performed efficiently. Note that the processing of the processor PU1 may be performed by any processor PU other than the processor PU1, and the processing of the processor PU2 may be performed by any processor PU other than the processor PU2. Further, the number of processors PU in the processing unit MP is not limited to four or more, and may be three, for example.

  FIG. 2 shows an example of the operation of the multiprocessor system PSYS shown in FIG. FIG. 2 shows operations of the processors PU1, PU2, PU3, and PU4 when performing a calculation process using data stored in the external memory MEM. For example, the operations of the processors PU other than the processors PU1, PU2, PU3, and PU4 are the same as those of the processor PU3.

  A symbol R in the drawing indicates that processing for reading data from the external memory MEM is being performed. A symbol W indicates that a process of writing data to the external memory MEM is being performed. The symbol r indicates that processing for reading data from the internal memory IMEM is being performed. A symbol w indicates that a process of writing data to the internal memory IMEM is being performed. The symbol CAL indicates that calculation processing is being performed.

  In addition, solid arrows other than the arrow indicating the time in the figure indicate the flow of the input data IDATA for calculation processing. Dashed arrows indicate the flow of output data ODATA that is the result of the calculation process. A thick arrow indicates that access is performed at a lower speed than a thin arrow. The number at the end of the code of the output data ODATA corresponds to the number at the end of the code of the input data IDATA. For example, the output data ODATA1 is a result of calculation processing using the input data IDATA1.

  The external memory MEM stores input data IDATA used for calculation processing in advance. For example, a computer using the multiprocessor system PSYS transfers the input data IDATA to the external memory MEM of the multiprocessor system PSYS before causing the multiprocessor system PSYS to perform calculation processing.

  First, the processor PU1 reads the input data IDATA1 from the external memory MEM (FIG. 2 (a)), and writes the read input data IDATA1 to the internal memory IMEM (FIG. 2 (b)). Then, the processors PU2, PU3, and PU4 read the input data IDATA1 from the internal memory IMEM (FIG. 2 (c)), and perform a calculation process CAL using the input data IDATA1.

  Further, the processor PU1 reads the input data IDATA2 next to the input data IDATA1 from the external memory MEM without waiting for the end of the calculation processing CAL of the processors PU2, PU3, PU4 (FIG. 2 (d)). Then, the processor PU1 writes the read input data IDATA2 in the internal memory IMEM (FIG. 2 (e)). In this way, the processor PU1 first transfers the input data IDATA1 and IDATA2 for two times of the calculation process CAL from the external memory MEM to the internal memory IMEM.

  When the calculation process CAL using the input data IDATA1 is completed, the processors PU2, PU3, and PU4 write the output data ODATA1 as a calculation result to the internal memory IMEM (FIG. 2 (f)). Then, the processors PU2, PU3, and PU4 read the input data IDATA2 from the internal memory IMEM (FIG. 2 (g)), and perform a calculation process CAL using the input data IDATA2.

  The input data IDATA2 is written to the internal memory IMEM by the processor PU1 before the calculation process CAL using the input data IDATA1 is completed. Accordingly, the processors PU2, PU3, and PU4 can read the input data IDATA2 from the internal memory IMEM immediately after writing the output data ODATA1 to the internal memory IMEM. Further, the internal memory IMEM operates at a higher speed than the external memory MEM. Therefore, in this embodiment, the interval from the end of the first calculation process CAL to the start of the second calculation process CAL can be shortened.

  When the output data ODATA1 is written to the internal memory IMEM, the processor PU1 reads the output data ODATA1 from the internal memory IMEM (FIG. 2 (h)), and writes the read output data ODATA1 to the external memory MEM (FIG. 2 (i) )). Then, the processor PU1 reads the input data IDATA3 next to the input data IDATA2 from the external memory MEM (FIG. 2 (j)), and writes the read input data IDATA3 to the internal memory IMEM (FIG. 2 (k)).

  For example, the processor PU1 writes the input data IDATA3 to the internal memory IMEM before the writing of the output data ODATA2 to the internal memory IMEM by the processors PU2, PU3, and PU4 is completed. That is, the processor PU1 writes the input data IDATA3 to the internal memory IMEM before the processors PU2, PU3, and PU4 perform the read operation of the input data ODATA3.

  Thus, for example, the processor PU1 does not perform calculation processing by itself, but transfers data that transfers input data IDATA from the external memory MEM to the internal memory IMEM, and transfers output data ODATA from the internal memory IMEM to the external memory MEM. Repeat data transfer.

  For example, each time the input data IDATA is transferred to the internal memory IMEM, the processors PU2, PU3, and PU4 perform the calculation process CAL using the input data IDATA stored in the internal memory IMEM. In order for the processor PU1 to specially perform data transfer between the low-speed external memory MEM and the high-speed internal memory IMEM, the processors PU2, PU3, and PU4 perform the calculation processing CAL without accessing the low-speed external memory MEM. Can be implemented.

  FIG. 3 shows another example of the operation of the multiprocessor system PSYS shown in FIG. The meanings of the arrows in the figure are the same as those in FIG. The operation of the multiprocessor system PSYS shown in FIG. 3 is the same as that of FIG. 2 except for the operations of the processors PU1 and PU2.

  For example, the processor PU2 transfers the input data IDATA from the external memory MEM to the internal memory IMEM instead of the processor PU1 (FIG. 3 (a, b)). Therefore, the processor PU1 does not read the input data IDATA while the processor PU2 is transferring the input data IDATA from the external memory MEM to the internal memory IMEM, and does not read the input data IDATA from the internal memory IMEM to the external memory MEM. (Fig. 3 (c, d)).

  For example, the multiprocessor system PSYS performs in parallel processing of writing output data ODATA to the external memory MEM by the processor PU1 and processing of reading input data IDATA from the external memory MEM by the processor PU2. Thereby, in this embodiment, even when the time of the calculation process CAL of each processor PU is short, the input data IDATA necessary for the calculation process CAL can be written in the internal memory IMEM in advance.

  For example, the input data IDATA12 is written to the internal memory IMEM by the processor PU2 before all the output data ODATA11 of the calculation process CAL using the input data IDATA11 is written to the internal memory IMEM. Therefore, in this embodiment, the interval from the end of the calculation process CAL to the start of the next calculation process CAL can be shortened.

  FIG. 4 shows an example of the operation of the multiprocessor system PSYS when the processing of the processor PU2 shown in FIG. 1 is switched. 4 shows operations of the processors PU1, PU2, PU3, and PU4 when the operation shown in FIG. 2 is switched to the operation shown in FIG. For example, the operations of the processors PU other than the processors PU1, PU2, PU3, and PU4 are the same as those of the processor PU3. The meanings of the arrows other than the double-lined arrow in the figure are the same as those in FIG. In addition, the double-lined arrow in a figure has shown that the process of processor PU2 switches. Also, a reference PU2 with parentheses indicates an operation of the processor PU2 after the process is switched.

  For example, the processors PU2, PU3, and PU4 write the output data ODATA2 to the internal memory IMEM (FIG. 4A). Then, the processors PU2, PU3, and PU4 write the output data ODATA2 to the internal memory IMEM, and then access the internal memory IMEM to read the input data IDATA3. At this time, since the input data IDATA3 is not stored in the internal memory IMEM, the processors PU2, PU3, and PU4 stand by until the input data IDATA3 is written in the internal memory IMEM (FIG. 4B).

  The processor PU1 transfers the input data IDATA3 from the external memory MEM to the internal memory IMEM (FIG. 4 (c, d)). Since the input data IDATA3 is written in the internal memory IMEM, the processors PU2, PU3, and PU4 read the input data IDATA3 from the internal memory IMEM (FIG. 4 (e)), and perform a calculation process CAL using the input data IDATA3. When the calculation process CAL using the input data IDATA3 is completed, the processors PU2, PU3, and PU4 write the output data ODATA3 to the internal memory IMEM (FIG. 4 (f)).

  The processor PU1 transfers the input data IDATA3 from the external memory MEM to the internal memory IMEM, and then transfers the output data ODATA2 from the internal memory IMEM to the external memory MEM (FIG. 4 (g, h)). Then, the processor PU1 transfers the input data IDATA4 from the external memory MEM to the internal memory IMEM (FIG. 4 (i, j)). Further, the processor PU1 transfers the output data ODATA3 from the internal memory IMEM to the external memory MEM (FIG. 4 (k, l)).

  Here, for example, because the processor PU2 waits when reading the input data IDATA3, the processing to be performed after the output data ODATA3 is written to the internal memory IMEM is switched from the calculation processing CAL to the data transfer (FIG. 4). Double arrow). For example, the processor PU2 transfers the input data IDATA5 from the external memory MEM to the internal memory IMEM after the processor PU1 reads the output data ODATA3 from the internal memory IMEM (FIG. 4 (m, n)). As described above, when the waiting state occurs in reading the input data IDATA from the internal memory IMEM, the processing of the processor PU2 is switched from the calculation processing CAL to the data transfer.

  After the input data IDATA4 is written to the internal memory IMEM, the processors PU3 and PU4 read the input data IDATA4 from the internal memory IMEM (FIG. 4 (o)), and perform the calculation process CAL using the input data IDATA4. The input data IDATA4 is transferred from the external memory MEM to the internal memory IMEM by the processor PU1 before the processing of the processor PU2 is switched to data transfer.

  When the calculation process CAL using the input data IDATA4 is completed, the processors PU3 and PU4 write the output data ODATA4 to the internal memory IMEM (FIG. 4 (p)). At this time, the input data IDATA5 has already been written in the internal memory IMEM by the processor PU2. Therefore, the processors PU3 and PU4 read the input data IDATA5 from the internal memory IMEM without writing the output data ODATA4 to the internal memory IMEM and waiting for the input data IDATA5 to be written to the internal memory IMEM. (FIG. 4 (q)). Thereby, the processors PU3 and PU4 can efficiently perform the calculation process CAL.

  The operation of each processor PU after the processor PU2 transfers the input data IDATA5 from the external memory MEM to the internal memory IMEM is, for example, the same as that in FIG. For example, the processor PU1 repeatedly performs data transfer for transferring the output data ODATA from the internal memory IMEM to the external memory MEM during the period in which the processor PU2 is transferring the input data IDATA from the external memory MEM to the internal memory IMEM.

  FIG. 5 shows another example of the operation of the multiprocessor system PSYS when the processing of the processor PU2 shown in FIG. 1 is switched. FIG. 5 shows operations of the processors PU1, PU2, PU3, and PU4 when the operation shown in FIG. 3 is switched to the operation shown in FIG. For example, the operations of the processors PU other than the processors PU1, PU2, PU3, and PU4 are the same as those of the processor PU3. The meanings of the arrows in the figure are the same as those in FIG. 4 described above. Also, a reference PU2 with parentheses indicates an operation of the processor PU2 after the process is switched.

  For example, the processor PU1 writes the output data ODATA20 to the external memory MEM (FIG. 5A). For example, when the writing of the output data ODATA20 to the external memory MEM by the processor PU1 is started, the processor PU2 transfers the input data IDATA22 from the external memory MEM to the internal memory IMEM (FIG. 5 (b, c)). . Further, for example, the processors PU3 and PU4 write the output data ODATA21 to the internal memory IMEM (FIG. 5 (d)).

  When the output data ODATA21 is written in the internal memory IMEM, the processor PU1 transfers the output data ODATA21 from the internal memory IMEM to the external memory MEM (FIG. 5 (e, f)). Here, for example, when the writing of the output data ODATA20 to the external memory MEM by the processor PU1 is finished, the writing of the output data ODATA21 to the internal memory IMEM by the processors PU3 and PU4 is not finished. For this reason, when the processor PU1 reads the output data ODATA21 from the internal memory IMEM, a waiting state occurs (FIG. 5 (g)).

  For example, when the waiting time (waiting time) of the processor PU1 is longer than a preset threshold time T1, the processing of the processor PU2 switches from data transfer to calculation processing CAL (double-line arrow in FIG. 5). That is, when the time of the calculation process CAL is relatively long with respect to the time required for data transfer, the processor PU2 performs the calculation process CAL. Further, the processor PU1 resumes data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM because the processing of the processor PU2 is switched from data transfer to calculation processing CAL. For example, the processor PU1 transfers the output data ODATA21 from the internal memory IMEM to the external memory MEM, and then transfers the input data IDATA23 from the external memory MEM to the internal memory IMEM (FIG. 5 (h, i)).

  The processors PU3 and PU4 read the input data IDATA22 from the internal memory IMEM (FIG. 5 (j)), and write the output data ODATA22 as a result of the calculation process CAL using the input data IDATA22 to the internal memory IMEM (FIG. 5 (k)). )). Then, after the input data IDATA23 is written to the internal memory IMEM, the processors PU2, PU3, and PU4 read the input data IDATA23 from the internal memory IMEM (FIG. 5 (l)), and perform the calculation process CAL using the input data IDATA23. carry out.

  Thus, when the standby time of the processor PU1 is longer than the preset threshold time T1, the processor PU2 is added to the processor PU that performs the calculation process CAL. Therefore, the multiprocessor system PSYS can efficiently execute the calculation process CAL. . That is, in this embodiment, when the time of the calculation process CAL is relatively long with respect to the time required for data transfer, it is possible to prevent the number of processors PU that perform the calculation process CAL from decreasing. For this reason, the multiprocessor system PSYS can efficiently perform the calculation process CAL.

  When the output data ODATA22 is written in the internal memory IMEM, the processor PU1 transfers the output data ODATA22 from the internal memory IMEM to the external memory MEM (FIG. 5 (m, n)). For example, the processor PU1 repeatedly performs data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM and data transfer for transferring the output data ODATA from the internal memory IMEM to the external memory MEM. For example, the processors PU2, PU3, and PU4 perform the calculation process CAL every time the input data IDATA is transferred to the internal memory IMEM.

  FIG. 6 shows an example of the operation of the processor PU1 shown in FIG. Processes S100 to S126 are performed based on a program stored in the external memory MEM, for example. Prior to the processing S100, the input data IDATA is stored in the external memory MEM. Further, for example, the processor PU (PU1 or PU2) that has read the last input data IDATA writes a final flag indicating that the last input data IDATA has been read into the external memory MEM. Note that flags other than the final flag (such as IDATA transfer permission flag) are stored in the internal memory IMEM, for example. For example, the initial value of each flag is “0”.

  In process S100, the processor PU1 transfers the first input data IDATA from the external memory MEM to the internal memory IMEM. In process S102, the processor PU1 determines whether or not the last input data IDATA has been transferred from the external memory MEM to the internal memory IMEM. For example, the processor PU1 determines whether or not a final flag indicating that the last input data IDATA has been read is written in the external memory MEM.

  When the last input data IDATA is transferred from the external memory MEM to the internal memory IMEM (Yes in process S102), the operation of the processor PU1 moves to process S120. On the other hand, when the last input data IDATA has not been transferred from the external memory MEM to the internal memory IMEM (No in process S102), the operation of the processor PU1 proceeds to process S104.

  In process S104, the processor PU1 determines whether only the processor PU1 is performing data transfer between the external memory MEM and the internal memory IMEM. That is, the processor PU1 determines whether or not the processor PU2 transfers the input data IDATA from the external memory MEM to the internal memory IMEM. For example, the processor PU1 determines whether or not the processor PU2 transfers the input data IDATA from the external memory MEM to the internal memory IMEM by referring to a PU2 data transfer flag indicating processing executed by the processor PU2.

  Here, for example, when the processing of the processor PU2 is data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM, the PU2 data transfer flag is set to “1” (processing S218 in FIG. 7 described later). The Further, for example, when the process of the processor PU2 is a calculation process, the PU2 data transfer flag is cleared to “0” (process S228 in FIG. 7).

  When only the processor PU1 performs data transfer between the external memory MEM and the internal memory IMEM (Yes in process S104), the operation of the processor PU1 proceeds to process S106. That is, when the process of the processor PU2 is a calculation process, the operation of the processor PU1 moves to process S106. On the other hand, when the process of the processor PU2 is a data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM (No in process S104), the operation of the processor PU1 proceeds to process S108.

  In the process S106, the processor PU1 clears the IDATA transfer permission flag to “0”, and transfers the input data IDATA from the external memory MEM to the internal memory IMEM. Here, the IDATA transfer permission flag is a flag that is referred to by the processor PU2 in order to determine when the processor PU2 reads the input data IDATA from the external memory MEM. For example, the IDATA transfer permission flag is referred to by the processor PU2 in step S222 in FIG.

  In process S108, the processor PU1 sets the evaluation value EV1 to “0”. Here, the evaluation value EV1 is information referred to by the processor PU2, for example, and is stored in the internal memory IMEM. For example, the evaluation value EV1 is referred to by the processor PU2 in the process S226 of FIG. 7 in order to determine whether or not the processor PU2 continues the data transfer.

  In process S110, the processor PU1 reads the output data ODATA from the internal memory IMEM. In process S112, the processor PU1 determines whether or not the output data ODATA has been successfully read. For example, the processor PU1 fails to read the output data ODATA in a period before the output data ODATA to be read is written in the internal memory IMEM.

  When reading of the output data ODATA has failed (No in step S112), the processor PU1 increases the evaluation value EV1 by “1” in step S114. Then, the operation of the processor PU1 proceeds to process S110. As described above, the processor PU1 repeatedly performs the operations of steps S110, S112, and S114 until the output data ODATA is successfully read.

  On the other hand, when the output data ODATA has been successfully read (Yes in step S112), the processor PU1 subtracts “1” from the evaluation value EV1 and sets the IDATA transfer permission flag to “1” in step S116. The processor PU1 may set the IDATA transfer permission flag to “1” in step S108 instead of setting the IDATA transfer permission flag to “1” in step S116.

  In process S118, the processor PU1 writes the output data ODATA to the external memory MEM. Then, the operation of the processor PU1 returns to the process S102. In this way, the processor PU1 repeatedly performs the operations of steps S102 to S118 until the last input data IDATA is transferred from the external memory MEM to the internal memory IMEM.

  When the last input data IDATA is transferred from the external memory MEM to the internal memory IMEM (Yes in process S102), the processor PU1 reads the output data ODATA from the internal memory IMEM in process S120.

  In process S122, the processor PU1 determines whether or not the output data ODATA has been successfully read. When reading of the output data ODATA has failed (No in process S122), the operation of the processor PU1 returns to process S120. On the other hand, when the output data ODATA has been successfully read (Yes in process S122), the processor PU1 sets an end flag in data indicating the end of the calculation process (for example, “1”) in process S124.

  Here, the end flag is, for example, a processor PU (PU2, PU3, PU4, etc.) that performs the calculation process in order to determine whether the calculation process using the input data IDATA stored in the external memory MEM has ended. ) Is a flag referred to. For example, the processor PU1 writes an end flag in the internal memory IMEM as the input data IDATA of the processor PU that performs the calculation process. Thereby, for example, the end flag is referred to by the processors PU2, PU3, etc. (processing S212 in FIG. 7 and processing S304 in FIG. 8 described later).

  In process S126, the processor PU1 writes the output data ODATA to the external memory MEM. Thereby, the processing of the processor PU1 ends. The operation of the processor PU1 is not limited to this example. The processor PU1 may switch whether or not to perform data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM in accordance with the processing of the processor PU2.

  FIG. 7 shows an example of the operation of the processor PU2 shown in FIG. Processes S200 to S228 are performed based on, for example, a program stored in the external memory MEM. For example, the PU2 data transfer flag is stored in the internal memory IMEM. Note that the initial value of the PU2 data transfer flag is, for example, “0”.

  In the process S200, the processor PU2 reads the first input data IDATA from the internal memory IMEM, and performs a calculation process using the read input data IDATA. Then, the processor PU2 writes the output data ODATA that is the result of the calculation process to the internal memory IMEM.

  In the process S202, the processor PU2 sets the evaluation value EV2 to “0”. Here, the evaluation value EV2 is information for determining whether reading of the input data IDATA has failed, for example, and is stored in the internal memory IMEM. In process S204, the processor PU2 reads the input data IDATA from the internal memory IMEM.

  In process S206, the processor PU2 determines whether or not the input data IDATA has been successfully read. For example, the processor PU2 fails to read the input data IDATA in a period before the input data IDATA to be read is written in the internal memory IMEM.

  When reading of the input data IDATA has failed (No in process S206), the processor PU2 increases the evaluation value EV2 by “1” in process S208. Then, the operation of the processor PU2 proceeds to process S204. As described above, the processor PU2 repeatedly performs the operations of steps S204, S206, and S208 until the input data IDATA is successfully read. On the other hand, when the input data IDATA has been successfully read (Yes in step S206), the processor PU2 subtracts “1” from the evaluation value EV2 in step S210.

  In the process S212, the processor PU2 determines whether or not the read input data IDATA is an end flag. The end flag indicates that all the calculation processes have been completed as described with reference to FIG. Therefore, when the read input data IDATA is an end flag (Yes in step S212), the processing of the processor PU2 ends. On the other hand, when the read input data IDATA is not the end flag (No in process S212), the operation of the processor PU2 proceeds to process S214.

  In the process S214, the processor PU2 performs a calculation process using the read input data IDATA. Then, the processor PU2 writes the output data ODATA that is the result of the calculation process to the internal memory IMEM. In the process S216, the processor PU2 determines whether or not the evaluation value EV2 is “0” or more. That is, the processor PU2 determines whether or not reading of the input data IDATA has failed at least once.

  Note that a value equal to or greater than “0” may be set in advance as the determination criterion in step S216. In the process S216 at this time, for example, the processor PU2 determines whether or not the evaluation value EV2 is equal to or greater than a preset value. That is, the processor PU2 may determine whether or not the reading of the input data IDATA has failed for a preset number of times.

  When reading of the input data IDATA has never failed (No in process S216), the operation of the processor PU2 returns to process S202. On the other hand, when the reading of the input data IDATA has failed one or more times (Yes in process S216), the operation of the processor PU2 proceeds to process S218. As described above, the processor PU2 repeatedly performs the calculation process (operations in steps S202 to S216) in a period in which no waiting state occurs when the input data IDATA is read. That is, the processor PU2 repeatedly performs calculation processing (operations S202 to S216) until a waiting state occurs when the input data IDATA is read.

  In the process S218, the processor PU2 sets the PU2 data transfer flag to “1”. Thereby, the processor PU1 detects that the process of the processor PU2 has switched from the calculation process to the data transfer (data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM) in the process S104 shown in FIG. it can.

  In process S220, the processor PU2 determines whether or not the last input data IDATA has been transferred from the external memory MEM to the internal memory IMEM. For example, the processor PU2 determines whether or not a final flag indicating that the last input data IDATA has been read is written in the external memory MEM.

  When the last input data IDATA is transferred from the external memory MEM to the internal memory IMEM (Yes in process S220), the process of the processor PU2 ends. Note that when the last input data IDATA is transferred from the external memory MEM to the internal memory IMEM, the operation of the processor PU2 may move to step S202. On the other hand, when the last input data IDATA has not been transferred from the external memory MEM to the internal memory IMEM (No in process S220), the operation of the processor PU2 proceeds to process S222.

  In process S222, the processor PU2 determines whether or not transfer of the input data IDATA from the external memory MEM to the internal memory IMEM is permitted. For example, when the IDATA transfer permission flag is “0”, the processor PU2 determines that the transfer of the input data IDATA is not permitted. For example, when the IDATA transfer permission flag is “1”, the processor PU2 determines that the transfer of the input data IDATA is permitted.

  When transfer of the input data IDATA from the external memory MEM to the internal memory IMEM is not permitted (No in process S222), the operation of the processor PU2 returns to process S222. That is, the processor PU2 waits until transfer of the input data IDATA is permitted. Thus, in this embodiment, it is possible to prevent the transfer of the input data IDATA from the external memory MEM to the internal memory IMEM from being excessively preceded by the calculation process of the processor PU3 and the like.

  On the other hand, when transfer of the input data IDATA from the external memory MEM to the internal memory IMEM is permitted (Yes in process S222), the operation of the processor PU2 proceeds to process S224. In the process S224, the processor PU2 clears the IDATA transfer permission flag to “0”, and transfers the input data IDATA from the external memory MEM to the internal memory IMEM.

  In the process S226, the processor PU2 determines whether or not the evaluation value EV1 is greater than or equal to the threshold value TH. Here, the threshold value TH is, for example, a value equal to or greater than “0” set by the user or the like when executing the application. For example, the threshold value TH is stored in the internal memory IMEM. That is, the processor PU2 determines whether or not reading of the output data ODATA by the processor PU1 has failed more than the threshold TH.

  When the number of failures to read the output data ODATA is less than the threshold value TH (No in process S226), the operation of the processor PU2 returns to process S220. That is, when the standby time of the processor PU1 (the above-described FIG. 5G, etc.) is shorter than a preset threshold time, for example, the processor PU2 continues to transfer the input data IDATA from the external memory MEM to the internal memory IMEM. And implement.

  On the other hand, when the number of failures to read the output data ODATA is equal to or greater than the threshold value TH (Yes in process S226), the processor PU2 clears the PU2 data transfer flag to “0” in process S228. Then, the operation of the processor PU2 returns to the process of process S202. That is, when the standby time of the processor PU1 is longer than a preset threshold time, for example, the processing of the processor PU2 is switched from data transfer to calculation processing.

  Thus, when the time for the calculation process is relatively long with respect to the time required for data transfer, the processor PU2 performs the calculation process. When the calculation processing time is relatively short with respect to the time required for data transfer, the processor PU2 performs data transfer between the external memory MEM and the internal memory IMEM. Thereby, the multiprocessor system PSYS can efficiently perform the calculation process. The operation of the processor PU2 is not limited to this example. The processor PU2 only needs to be able to switch between data transfer and calculation processing between the external memory MEM and the internal memory IMEM in accordance with the data transfer time and calculation processing time of the processor PU1.

  FIG. 8 shows an example of the operations of the processors PU other than the processors PU1 and PU2 shown in FIG. The processes S300 to S306 are performed based on a program stored in the external memory MEM, for example. The operations of the processors PU other than the processors PU1 and PU2 are the same as those of the processor PU3. Therefore, the operation of the processor PU3 will be described.

  In process S300, the processor PU3 reads input data IDATA from the internal memory IMEM. In process S302, the processor PU3 determines whether or not the input data IDATA has been successfully read. When reading of the input data IDATA has failed (No in step S302), the operation of the processor PU3 returns to step S300. That is, the processor PU3 waits until the input data IDATA is successfully read.

  On the other hand, when the input data IDATA has been successfully read (Yes in process S302), the processor PU3 determines whether or not the read input data IDATA is an end flag in process S304. When the read input data IDATA is an end flag (Yes in process S304), the process of the processor PU3 ends. On the other hand, when the read input data IDATA is not an end flag (No in process S304), the operation of the processor PU3 proceeds to process S306.

  In the process S306, the processor PU3 performs a calculation process using the read input data IDATA, and writes the output data ODATA as a result of the calculation process in the internal memory IMEM. Then, the operation of the processor PU3 returns to the process S300. Thus, for example, the processor PU3 repeatedly performs the calculation process until the end flag is read.

  As described above, in this embodiment, the processor PU1 performs data transfer between the external memory MEM and the internal memory IMEM, and the processor PU2 switches between calculation processing and data transfer according to the calculation processing time. For example, when the calculation process time is relatively long with respect to the time required for data transfer, the processor PU2 performs the calculation process. When the calculation processing time is relatively short with respect to the time required for data transfer, the processor PU2 performs data transfer between the external memory MEM and the internal memory IMEM. Further, processors other than the processors PU1 and PU2 perform calculation processing without accessing the low-speed external memory MEM. As a result, in this embodiment, the calculation processing efficiency of the multiprocessor system PSYS can be improved.

  FIG. 9 shows an example of a multiprocessor system PSYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The multiprocessor system PSYS of this embodiment has, for example, a plurality of processing units MP. Other configurations are the same as those of the above-described embodiment. The operation of the processor PU of each processing unit MP is the same as that in the above-described embodiment.

  For example, as described with reference to FIG. 6, the processor PU (PU1 or PU2) that has read the last input data IDATA writes a final flag indicating that the last input data IDATA has been read into the external memory MEM. For this reason, the processors PU1 and PU2 of each processing unit MP determine whether or not the last input data IDATA has been transferred from the external memory MEM to the internal memory IMEM by referring to the final flag stored in the external memory MEM. it can. In other words, in a configuration with one processing unit MP, the final flag may be stored in the internal memory IMEM.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, since a plurality of processing units MP can perform calculation processing in parallel, the efficiency of calculation processing of the multiprocessor system PSYS can be further improved.

  FIG. 10 shows an example of the operation of the multiprocessor system PSYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The multiprocessor system PSYS of this embodiment is the same as the above-described embodiment except for the operations of the processors PU1 and PU2. In addition, the meaning of the arrow in a figure is the same as FIG. 4 mentioned above. Also, a reference PU2 with parentheses indicates an operation of the processor PU2 after the process is switched.

  For example, the processor PU2 is the same as that in the above-described embodiment except for the operation when performing data transfer between the external memory MEM and the internal memory IMEM. For example, when a wait state occurs in the calculation process CAL, the processor PU2 transfers the input data IDATA from the external memory MEM to the internal memory IMEM shown in FIG. Transfer to MEM is performed (double line arrow in FIG. 10).

  That is, the processor PU2 performs data transfer for transferring the output data ODATA from the internal memory IMEM to the external memory MEM as data transfer performed when a wait state occurs in the calculation process CAL. Therefore, the update of the evaluation value EV1 and the setting of the IDATA transfer permission flag shown in FIG. 6 are performed by the processor PU2.

  For example, when the processing of the processor PU2 is a data transfer in which the output data ODATA is transferred from the internal memory IMEM to the external memory MEM, the processor PU1 refers to the IDATA transfer permission flag until the transfer of the input data IDATA is permitted. stand by. For example, when the IDATA transfer permission flag is “1”, the processor PU1 starts data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM. Thus, for example, when the processing of the processor PU2 is not the calculation processing CAL, the processor PU1 repeatedly performs data transfer for transferring the input data IDATA from the external memory MEM to the internal memory IMEM. Other operations of the processor PU1 are the same as those in the above-described embodiment.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 11 shows an example of a system SYS on which the multiprocessor system PSYS of the above-described embodiment is mounted. The system SYS has, for example, a multiprocessor system PSYS and a computer CSYS connected to the multiprocessor system PSYS. The computer CSYS includes, for example, a central processing unit CPU that controls the operation of the system SYS, a hard disk HDD connected to the central processing unit CPU, and a main memory MM connected to the central processing unit CPU. For example, the central processing unit CPU transfers input data stored in the main memory MM to the external memory MEM of the multiprocessor system PSYS.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first memory;
A processing unit connected to the first memory and performing processing using data stored in the first memory;
The processor is
A second memory;
A first processor that performs data transfer for transferring at least one of the data and processing data as a result of the processing between the first memory and the second memory;
A second processor that performs switching between data transfer between the first memory and the second memory and the processing;
And a third processor that performs the processing using the data transferred to the second memory.
(Appendix 2)
The first processor transfers the first data of the processing executed by the second processor and the third processor from the first memory to the second memory, and then transfers the first processing data of the processing. The multiprocessor system according to claim 1, wherein the data following the first data is transferred from the first memory to the second memory before being transferred from the second memory to the first memory.
(Appendix 3)
The second processor has a waiting time from writing the processing data of the previous processing in the continuous processing to the second memory until reading the data of the next processing from the second memory. Then, the processing to be performed is switched from the processing to the data transfer. The multiprocessor system according to Supplementary Note 1 or Supplementary Note 2.
(Appendix 4)
The second processor transfers the data from the first memory to the second memory as the data transfer,
The multiprocessor system according to claim 3, wherein the first processor transfers the processing data from the second memory to the first memory when the second processor executes the data transfer.
(Appendix 5)
The second processor transfers the processing data from the second memory to the first memory as the data transfer,
The multiprocessor system according to claim 3, wherein the first processor transfers the data from the first memory to the second memory when the second processor performs the data transfer.
(Appendix 6)
When the waiting time when the first processor reads the processing data from the second memory is longer than a preset threshold time, the second processor switches the processing to be performed from the data transfer to the processing. The multiprocessor system according to Supplementary Note 3, wherein the multiprocessor system is characterized.
(Appendix 7)
A multiprocessor system comprising: a first memory; and a processing unit connected to the first memory and including a second memory and a plurality of processors. The multiprocessor system executes processing using data stored in the first memory. In the processor system program,
A first processor that is one of the plurality of processors transfers the data from the first memory to the second memory;
A second processor and a third processor, which are one of the plurality of processors, perform the processing, and store processing data as a result of the processing in the second memory;
The first processor accesses the second memory and transfers the stored processing data to the first memory;
When the timing at which the second processor and the third processor store the processing data in the second memory is earlier than the timing at which the first processor accesses the second memory, the operation of the second processor A program for a multiprocessor system, characterized in that:
(Appendix 8)
A multiprocessor system operating method comprising: a first memory; and a processing unit connected to the first memory and including a second memory and a plurality of processors, wherein the processing is performed using data stored in the first memory In
A first processor that is one of the plurality of processors transfers the data from the first memory to the second memory;
A second processor and a third processor, which are one of the plurality of processors, perform the processing, and store processing data as a result of the processing in the second memory;
The first processor accesses the second memory and transfers the stored processing data to the first memory;
When the timing at which the second processor and the third processor store the processing data in the second memory is earlier than the timing at which the first processor accesses the second memory, the operation of the second processor A method of operating a multiprocessor system, characterized in that:
(Appendix 9)
After the first data of the processing performed by the second processor and the third processor is transferred from the first memory to the second memory, the first processing data of the processing is transferred from the second memory. The multiprocessor according to claim 8, wherein the first processor transfers the data next to the first data from the first memory to the second memory before being transferred to the first memory. How the system works.
(Appendix 10)
When a waiting time occurs after the processing data of the previous processing in the continuous processing is written to the second memory until the data of the next processing is read from the second memory, the second The operation method of the multiprocessor system according to appendix 8 or appendix 9, wherein the process to be executed by the processor is switched from the process to the transfer.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  CPU, central processing unit; CSYS, computer; HDD, hard disk; IMEM, MEM, MM, memory; MP, processing unit; PSYS, multiprocessor system;

Claims (6)

A first memory;
A processing unit connected to the first memory and performing processing using data stored in the first memory;
The processor is
A second memory;
A first processor that performs data transfer for transferring at least one of the data and processing data as a result of the processing between the first memory and the second memory;
A second processor that performs switching between data transfer between the first memory and the second memory and the processing;
And a third processor that performs the processing using the data transferred to the second memory. The first processor transfers the first data of the processing executed by the second processor and the third processor from the first memory to the second memory, and then transfers the first processing data of the processing. 2. The multiprocessor system according to claim 1, wherein the data next to the first data is transferred from the first memory to the second memory before being transferred from the second memory to the first memory. . The second processor has a waiting time from writing the processing data of the previous processing in the continuous processing to the second memory until reading the data of the next processing from the second memory. The multiprocessor system according to claim 1, wherein the processing to be performed is switched from the processing to the data transfer. A multiprocessor system operating method comprising: a first memory; and a processing unit connected to the first memory and including a second memory and a plurality of processors, wherein the processing is performed using data stored in the first memory In
A first processor that is one of the plurality of processors transfers the data from the first memory to the second memory;
A second processor and a third processor, which are one of the plurality of processors, perform the processing, and store processing data as a result of the processing in the second memory;
The first processor accesses the second memory and transfers the stored processing data to the first memory;
When the timing at which the second processor and the third processor store the processing data in the second memory is earlier than the timing at which the first processor accesses the second memory, the operation of the second processor A method of operating a multiprocessor system, characterized in that: After the first data of the processing performed by the second processor and the third processor is transferred from the first memory to the second memory, the first processing data of the processing is transferred from the second memory. The multi-processor according to claim 4, wherein the first processor transfers the data next to the first data from the first memory to the second memory before being transferred to the first memory. How the processor system works. When a waiting time occurs after the processing data of the previous processing in the continuous processing is written to the second memory until the data of the next processing is read from the second memory, the second The operation method of the multiprocessor system according to claim 4 or 5, wherein a process executed by a processor is switched from the process to the transfer.

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