JP2011175377A - Flash memory control device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively use a flash memory, while increasing data rewriting frequency. <P>SOLUTION: A flash memory control device includes an arithmetic part and the flash memory. The flash memory has a plurality of areas DA1-DA3, PA1-PA3. The plurality of areas DA1-DA3, PA1-PA3 include: the program areas PA1-PA3 which store a program executed by the arithmetic part and wherein rewriting of data is not performed; and the data areas DA1-DA3 which store data and wherein rewriting of the data is performed. When a cumulative frequency at which the data are written reaches a maximum rewriting frequency, the arithmetic part executes exchange processing to a first area allocated as the data area DA3/DA1/DA2. In the exchange processing, the first area and a second area allocated as the program area PA3/PA2/PA1 are exchanged. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a flash memory control apparatus and method for controlling a flash memory.

  The number of products equipped with flash memory is increasing in electronic devices, and the number of scenes where flash memory is used as a maintenance and data area for electronic devices is increasing. In recent years, there has been an increasing demand for flash memory to be effectively used and increased in the number of data rewrites.

  Japanese Patent Application Laid-Open No. 2000-020405 describes a technique for increasing the number of data rewrites (referred to as a conventional flash memory control device).

  FIG. 1 shows the configuration of an electronic apparatus to which a conventional flash memory control device 101 is applied.

  The electronic device includes a conventional flash memory control device 101 and a peripheral device 103. The peripheral device 103 acquires data including characters and images by communication or input.

  A conventional flash memory control device 101 includes a CPU (Central Processing Unit) computing unit 102, a first flash memory (hereinafter referred to as a first FROM) 104, and a second flash memory (hereinafter referred to as a second FROM) 105. It has.

  The first FROM 104 is assigned to the program storage area at addresses 020000h to 03FFFFh. The program storage area stores a program executed by the arithmetic unit 102, and data is not rewritten.

  The second FROM 105 is allocated to the image information storage area of addresses 040000h to 05FFFFh. In the image information storage area, data acquired by the peripheral device is stored, and data is rewritten.

  The arithmetic unit 102 rewrites data in the first FROM 104 when the second FROM 105 reaches the end of its life and the rewrite speed becomes slow. In this case, the calculation unit 102 performs a replacement process.

  FIG. 2 is a flowchart showing replacement processing as the operation of the conventional flash memory control apparatus 101. FIG. 3A shows a program storage area and an image information storage area allocated to the first and second FROMs 104 and 105 before the replacement process is executed.

  In the replacement process, first, the calculation unit 102 stores the program stored in the program storage area at addresses 020000h to 03FFFFh in the image information storage area at addresses 040000h to 05FFFFh (step ST401). That is, the program stored in the first FROM 104 is stored in the second FROM 105.

  Next, the operation unit 102 assigns the image information storage area “addresses 040000h to 05FFFFh” and the program storage area “addresses 020000h to 03FFFFh” as the first and second FROMs 104 and 105, respectively (step ST402). That is, the first and second FROMs 104 and 105 are exchanged.

  Next, arithmetic unit 102 deletes the program stored in the image information storage area at addresses 040000h to 05FFFFh (step ST403). That is, the program stored in the first FROM 104 is erased.

  FIG. 3B shows the image information storage area and the program storage area assigned to the first and second FROMs 104 and 105, respectively, after the replacement process is executed.

  Thus, in the conventional flash memory control device 101, even if the second FROM 105 reaches the end of its life, data can be rewritten by the first FROM 104, so that the life of the flash memory can be approximately doubled.

JP 2000-020405 A

  Usually, the flash memory has a plurality of areas. However, in the conventional flash memory control device 101, the replacement process is executed when it is determined that the second FROM 105 has reached the end of life without using the maximum number of rewrites for each of the plurality of areas of the second FROM 105.

  That is, in the conventional flash memory control device 101, the first and second FROMs 104 and 105 in which the program and data are stored are determined without determining whether or not the maximum number of rewrites is used for each of the plurality of areas. The replacement process is executed, and the program is stored in the second FROM 105. Thus, in the conventional flash memory control apparatus 101, since the replacement process is executed by two flash memories, it cannot be said that the flash memory is effectively used.

  Therefore, there is a demand for a flash memory control device that can increase the number of data rewrites and can effectively use the flash memory.

  In the following, means for solving the problems will be described using the reference numerals used in the embodiments for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the mode for carrying out the invention, and the technical scope of the invention described in the claims. Must not be used to interpret

  The flash memory control device (1) of the present invention includes a calculation unit (2) and a flash memory (4). The flash memory (4) has a plurality of areas (DA1 to DA3, PA1 to PA3). In a plurality of areas (DA1 to DA3, PA1 to PA3), a program executed by the arithmetic unit (2) is stored, data is not rewritten, data is stored, and data is stored. And data areas (DA1 to DA3) to be rewritten. The calculation unit (2) performs data for the first area ("address 080000h to 08FFFFh" / "address 060000h to 06FFFFh" / "address 070000h to 07FFFFh") assigned as the data area (DA3 / DA1 / DA2). The replacement process is executed when the cumulative number of times of writing reaches the maximum number of rewrites. In the replacement process, the first area (“address 080000h to 08FFFFh” / “address 060000h to 06FFFFh” / “address 070000h to 07FFFFh”) and the second area (“address”) assigned as the program area (PA3 / PA2 / PA1) "050,000h to 05FFFFh" / "address 040000h to 04FFFFh" / "address 030000h to 03FFFFh").

  As described above, in the flash memory control device (1) of the present invention, as a first effect, one flash memory is subdivided into a plurality of areas including a program area and a data area, and each of the plurality of areas is divided. On the other hand, since it is determined whether or not the maximum number of times of rewriting is used and the replacement process is executed, the number of times of rewriting can be increased with only one flash memory.

  Further, in the flash memory control device (1) of the present invention, as a second effect, it can be said that the flash memory is effectively used because the replacement process is executed with only one flash memory.

  Therefore, according to the flash memory control device (1) of the present invention, the number of data rewrites can be increased and the flash memory can be used effectively.

FIG. 1 shows the configuration of an electronic apparatus to which a conventional flash memory control device 101 is applied. FIG. 2 is a flowchart showing replacement processing as the operation of the conventional flash memory control apparatus 101. FIG. 3A shows a program storage area and an image information storage area allocated to the first and second FROMs 104 and 105 before the replacement process is executed. FIG. 3B shows the image information storage area and the program storage area assigned to the first and second FROMs 104 and 105, respectively, after the replacement process is executed. FIG. 4 shows a configuration of an electronic apparatus to which the flash memory control device 1 according to the embodiment of the present invention is applied. FIG. 5 shows the data areas DA1 to DA3 of the flash memory 4. FIG. 6 shows the program area address management table 6. FIG. 7 is a flowchart showing the operation of the flash memory control device 1 according to the embodiment of the present invention. FIG. 8A shows the program area address management table 6 after the first replacement process is executed. FIG. 8B shows the program area address management table 6 after the second replacement process is executed. FIG. 8C shows the program area address management table 6 after the third replacement process is executed. FIG. 9A shows a plurality of areas PA1, PA2, PA3, DA1, DA2, and DA3 of the flash memory 4 before the first replacement process is executed. FIG. 9B shows a plurality of areas PA1, PA2, DA3, DA1, DA2, and PA3 of the flash memory 4 after the first replacement process is executed (before the second replacement process is executed). FIG. 9C shows a plurality of areas PA1, DA1, DA3, PA2, DA2, and PA3 of the flash memory 4 after the second replacement process is executed (before the third replacement process is executed). FIG. 9D shows a plurality of areas DA2, DA1, DA3, PA2, PA1, and PA3 of the flash memory 4 after the third replacement process is executed (before the fourth replacement process is executed). FIG. 9E shows a plurality of areas DA2, DA1, DA3, PA2, PA1, PA3 of the flash memory 4 used up to the maximum number of rewrites. FIG. 10A shows a plurality of areas PA1, PA2, and DA1 of the flash memory 4 before the first replacement process is executed. FIG. 10B shows a plurality of areas PA1, PA2, and DA1 of the flash memory 4 after the first replacement process is executed (before the second replacement process is executed). FIG. 10C shows a plurality of areas PA1, PA2, and DA1 of the flash memory 4 after the second replacement process (before the third replacement process is executed). FIG. 11A shows that a data area of a plurality of areas is composed of four sectors (sectors S10 to S13), and when one sector is 4 KB, a data area of 16 KB is shown. FIG. 11B shows that a data area of a plurality of areas is composed of 4 sectors (sectors S20 to S27), and when one sector is 4 KB, a data area of 32 KB is shown.

  Hereinafter, a flash memory control device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 shows a configuration of an electronic apparatus to which the flash memory control device 1 according to the embodiment of the present invention is applied.

  The electronic device includes a flash memory control device 1 according to an embodiment of the present invention and peripheral devices. The peripheral device acquires data including characters and images by communication or input.

  A flash memory control device 1 according to an embodiment of the present invention includes a calculation unit 2 that is a CPU (Central Processing Unit) and a flash memory 4.

  The flash memory 4 has a plurality of areas.

  The plurality of areas include a program area where data is not rewritten and a data area where data is rewritten.

  In the program area, a program executed by the calculation unit 2 is stored.

  Data acquired by the peripheral device 103 is stored in the data area.

  Hereinafter, for convenience of explanation, the number of data areas in the plurality of areas of the flash memory 4 is 3, which will be referred to as data areas DA1 to DA3, respectively. Similarly, the number of program areas in the plurality of areas of the flash memory 4 is 3, which will be referred to as program areas PA1 to PA3, respectively.

  The calculation unit 2 includes a rewrite count management table 5 that is referred to when it itself processes data. FIG. 5 shows the rewrite count management table 5. The rewrite count management table 5 stores the cumulative count for each of the plurality of areas DA1 to DA3 and PA1 to PA3. The cumulative number represents the number of times the initial value is 0 and data is written.

  The calculation unit 2 includes a program area address management table 6 for reference when executing the program. FIG. 6 shows the program area address management table 6. The program area address management table 6 stores the addresses of the program areas PA1 to PA3 and information indicating the length (length) of the program.

  When the cumulative number of times the data has been written reaches the maximum number of rewrites with respect to the first area assigned as the data areas DA1 to DA3 of the flash memory 4, the calculation unit 2 and the program area PA1 A replacement process for replacing the second area assigned as .about.PA3 is executed.

  FIG. 7 is a flowchart showing the operation of the flash memory control device 1 according to the embodiment of the present invention.

  FIG. 9A shows a plurality of areas PA1, PA2, PA3, DA1, DA2, and DA3 of the flash memory 4 before the first replacement process is executed. For example, the addresses of the plurality of areas PA1, PA2, PA3, DA1, DA2, and DA3 are 030000h to 03FFFFh, 040000h to 04FFFFh, 050000h to 05FFFFh, 060000h to 06FFFFh, 070000h to 07FFFFh, and 800000h to 08FFFFh, respectively.

(First replacement process)
The arithmetic unit 2 sequentially writes the latest data to the first area “addresses 800000h to 08FFFFh” assigned as the data area DA3, and erases the data when there is no more writing space in the first area. Secure (step F1).

  The calculation unit 2 adds the number of times of writing at that time to the cumulative number of times of the first area “addresses 080000h to 08FFFFh” stored in the rewrite number management table 5, and uses this number as the cumulative number of times in the first area “address "080000h to 08FFFFh" are updated (step F2).

  The computing unit 2 refers to the rewrite count management table 5 to determine whether or not the cumulative number of the first area “addresses 080000h to 08FFFFh” has reached the maximum rewrite count (step F3). For convenience of explanation, the maximum number of rewrites is 50.

  Here, when the cumulative number does not reach the maximum number of rewrites “50” (step F3-Yes), the calculation unit 2 executes step F1 again.

  On the other hand, when the cumulative number reaches the maximum number of rewrites “50” (step F3-No), the calculation unit 2 can replace the program area PA1 to PA3 with the first area “addresses 800000h to 08FFFFh”. A second region is selected. When the cumulative number of the second area among the program areas PA1 to PA3 represents 0, the second area can be replaced with the first area “addresses 800000h to 08FFFFh”. In this case, since the cumulative number of program areas PA1 to PA3 represents 0, the second area may be any of the program areas PA1 to PA3. The computing unit 2 selects, from the program areas PA1 to PA3, the program area PA3 “addresses 050000h to 05FFFFh” in which the cumulative number represents 0 as the second area (step F4-Yes).

  In this case, the calculating part 2 performs a replacement process (step F5).

  First, the calculation unit 2 erases the data stored in the first area “addresses 800000h to 08FFFFh”.

  Next, the calculation unit 2 stores the program stored in the second area “addresses 050000h to 05FFFFh” in the first area “addresses 800000h to 08FFFFh”. That is, the program stored in the program area PA3 is stored in the data area DA3.

  Next, the calculation unit 2 allocates the first area “addresses 800000h to 08FFFFh” and the second area “addresses 050000h to 05FFFFh” as the program area PA3 and the data area DA3, respectively. That is, the program area PA3 and the data area DA3 are exchanged.

  Next, the arithmetic unit 2 erases the program stored in the second area “addresses 050000h to 05FFFFh”. That is, the program stored in the data area DA3 is erased.

  When executing the replacement process, the arithmetic unit 2 changes the address of the program area PA3 stored in the program area address management table 6 from the address of the second area 050000h to 05FFFFh to the address of the first area 080000h to 08FFFFh (step) F6).

  FIG. 8A shows the program area address management table 6 after the first replacement process is executed.

  FIG. 9B shows a plurality of areas PA1, PA2, DA3, DA1, DA2, and PA3 of the flash memory 4 after the first replacement process is executed (before the second replacement process is executed). The addresses of the plurality of areas PA1, PA2, DA3, DA1, DA2, and PA3 are 030000h to 03FFFFh, 040000h to 04FFFFh, 050000h to 05FFFFh, 060000h to 06FFFFh, 070000h to 07FFFFh, and 800000h to 08FFFFh, respectively.

(Second replacement process)
The arithmetic unit 2 sequentially writes the latest data in the first area “address 060000h to 06FFFFh” assigned as the data area DA1, and erases the data when there is no more writing space in the first area. Secure (step F1).

  The computing unit 2 adds the number of times of writing at that time to the cumulative number of times of the first area “address 060000h to 06FFFFh” stored in the rewrite count management table 5, and uses this number as the cumulative number of times in the first area “address” "060000h to 06FFFFh" are updated (step F2).

  The computing unit 2 refers to the rewrite count management table 5 to determine whether or not the cumulative number of the first area “addresses 060000h to 06FFFFh” has reached the maximum rewrite count “50” (step F3).

  Here, when the cumulative number does not reach the maximum number of rewrites “50” (step F3-Yes), the calculation unit 2 executes step F1 again.

  On the other hand, when the cumulative number exceeds the maximum number of rewrites “50” (step F3-No), the calculation unit 2 can replace the program area PA1 to PA3 with the first area “addresses 060000h to 06FFFFh”. A second region is selected. When the cumulative number of the second area among the program areas PA1 to PA3 represents 0, the second area can be replaced with the first area “addresses 060000h to 06FFFFh”. In this case, since the cumulative number of program areas PA1 and PA2 represents 0, the second area may be any of the program areas PA1 and PA2. The calculation unit 2 selects, from the program areas PA1 to PA3, the program area PA2 “addresses 040000h to 04FFFFh” in which the cumulative number represents 0 as the second area (step F4-Yes).

  In this case, the calculating part 2 performs a replacement process (step F5).

First, the calculation unit 2 erases the data stored in the first area “addresses 060000h to 06FFFFh”.

  Next, the calculation unit 2 stores the program stored in the second area “addresses 040000h to 04FFFFh” in the first area “addresses 060000h to 06FFFFh”. That is, the program stored in the program area PA2 is stored in the data area DA1.

  Next, the arithmetic unit 2 allocates the first area “addresses 060000h to 06FFFFh” and the second area “addresses 400000h to 04FFFFh” as the program area PA2 and the data area DA1, respectively. That is, the program area PA2 and the data area DA1 are exchanged.

  Next, the arithmetic unit 2 erases the program stored in the second area “addresses 040000h to 04FFFFh”. That is, the program stored in the data area DA1 is erased.

  When executing the replacement process, the arithmetic unit 2 changes the address of the program area PA2 stored in the program area address management table 6 from the address of the second area 040000h to 04FFFFh to the address of the first area 060000h to 06FFFFh (step) F6).

  FIG. 8B shows the program area address management table 6 after the second replacement process is executed.

  FIG. 9C shows a plurality of areas PA1, DA1, DA3, PA2, DA2, and PA3 of the flash memory 4 after the second replacement process is executed (before the third replacement process is executed). The addresses of the plurality of areas PA1, DA1, DA3, PA2, DA2, and PA3 are 030000h to 03FFFFh, 040000h to 04FFFFh, 050000h to 05FFFFh, 060000h to 06FFFFh, 070000h to 07FFFFh, and 800000h to 08FFFFh, respectively.

(Third replacement process)
The calculation unit 2 sequentially writes the latest data to the first area “address 070000h to 07FFFFh” assigned as the data area DA2, and erases the data when there is no more writing space in the first area. Secure (step F1).

  The calculation unit 2 adds the number of times of writing at that time to the cumulative number of times of the first area “address 070000h to 07FFFFh” stored in the rewrite count management table 5, and uses this number as the cumulative number of times in the first area “address” 070000h to 07FFFFh "are updated (step F2).

  The computing unit 2 refers to the rewrite count management table 5 to determine whether or not the cumulative count of the first area “addresses 070000h to 07FFFFh” has reached the maximum rewrite count “50” (step F3).

  Here, when the cumulative number does not reach the maximum number of rewrites “50” (step F3-Yes), the calculation unit 2 executes step F1 again.

  On the other hand, when the cumulative number exceeds the maximum number of rewrites “50” (step F3-No), the calculation unit 2 can replace the program area PA1 to PA3 with the first area “address 070000h to 07FFFFh”. A second region is selected. When the cumulative number of the second area among the program areas PA1 to PA3 represents 0, the second area can be replaced with the first area “address 070000h to 07FFFFh”. In this case, since the cumulative number of times for the program area PA1 represents 0, the second area becomes the program area PA1. That is, the computing unit 2 selects, from the program areas PA1 to PA3, the program area PA1 “address 030000h to 03FFFFh” in which the cumulative number represents 0 as the second area (step F4-Yes).

  In this case, the calculating part 2 performs a replacement process (step F5).

  First, the calculation unit 2 erases the data stored in the first area “address 070000h to 07FFFFh”.

  Next, the arithmetic unit 2 stores the program stored in the second area “address 030000h to 03FFFFh” in the first area “address 070000h to 07FFFFh”. That is, the program stored in the program area PA1 is stored in the data area DA2.

  Next, the arithmetic unit 2 allocates the first area “addresses 070000h to 07FFFFh” and the second area “addresses 030000h to 03FFFFh” as the program area PA1 and the data area DA2, respectively. That is, the program area PA1 and the data area DA2 are exchanged.

  Next, the calculation unit 2 erases the program stored in the second area “addresses 030000h to 03FFFFh”. That is, the program stored in the data area DA2 is erased.

  When executing the replacement process, the calculation unit 2 changes the address of the program area PA1 stored in the program area address management table 6 from the address of the second area from 030000h to 03FFFFh to the address of the first area from 070000h to 07FFFFh (step) F6).

  FIG. 8C shows the program area address management table 6 after the third replacement process is executed.

  FIG. 9D shows a plurality of areas DA2, DA1, DA3, PA2, PA1, and PA3 of the flash memory 4 after the third replacement process is executed (before the fourth replacement process is executed). The addresses of the plurality of areas PA1, DA1, DA3, PA2, DA2, and PA3 are “address 030000h to 03FFFFh”, “address 040000h to 04FFFFh”, “address 050000h to 05FFFFh”, “address 060000h to 06FFFFh”, and “address”, respectively. 070000h to 07FFFFh "and" Address 080000h to 08FFFFh ".

  As described above, in the flash memory control device 1 according to the embodiment of the present invention, when the calculation unit 2 repeats steps F1 to F6, all the areas PA1 to PA3 and DA1 to DA3 are used up to the maximum number of rewrites. can do. FIG. 9E shows a plurality of areas DA2, DA1, DA3, PA2, PA1, PA3 of the flash memory 4 used up to the maximum number of rewrites. In this case, the cumulative number of the plurality of areas DA2, DA1, DA3, PA2, PA1, PA3 all represents “50” (step F4-No).

  In the above description, the data areas DA1 to DA3 and the program areas PA1 to PA3 are exemplified as the plurality of areas, and the case where the number of the data areas and the program areas is the same is described. It can be realized even if the number is different.

  For example, as shown in FIG. 10A, it is assumed that a plurality of areas of the flash memory 4 before the first replacement process is performed are areas PA1, PA2, and DA1. In this case, when the first replacement process is performed, as illustrated in FIG. 10B, the calculation unit 2 replaces the program area PA2 and the data area DA1, and when the second replacement process is performed, As shown in FIG. 4, the calculation unit 2 may replace the program area PA1 and the data area DA1.

  Here, the number of data rewrites will be described with reference to FIGS. 11A and 11B.

  FIG. 11A shows that a data area of a plurality of areas is composed of four sectors (sectors S10 to S13), and when one sector is 4 KB, a data area of 16 KB is shown. This is referred to as (A).

For example, when the sector S11 reaches the maximum number of rewrites that is “worst” as the number of data rewrites, the replacement process is executed. If rewriting of sectors S11 to S13 having good characteristics other than the sector S11 is performed 40 times before the rewriting of 50 times that is the maximum number of rewritings of the sector S11 is performed,
Total number of rewrites = 50 times × 1 sector + 40 times × 3 sectors = 170 times (MAX: 50 times × 4 sectors = 200 times)
It is represented by

  FIG. 11B shows that a data area of a plurality of areas is composed of 4 sectors (sectors S20 to S27), and when one sector is 4 KB, a data area of 32 KB is shown. This is referred to as the case (B).

For example, when the sector S22 reaches the maximum number of rewrites that is “worst” as the number of data rewrites, the replacement process is executed. If rewriting of sectors S20, S21, and S23 to S27 having good characteristics other than the sector S22 is performed 40 times before the sector S22 performs 50 rewritings, which is the maximum number of rewritings,
Total number of rewrites = 50 times × 1 sector + 40 times × 7 sectors = 330 times (MAX: 50 times × 8 sectors = 400 times)
It is represented by

  Thus, according to the flash memory control device 1 according to the embodiment of the present invention, it can be seen from (A) and (B) that the number of data rewrites increases as the number of regions increases. .

  Further, the difference in the number of rewrites between the conventional flash memory control device 101 and the flash memory control device 1 according to the embodiment of the present invention will be specifically described.

  When one sector size is 4 KB, all flash memories are 1 MB, the rewrite frequency of one sector is 100 times, and the average rewrite frequency per sector of the replacement area 512 KB is 95 times, the conventional flash memory control device 101 has a total rewrite frequency of In contrast to the 24320 times (256 sectors × 95 times), in the flash memory control device 1 according to the embodiment of the present invention, the total number of rewrites is 25600 times (256 sectors × 100 times).

  Thus, according to the flash memory control device 1 according to the embodiment of the present invention, the number of rewrites can be increased with only one flash memory by increasing the number of data areas and program areas.

  As described above, in the flash memory control device 1 according to the embodiment of the present invention, as a first effect, a single flash memory is subdivided into a plurality of areas including a program area and a data area, and a plurality of areas are divided. Therefore, it is possible to increase the number of times of rewriting with only one flash memory.

  Moreover, in the flash memory control device 1 according to the embodiment of the present invention, as a second effect, it can be said that the flash memory is effectively utilized because the replacement process is executed with only one flash memory.

  Therefore, according to the flash memory control device 1 according to the embodiment of the present invention, the number of data rewrites can be increased and the flash memory can be used effectively.

1 Flash memory controller,
2 arithmetic unit (CPU),
4 Flash memory,
5 Rewrite count management table,
6 Program area address management table,
101 flash memory control device,
102 arithmetic unit (CPU),
103 peripheral equipment,
104 flash memory,
DA1-DA3 data area,
PA1 to PA3 program area

Claims (13)

An arithmetic unit;
A flash memory having a plurality of areas including a program area in which a program executed by the arithmetic unit is stored and data is not rewritten, and a data area in which the data is stored and the data is rewritten Equipped,
The computing unit is
When the cumulative number of times the data has been written reaches the maximum number of rewrites with respect to the first area assigned as the data area, the first area and the second area assigned as the program area A flash memory control device that executes replacement processing for replacement. The computing unit is
When the cumulative number of times the data has been written to the first area reaches the maximum number of rewrites, as the execution of the replacement process,
Erasing the data stored in the first area;
Storing the program stored in the second area allocated as the program area in the first area;
The first and second areas are assigned as the program area and the data area, respectively.
The flash memory control device according to claim 1, wherein the program stored in the second area is erased. For each of the plurality of areas, the initial value is 0, and the accumulated number of times indicating the number of times the data is written is stored, and the rewrite for reference when the arithmetic unit processes the data A frequency management table;
The computing unit is
When the cumulative number of times in the first area has not reached the maximum number of rewrites, the data is written into the first area, and the number of times of writing at that time is added to the cumulative number of times in the first area. Is the cumulative number of times,
The flash memory control device according to claim 2, wherein the replacement process is executed when the cumulative number of times in the first area reaches the maximum number of rewrites. If the cumulative number of the second area of the program area represents 0, the second area can be replaced with the first area,
The computing unit is
When the cumulative number of times the data has been written reaches the maximum number of rewrites with respect to the first area, the second area in which the cumulative number represents 0 is selected from the program area. The flash memory control device according to claim 2, wherein the replacement process is executed. An address of the program area is stored, and further includes a program area address management table for reference when the arithmetic unit executes the program,
5. The address of the program area stored in the program area address management table is changed from the address of the second area to the address of the first area when the replacement process is executed. 6. Flash memory controller. 6. The flash memory control device according to claim 5, wherein the program area address management table further stores information indicating the length of the program in association with the address of the program area. A flash memory control device according to any one of claims 1 to 6,
An electronic device comprising: a peripheral device that acquires the data including characters and images by communication or input. A flash memory having a plurality of areas including a program area in which a program executed by the arithmetic unit is stored and data is not rewritten, and a data area in which the data is stored and the data is rewritten, A method controlled by a calculation unit,
Determining whether the cumulative number of times the data has been written has reached the maximum number of rewrites for the first area allocated as the data area;
When the cumulative number of times the data has been written reaches the maximum number of rewrites, the first area and the second area allocated as the program area are exchanged for the first area. And a flash memory control method. The step of executing the replacement process includes:
Erasing the data stored in the first area;
Storing the program stored in the second area allocated as the program area in the first area;
The first and second areas are assigned as the program area and the data area, respectively.
The flash memory control method according to claim 8, further comprising: erasing the program stored in the second area. When the arithmetic unit processes the data, the rewrite count management table in which the initial value is 0 for each of the plurality of areas and the accumulated count indicating the number of times the data is written is stored. A step of referring to
Writing the data in the first area when the cumulative number of times in the first area has not reached the maximum number of rewrites;
Adding the number of times of writing to the cumulative number of times in the first area, and updating the number of rewrites management table with this number as the cumulative number;
The flash memory control method according to claim 9, further comprising the step of executing the replacement process when the cumulative number of times in the first area reaches the maximum number of rewrites. If the cumulative number of the second area of the program area represents 0, the second area can be replaced with the first area,
When the cumulative number of times the data has been written reaches the maximum number of rewrites with respect to the first area, the second area in which the cumulative number represents 0 is selected from the program area. The flash memory control method according to claim 9, further comprising a step of executing the replacement process. The arithmetic unit is provided with a program area address management table for storing an address of the program area and for reference when the arithmetic unit executes the program,
9. The method of claim 8, further comprising a step of changing the address of the program area stored in the program area address management table from the address of the second area to the address of the first area after the step of executing the replacement process. The flash memory control method according to any one of to 11. 13. The flash memory control method according to claim 12, wherein the program area address management table further stores information indicating the length of the program in association with the address of the program area.

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