JP2011171433A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the technique that makes an insulating resin layer unlikely to peel from a backside of a semiconductor chip in manufacture of a semiconductor device having an external terminal formed using an electrolytic plating method. <P>SOLUTION: The semiconductor chip 7 which has a peeling layer 11 having thickness of 0.1-1 μm formed in a chip mounting region DIA on an upper surface of a mother board 8 by a spraying method or a coating method, and the semiconductor chip 7 also has a cured first resin sheet 3 and an incompletely cured second resin sheet 6 stuck on the backside with the peeling layer 11 interposed is bonded to the chip mounting region DIA on the upper surface of the mother board 8 so that the backside of the semiconductor chip 7 and the upper surface of the mother board 8 face each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and in particular, an external terminal (bonding lead) in which a semiconductor chip is sealed with a resin sealing body and electrically connected to an electrode pad formed on the surface of the semiconductor chip. The present invention relates to a technique effective when applied to a semiconductor device having a package structure in which a lead, an electrode member) is exposed from the lower surface of a resin sealing body.

  For example, Japanese Patent Laid-Open No. 2002-76040 (Patent Document 1) discloses a semiconductor chip, a plurality of electrode members, and a plurality of connection means for electrically connecting a plurality of electrodes and a plurality of electrode members on the surface of the semiconductor chip. And a semiconductor chip, a plurality of electrode members, and a resin sealing body that seals the plurality of connecting means, wherein the back surface of the semiconductor chip and the plurality of electrode members are exposed from the bottom surface of the resin sealing body A semiconductor device is disclosed.

  Japanese Patent Laying-Open No. 2005-294443 (Patent Document 2) discloses that an external terminal manufactured from a lead frame and a semiconductor chip are electrically connected with a wire, sealed with a sealing resin, and back of the semiconductor chip. Disclosed is a semiconductor device in which an insulating resin layer is previously formed by coating or the like, and this insulating resin layer is exposed on the lower surface side of the sealing resin and is present on the same plane as the lower surface of the external terminal Has been.

  In JP 2009-76717 A (Patent Document 3), a structure having a lead electrode and a tab electrode mainly composed of a nickel layer is formed on the upper surface of a stainless steel plate by electroplating. A technique for peeling the structure from a stainless steel plate is disclosed.

JP 2002-76040 A JP 2005-294443 A JP 2009-76717 A

  As electronic devices become smaller and thinner, semiconductor devices (semiconductor packages) mounted on electronic devices are also required to be smaller and thinner.

  In order to reduce the size and thickness of a semiconductor device, for example, as shown in FIG. 3 of Patent Document 1, a structure that eliminates a die pad (tab, chip mounting portion) for supporting a semiconductor chip is effective. Has been.

  However, in the case of such a structure, since the back surface of the semiconductor chip mounted in the semiconductor device is exposed from the sealing body, a load (stress) is applied to the semiconductor chip, and cracks are likely to occur in the semiconductor chip. If the thickness of the semiconductor chip is large, even if a slight load is applied to the semiconductor chip, it will not be a serious problem. However, the semiconductor chip tends to be thin due to the demand for downsizing and thinning of the semiconductor device. It is in. Therefore, in a semiconductor device that is becoming smaller and thinner, there is a risk that reliability of the semiconductor device may be reduced due to a slight load applied to the semiconductor chip. Further, when the back surface of the semiconductor chip is exposed from the sealing body, moisture enters from the interface between the sealing body and the semiconductor chip, and the reliability of the semiconductor device may be reduced due to the moisture.

  Therefore, the inventors of the present application have studied a manufacturing method in which a semiconductor chip is mounted on a mother substrate through an insulating resin layer, as shown in FIG. According to such a manufacturing method, since the insulating resin layer is disposed on the back surface of the semiconductor chip, the back surface of the semiconductor chip can be protected. Moreover, according to such a manufacturing method, since the die pad can be eliminated, it is possible to achieve both elimination of the die pad and protection of the back surface of the semiconductor chip. Therefore, not only can the semiconductor device be reduced in size and thickness, but also a reduction in the reliability of the semiconductor device can be suppressed, so that such a manufacturing method was considered effective.

  However, the inventors of the present application consider that it is necessary to reduce the thickness of the lead serving as the external terminal in order to realize further miniaturization of the semiconductor device, and use the electrolytic plating method as in Patent Document 3 described above. The external terminals formed were investigated. As a result, by using the electrolytic plating method, the external terminal has a thickness of about half or less of the thickness of the lead formed of a part of the lead frame formed by patterning the conductive substrate as in Patent Document 2. It was found that it can be formed.

  However, when forming an external terminal using the electrolytic plating method, a base material made of metal must be used as a mother substrate. As a result, when the mother substrate is peeled from the sealing body, a new problem has occurred that the insulating resin layer disposed between the back surface of the semiconductor chip and the mother substrate is peeled off from the back surface of the semiconductor chip. . This is because the adhesion force between the base substrate made of metal and the insulating resin layer is superior to the adhesion force between the semiconductor chip made of silicon and the insulating resin layer.

  Therefore, in the present invention, in order to reduce the size and thickness of the semiconductor device, the external terminals are formed by using an electroplating method using a base material made of metal as a base substrate, but the insulating resin layer is formed from the base substrate. Disclosed is a technique capable of making an insulating resin layer difficult to peel from the back surface of a semiconductor chip by facilitating the peeling.

  An object of the present invention is to provide a technique capable of preventing an insulating resin layer from being peeled off from the back surface of a semiconductor chip in the manufacture of a semiconductor device having an external terminal formed by using an electrolytic plating method.

  Another object of the present invention is to provide a technique capable of reducing the size and thickness of a semiconductor device while suppressing a decrease in reliability of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  This embodiment is a method of manufacturing a semiconductor device including the following steps. (A) having a first main surface, a plurality of chip regions formed on the first main surface, a scribe region formed between the plurality of chip regions, and a second main surface opposite to the first main surface A step of preparing a semiconductor wafer, (b) a step of attaching a first resin sheet to the second main surface of the semiconductor wafer, (c) an upper surface, a chip mounting region provided on the upper surface, and an electrolytic plating method around the chip mounting region A step of preparing a mother substrate having a plurality of external terminals formed by using a conductive member and a lower surface opposite to the upper surface, and (d) providing a release layer on a chip mounting region of the mother substrate A step of forming, (e) a step of mounting the semiconductor chip obtained by dividing the semiconductor wafer on the chip mounting region of the mother substrate via the first resin sheet and the release layer, and (f) forming on the surface of the semiconductor chip With multiple electrode pads (G) a part of each of the plurality of external terminals, the upper surface of the mother board, the semiconductor chip, and the plurality of conductive members (H) The process of removing a mother board | substrate and exposing each other part of a peeling layer and a some external terminal from a sealing body.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  In the manufacture of a semiconductor device having an external terminal formed using an electrolytic plating method, the insulating resin layer can be made difficult to peel from the back surface of the semiconductor chip. In addition, the semiconductor device can be reduced in size and thickness by suppressing a decrease in reliability of the semiconductor device.

It is principal part sectional drawing in the manufacturing process explaining the manufacturing method of the semiconductor device by Embodiment 1 of this invention. FIG. 2 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 1; FIG. 3 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 2; FIG. 4 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 3; FIG. 5 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 5; FIG. 7 is a plan view of essential parts of the semiconductor device in the manufacturing process of the semiconductor device, following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device along the line AA ′ shown in FIG. 7. FIG. 9 is a plan view of essential parts of the semiconductor device in the manufacturing process of the semiconductor device, following FIGS. 7 and 8; FIG. 10 is a main part cross-sectional view of the semiconductor device along the line BB ′ shown in FIG. 9; FIG. 11 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIGS. 9 and 10; FIG. 12 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 11; FIG. 13 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 12; FIG. 14 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 13; FIG. 15 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 14; FIG. 16 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 15; FIG. 17 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 16; FIG. 18 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 17; FIG. 19 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 20; FIG. 22 is a principal part cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device, following FIG. 21; It is process drawing explaining the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is principal part sectional drawing explaining the state which mounted the semiconductor chip by Embodiment 2 of this invention in the chip mounting area | region of the motherboard. It is a principal part top view which shows the 1st example of the motherboard which mounts the semiconductor chip by Embodiment 2 of this invention. It is a principal part top view which shows the 2nd example of the motherboard which mounts the semiconductor chip by Embodiment 2 of this invention. It is a principal part top view which watermarked the sealing body of the semiconductor device by Embodiment 1 of this invention. 1 is a plan view of a main part on the back surface (mounting surface) side of a semiconductor device according to a first embodiment of the present invention; FIG. 28 is a fragmentary cross-sectional view of the semiconductor device along the line CC ′ shown in FIG. 27;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
≪About semiconductor devices≫
The semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 27 is a plan view of relevant parts through the sealing body of the semiconductor device, FIG. 28 is a plan view of relevant parts on the back surface (mounting surface) side of the semiconductor device, and FIG. 29 is taken along the line CC ′ shown in FIG. It is principal part sectional drawing of a semiconductor device.

  The semiconductor device 17 includes a semiconductor chip 7, resin sheets (first resin sheet 3 and second resin sheet 6) formed on the back surface of the semiconductor chip 7, a plurality of external terminals 9 provided around the semiconductor chip 7, and It is composed of a plurality of conductive members 13 that electrically connect a plurality of electrode pads 2 and a plurality of external terminals 9 arranged on the surface of the semiconductor chip 7. Further, the semiconductor chip 7, the resin sheets (the first resin sheet 3 and the second resin sheet 6), a part of each of the plurality of external terminals 9 (upper surface and side surface), and the plurality of conductive members 13 are resin-sealed bodies. 14 is sealed. However, the back surface of the semiconductor chip 7 is not exposed from the lower surface of the resin sealing body 14, and is formed on the back surface of the semiconductor chip 7 via resin sheets (the first resin sheet 3 and the second resin sheet 6). The other part (lower surface, mounting surface) of each of the release layer 11 and the plurality of external terminals 9 is exposed.

As described above, the die pad is not disposed on the back surface of the semiconductor chip 7, the resin sheet is disposed, and the plurality of external terminals 9 formed by the electrolytic plating method are used, thereby reducing the size and thickness of the semiconductor device. Can be realized. Moreover, since the back surface of the semiconductor chip 7 is protected by the resin sheet and the intrusion of moisture into the semiconductor chip 7 can be suppressed, a decrease in the reliability of the semiconductor device can also be suppressed. In the first embodiment, the use of a plurality (two) of resin sheets has been described. However, the thickness is sufficient to prevent moisture from entering, and further, the mother substrate 8 described in a later manufacturing method is used. If there is no problem with the adhesive strength, one resin sheet may be used.
≪About manufacturing method of semiconductor device≫
Next, the manufacturing method of the semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS. 1 to 6, 8, and 10 to 22 are main-portion cross-sectional views of the semiconductor device during the manufacturing process for explaining the semiconductor device manufacturing method, and FIGS. The principal part top view of the semiconductor device in a manufacturing process, FIG. 23 is process drawing explaining the manufacturing method of a semiconductor device.

  First, as shown in FIG. 1 (wafer preparation step P1), a semiconductor wafer 1 is prepared. The semiconductor wafer 1 is made of single crystal silicon, and has a diameter of, for example, 200 mm or 300 mm, and a thickness (first thickness) of, for example, 0.7 mm or more (a value at the time of entering the manufacturing process). The semiconductor wafer 1 includes a first main surface (front surface) 1x, a plurality of chip regions 1CA partitioned and formed in a matrix on the first main surface 1x, and a scribe region (dicing line) formed between the plurality of chip regions 1CA. 1SA and a second main surface (back surface) 1y opposite to the first main surface 1x.

  Although not limited to this, each chip region 1CA of the first main surface 1x of the semiconductor wafer 1 includes a multilayer wiring layer in which a plurality of semiconductor elements, a plurality of insulating layers and wiring layers are stacked, and the multilayer wiring layer. An integrated circuit composed of a surface protective film formed so as to cover the surface is formed. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film such as aluminum, tungsten, or copper. The surface protective film is formed of a multilayer film in which an inorganic insulating film such as a silicon oxide film or a silicon nitride film and an organic insulating film are stacked. In each chip region 1CA of the first main surface 1x of the semiconductor wafer 1, a plurality of electrode pads (bonding pads) 2 electrically connected to the plurality of semiconductor elements extend along each side of each chip region 1CA. (A part of the plurality of electrode pads 2 is shown in FIG. 1). The plurality of electrode pads 2 are composed of the uppermost wiring of the multilayer wiring layer, and are exposed through openings formed in the surface protective film corresponding to the respective electrode pads 2.

  Next, the thickness of the semiconductor wafer 1 is reduced to a predetermined thickness by roughly grinding the second main surface 1y of the semiconductor wafer 1 using an abrasive (for example, roughness # 360). Subsequently, the second principal surface 1y of the semiconductor wafer 1 is subjected to rough grinding by finish grinding using a grinding material (for example, roughness # 1500 or # 2000) having finer mesh than the previously used grinding material. The distortion of the second main surface 1y of the semiconductor wafer 1 that is sometimes generated is removed (back grinding). Further, the polishing streaks on the second main surface 1y of the semiconductor wafer 1 generated during finish grinding are removed by, for example, a spin etching method, a CMP (Chemical Mechanical Polishing) method, or the like (stress relief). The thickness (second thickness) of the semiconductor wafer 1 at the time when the back grinding and the stress relief are finished is, for example, 0.13 mm. The stress relief does not have to be performed on all the semiconductor wafers 1, but is performed according to the strength required for the semiconductor chip.

Next, as shown in FIG. 2 (first resin sheet bonding step P2), the second main surface 1y of the semiconductor wafer 1 and the upper surface of the first resin sheet (sealing sheet) 3 are opposed to each other to generate heat (for example, The first resin sheet 3 is attached to the second main surface 1y of the semiconductor wafer 1 by applying a pressure of 80 to 120 ° C.). The first resin sheet 3 is, for example, a thermosetting type, and is made of an epoxy resin containing a filler (SiO ₂ particles). The thickness is, for example, 20 μm. The first resin sheet 3 contains a relatively large amount (first amount) of filler in order to increase hardness and heat resistance. This is because in the completed semiconductor device, the back surface of the semiconductor chip is reliably protected by the first resin sheet 3.

  Next, as shown in FIG. 3 (first resin sheet curing step P3), the semiconductor wafer 1 to which the first resin sheet 3 is attached is heat-treated at a temperature of 150 to 170 ° C. for about 1 hour, for example. By applying, the 1st resin sheet 3 is hardened. Thereby, the first resin sheet 3 is hardly peeled off from the second main surface (back surface) 1y of the semiconductor wafer 1, and the hardness and heat resistance of the first resin sheet 3 are increased.

Next, as shown in FIG. 4 (second resin sheet and dicing tape bonding step P4), the dicing tape 4 is prepared. Although not shown, an annular frame is attached to the peripheral portion of the dicing tape 4 in plan view. The dicing tape 4 uses, for example, polyolefin as a base material, and the thickness thereof is, for example, 90 μm. On the upper surface of the dicing tape 4, a second resin sheet 6 made of a material different from that of the first resin sheet 3 is attached via an adhesive layer 5. The adhesive layer 5 is, for example, an acrylic UV curable pressure-sensitive adhesive, and has an adhesive force of, for example, 200 g / 25 mm before UV irradiation and 10 to 20 g / 25 mm after UV irradiation. The second resin sheet 6 is, for example, a thermosetting type, and is made of an epoxy resin containing a filler (SiO ₂ particles). The thickness is, for example, 20 μm. The second resin sheet 6 contains a relatively small amount (second amount) of filler, and the amount of filler contained in the second resin sheet 6 is greater than the amount of filler contained in the first resin sheet 3. There are few.

  Hereinafter, the reason for forming the second resin sheet 6 between the semiconductor wafer 1 and the dicing tape 4 and the amount of filler contained in the second resin sheet 6 are more than the amount of filler contained in the first resin sheet 3. The reason for reducing it will be explained.

  In the manufacturing process after mounting the semiconductor chip picked up from the dicing tape 4 on the upper surface of the mother substrate, before picking up the semiconductor chip, ultraviolet (Ultra Violet: UV) To reduce the adhesive strength of the adhesive layer 5 (UV irradiation step P6). At this time, since the dicing tape 4 used in the first embodiment is made of a material that can transmit ultraviolet rays, the dicing tape 4 can transmit ultraviolet rays. Thereafter, the semiconductor chip is picked up and mounted on the upper surface of the mother substrate (die bonding step P9).

  When the second resin sheet 6 is not formed, the semiconductor chip is mounted on the upper surface of the mother board through only the first resin sheet 3 (the adhesive layer 5 having reduced adhesive strength is attached to a part thereof). . However, even if heat treatment for bonding the semiconductor chip to the upper surface of the mother substrate is performed, the first resin sheet 3 is already cured, so that the bonding between the semiconductor chip and the mother substrate is weak and difficult to fix.

  On the other hand, when the second resin sheet 6 is formed, the mother resin is provided via the first resin sheet 3 and the second resin sheet 6 (the adhesive layer 5 having reduced adhesive strength is attached to a part thereof). A semiconductor chip is mounted on the upper surface of the substrate. At this stage, since the second resin sheet 6 has not been completely cured yet, when the heat treatment for bonding the semiconductor chip to the upper surface of the mother substrate is performed thereafter, the second resin sheet 6 is cured, and the semiconductor Bonding between the chip and the mother substrate is strengthened. As a result, the semiconductor chip can be reliably fixed to the upper surface of the mother substrate.

  Before picking up the semiconductor chip, ultraviolet rays are irradiated to reduce the adhesive strength of the adhesive layer 5. However, since the amount of filler contained in the second resin sheet 6 is relatively small, the second due to this UV irradiation. The resin sheet 6 is slightly cured. Therefore, even if the UV irradiation is performed, the second resin sheet 6 is soft, and the hardness of the second resin sheet 6 is kept lower than the hardness of the first resin sheet 3.

  Next, the upper surface of the dicing tape 4 and the second main surface 1 y of the semiconductor wafer 1 are opposed to each other, and both are attached via the first resin sheet 3, the second resin sheet 6, and the adhesive layer 5. Thereby, the semiconductor wafer 1 is fixed to the upper surface of the dicing tape 4 via the first resin sheet 3, the second resin sheet 6, and the adhesive layer 5.

  Here, the 2nd resin sheet 6 is affixed beforehand on the upper surface of the dicing tape 4 via the adhesive layer 5, the 1st resin sheet 3 and the 2nd resin sheet 6 are made to oppose, and the 1st resin sheet 3 Although the method for adhering the affixed semiconductor wafer 1 and the dicing tape 4 to which the second resin sheet 6 is affixed via the adhesive layer 5 has been described, the present invention is not limited to this. For example, the second resin sheet 6 is attached in advance to the first resin sheet 3 attached to the second surface 1y of the semiconductor wafer 1, and the second resin sheet 6 and the adhesive layer 5 are opposed to each other, so that the first resin sheet 6 The semiconductor wafer 1 to which the 3 and second resin sheets 6 are attached may be bonded to the dicing tape 4 on which the adhesive layer 5 is formed.

  Next, as shown in FIG. 5 (dicing step P5), the semiconductor wafer 1 is cut vertically and horizontally along the scribe region 1SA using, for example, an extremely thin circular blade with diamond fine particles attached thereto. At the same time, the first resin sheet 3, the second resin sheet 6, and the adhesive layer 5 are also cut vertically and horizontally along the scribe region 1 SA of the semiconductor wafer 1. Although the semiconductor wafer 1 is separated into semiconductor chips 7, the semiconductor chips 7 are fixed to the frame via the dicing tape 4 even after being separated into individual pieces, so that the aligned state is maintained.

  Next, as shown in FIG. 6 (UV irradiation process P6), by irradiating ultraviolet rays from the lower surface side of the dicing tape 4 and reducing the adhesive force of the adhesive layer 5 to, for example, about 10 to 20 g / 25 mm, The adhesive layer 5 is cured. Thereby, each semiconductor chip 7 is easily peeled off from the dicing tape 4.

  Next, as shown in FIGS. 7 and 8 (mother substrate preparation step P7), a mother substrate (base material, frame) 8 is prepared. The mother board 8 is made of a conductive member such as stainless steel (SUS403) or copper, for example, and is a multi-piece board in which areas (chip mounting areas DIA) on which one semiconductor chip 7 is mounted are partitioned and formed in a matrix. . FIG. 7 illustrates a mother board 8 in which three blocks each including a plurality of chip mounting areas DIA are formed. The thickness of the mother board 8 is, for example, 150 μm.

  A plurality of external terminals (electrodes) 9 are formed around the chip mounting area DIA on the upper surface of the mother board 8. The external terminal 9 is composed of a laminated film in which a gold film, a nickel film, and a gold film or a silver film are sequentially formed from the bottom by, for example, an electrolytic plating method, and has a mushroom shape in which the nickel film projects in an eaves shape. The upper surface of the external terminal 9 is higher than the chip mounting area DIA on the upper surface of the mother substrate 8, but the external terminal 9 formed by electrolytic plating is formed by patterning a conductive substrate (metal plate). It can be formed with a thickness less than about half of the thickness of the lead consisting of a part of the lead frame. Moreover, the anchor effect of the external terminal 9 can be expected in the molding process P12, which is a subsequent manufacturing process, by making the external terminal 9 into a mushroom shape. The thickness of the gold film constituting the external terminal 9 is, for example, 1 μm, the thickness of the nickel film is, for example, 30 to 60 μm, and the thickness of the gold film or the silver film is, for example, 3 μm or less.

  Next, as shown in FIGS. 9 and 10 (peeling layer forming step P8), the upper surface of the mother substrate 8 is formed with a mask 10 having an opening 10a in which only the chip mounting area DIA on which the semiconductor chip 7 is mounted is exposed. Place on the side. All the external terminals 9 are covered with a mask 10. Subsequently, the release layer 11 is formed only on the chip mounting area DIA on the upper surface of the mother substrate 8 through the mask 10. The release layer 11 is made of, for example, arranged fluorine molecules, and is formed, for example, by disposing (applying) a release agent 11a obtained by thinning fluorine with volatile chlorofluorocarbon in the chip mounting area DIA. Moreover, the thickness of the peeling layer 11 is 0.1-1 micrometer, for example, and is thinner than the thickness of the 1st resin sheet 3 or the 2nd resin sheet 6. FIG. This is to prevent a significant step from occurring in the completed semiconductor device.

  Here, since the release agent 11a having a reduced concentration is used, even if the release agent 11a is simply applied to the chip mounting area DIA, the resin is applied from the back surface of the semiconductor chip 7 in the process of peeling the mother substrate 8 later. The mother board 8 can be peeled off without peeling off the sheet. However, as shown in FIG. 10, the peelability of the mother substrate 8 can be further improved by spraying the thinned release agent 11a onto the chip mounting area DIA to form the release layer 11 by, for example, a spray method. .

  Next, as shown in FIG. 11 (die bonding step P9), the semiconductor chip 7 is peeled off from the dicing tape 4 and picked up. Since the adhesive force of the adhesive layer 5 is weakened in the UV irradiation process P6 which is the previous manufacturing process, even the semiconductor chip 7 which is thin and has a reduced strength can be reliably picked up. The first resin sheet 3 and the second resin sheet 6 are bonded to the back surface (second surface) of the semiconductor chip 7.

  The picked up semiconductor chip 7 is transported to a predetermined chip mounting area DIA on the upper surface of the mother board 8. Subsequently, the second resin sheet 6 bonded to the back surface of the semiconductor chip 7 and the chip mounting area DIA on the upper surface of the mother substrate 8 are opposed to each other through the release layer 11, and heat (for example, 80 to 120 ° C.) By applying pressure, the semiconductor chip 7 is attached to the chip mounting area DIA on the upper surface of the mother substrate 8. The first resin sheet 3, the second resin sheet 6, and the release layer 11 are interposed between the semiconductor chip 7 and the mother substrate 8.

  Next, as shown in FIG. 12 (baking process P10), the mother substrate 8 to which the plurality of semiconductor chips 7 are attached is subjected to a heat treatment at a temperature of 150 to 170 ° C. for about 1 hour, for example. The second resin sheet 6 is cured. The temperature for curing the second resin sheet 6 is a temperature lower than the heat resistant temperature of the release layer 11. Thereby, the hardness and heat resistance of the second resin sheet 6 are increased.

  As described above, when the second resin sheet 6 is not formed, the semiconductor chip 7 is mounted on the upper surface of the mother substrate 8 only through the cured first resin sheet 3. And the mother substrate 8 are weakly bonded and difficult to fix.

  However, the second resin sheet 6 that is not completely cured is provided between the semiconductor chip 7 and the mother substrate 8 and cured by the heat treatment, so that the semiconductor chip 7 and the mother substrate via the second resin sheet 6 are cured. Adhesion with 8 becomes stronger. Thereby, the semiconductor chip 7 can be reliably fixed to the upper surface of the mother substrate 8.

  Next, as shown in FIG. 13 (wire bonding step P11), a plurality of electrode pads 2 arranged on the edge of the surface (first main surface) of the semiconductor chip 7 and a chip mounting area DIA on the upper surface of the mother substrate 8 A plurality of external terminals 9 formed in the periphery of the substrate are electrically connected to each other using a plurality of conductive members 13 by, for example, a nail head bonding method (ball bonding method) using ultrasonic vibration in combination with thermocompression bonding. . For the conductive member 13, for example, a gold wire is used. In addition, a normal bonding method (a method in which the electrode pad 2 of the semiconductor chip 7 and a part of the wire are connected and then the external terminal 9 and the other part of the wire are connected) is used, but a reverse bonding method (the external terminal 9 and A method of connecting the electrode pad 2 of the semiconductor chip 7 and the other part of the wire after connecting a part of the wire may be used. At the time of bonding, heat of about 170 ° C. is also applied to the release layer 11, but since the heat resistant temperature of the release layer 11 is about 180 ° C., the release layer 11 does not deteriorate. FIG. 13 shows a part of the plurality of conductive members 13.

  Next, as shown in FIG. 14 (molding step P12), the mother substrate 8 on which a plurality of semiconductor chips 7 are mounted is set in a mold molding machine, and the sealing resin liquefied by increasing the temperature is molded. The upper surface side of the mother substrate 8 is sealed with a sealing resin to form one resin sealing body (sealing body) 14. Subsequently, heat treatment is performed at a temperature of 170 ° C., for example. Accordingly, the upper surface of the mother substrate 8, the plurality of semiconductor chips 7, a part of each of the plurality of external terminals 9 (upper surface and side surfaces), the plurality of conductive members 13, and the like cover the upper surface side of the mother substrate 8. Sealed by the sealing body 14. The thickness of the resin sealing body 14 is, for example, 300 μm. For the purpose of reducing the stress, the resin sealing body 14 is made of an epoxy thermosetting insulating resin to which, for example, a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added.

  Next, as shown in FIG. 15 (mother substrate removal step P13), the mother substrate 8 is peeled off from the resin sealing body. As a result, a part of the release layer 11 and the other part (lower surface, mounting surface) of each of the plurality of external terminals 9 are exposed from the lower surface of the resin sealing body 14.

  The first resin sheet 3, the second resin sheet 6, and the release layer 11 were formed between the semiconductor chip 7 and the mother board 8, but by peeling the mother board 8, as shown in FIG. The release layer 11 is physically separated into two. That is, one of the release layers 11 remains on the lower surface of the second resin sheet 6 attached to the back surface of the semiconductor chip 7, and the other one of the release layers 11 remains on the upper surface of the mother substrate 8. Therefore, even after the mother substrate 8 is peeled off, the first resin sheet 3 and the second resin sheet 6 are adhered to the back surface of the semiconductor chip 7. Since the release layer 11 is separated into two, the region where the release layer 11 on the back surface of the semiconductor chip 7 remains is recessed from the lower surface of the resin sealing body 14. However, the thickness of the release layer 11 is, for example, 0.1 to 1 μm as described above. Furthermore, since only about half of them are removed, the above-mentioned depression is about 0.5 μm or less, and there is no significant step in the completed semiconductor device.

  Further, the release layer 11 remaining on the second resin sheet 6 may not remain on the entire lower surface of the second resin sheet 2. In this case, a part of the lower surface of the second resin sheet 6 is exposed from the resin sealing body 14 and the release layer 11.

  Next, as shown in FIG. 17 (mark process P14), a product name or the like is stamped on the upper surface of the resin sealing body 14.

  Next, as shown in FIG. 18 (package dicing sheet bonding step P15), the dicing sheet 15 is prepared. An adhesive layer 16 is attached to the upper surface of the dicing sheet 15. The adhesive layer 16 is, for example, an acrylic UV curable adhesive. Subsequently, a resin seal in which the upper surface of the dicing sheet 15 is covered with the plurality of semiconductor chips 7, a part of each of the plurality of external terminals 9 (upper surface and side surfaces), and the plurality of conductive members 13 via the adhesive layer 16. The stationary body 14 is fixed.

  Next, as shown in FIG. 19 (package dicing step P16), the resin sealing body 14 is moved from the upper surface side of the resin sealing body 14 to the scribe region by using, for example, an ultrathin circular blade with diamond fine particles attached thereto. Cut vertically and horizontally along. At the same time, the adhesive layer 16 is also cut vertically and horizontally along the scribe region of the resin sealing body 14. The resin sealing body 14 is separated into individual semiconductor devices (semiconductor packages) 17, but the semiconductor device 17 is fixed via the dicing sheet 15 even after being separated into individual pieces, so that the aligned state is maintained. ing.

  Next, as shown in FIG. 20 (package cleaning step P <b> 17), the semiconductor device 17 is cleaned to remove debris and the like generated when the resin sealing body 14 and the adhesive layer 16 are cut.

  Next, as shown in FIG. 21 (UV irradiation process P18), ultraviolet rays are irradiated from the lower surface side of the dicing sheet 15 to reduce the adhesive force of the adhesive layer 16. Thereby, each semiconductor device 17 becomes easy to peel from the dicing sheet 15. Here, since the dicing sheet 15 used in the first embodiment is made of a material that can transmit ultraviolet rays, the dicing sheet 15 can transmit ultraviolet rays.

  Next, as shown in FIG. 22 (package dicing sheet removal step P19), the dicing sheet 15 is removed to divide into individual semiconductor devices 17. On the lower surface of the resin sealing body 14 of the semiconductor device 17, the lower surfaces (mounting surfaces) of the plurality of external terminals 9, and the first resin sheet 3 and the second resin sheet 6 on the back surfaces of the plurality of semiconductor chips 7, respectively. A part of the release layer 11 formed through the film is exposed. Therefore, the back surfaces of the plurality of semiconductor chips 7 are protected by the first resin sheet 3 and the second resin sheet 6. After that, the product is sorted according to the product standard, and the product is completed through a final appearance inspection.

  As described above, according to the first embodiment, in order to reduce the size and thickness of the semiconductor device 17, the external terminals 9 are formed by an electrolytic plating method using a conductive member such as stainless steel or copper as the base substrate 8. However, when the mother board 8 is peeled from the resin sealing body 14, the peeling layer 11 formed in the chip mounting area DIA on the upper surface of the mother board 8 is separated and the mother board 8 is peeled off. The release layer 11 is formed between the insulating resin layers (the first resin sheet 3 and the second resin sheet 6) formed on the back surface of the semiconductor chip 7 and the chip mounting area DIA on the upper surface of the mother substrate 8. Therefore, even if the mother substrate 8 is peeled from the resin sealing body 14, the insulating resin layers (the first resin sheet 3 and the second resin sheet 6) are not peeled off from the back surface of the semiconductor chip 7, and the back surface of the semiconductor chip 7. Can be protected.

  Further, since the back surface of the semiconductor chip 7 is protected by the insulating resin layers (the first resin sheet 3 and the second resin sheet 6), the moisture absorption resistance of the semiconductor device 17 is also improved.

  In addition, a second resin sheet 6 that is not completely cured is attached to the back surface of the semiconductor chip 7 when peeled off from the dicing tape 4 so as to overlap the cured first resin sheet 3. Therefore, when the semiconductor chip 7 is fixed to the chip mounting area DIA on the upper surface of the mother substrate 8, the second resin sheet 6 attached to the back surface of the semiconductor chip 7 is cured by heat treatment, so that the second resin sheet 6 is interposed. The adhesion between the semiconductor chip 7 and the mother substrate 8 can be strengthened. Thereby, the semiconductor chip 7 can be reliably fixed to the upper surface of the mother substrate 8.

(Embodiment 2)
In the first embodiment described above, when the mother board 8 is peeled from the resin sealing body 14, the peeling layer 11 formed in the chip mounting area DIA on the upper surface of the mother board 8 is separated and the mother board 8 is peeled off. This prevented the insulating resin layers (the first resin sheet 3 and the second resin sheet 6) formed on the back surface of the semiconductor chip 7 from peeling off. However, in the second embodiment, without using the release layer 11, as shown in FIG. 24, a recess (a groove that does not penetrate the mother substrate 8) 8a is formed in a part of the chip mounting area DIA of the mother substrate 8. By reducing the contact area between the insulating resin layers (first resin sheet 3 and second resin sheet 6) formed on the back surface of the semiconductor chip 7 and the upper surface of the mother substrate 8, the insulating resin layer (first resin) The mother substrate 8 is peeled from the resin sealing body 14 without peeling off the sheet 3 and the second resin sheet 6). In FIG. 24 described above, the recess 8a that is a groove that does not penetrate the mother substrate 8 is formed in the chip mounting area DIA of the mother substrate 8. However, a hole (through hole) that penetrates the mother substrate 8 may be formed. .

  A method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 25 is a plan view of a principal part in which the mother substrate and the semiconductor chip of the first example are overlapped during the manufacturing process for explaining the semiconductor device manufacturing method, and FIG. 26 is a second plan view during the manufacturing process for explaining the semiconductor device manufacturing method. It is the principal part top view which piled up the mother board of the example, and the semiconductor chip.

  FIG. 25 shows one chip mounting area of the mother board 20 of the first example. Here, a 4-pin specification semiconductor device is illustrated, and electrode pads (bonding pads) 22 are arranged at the four corners of the surface (first main surface) of the semiconductor chip 21 mounted on the semiconductor device. . The size of the semiconductor chip 21 is, for example, 0.5 mm × 0.5 mm, and the size of the electrode pad 22 is, for example, 0.06 mm × 0.06 mm.

  A circular hole (through hole) 23 is formed in the chip mounting region of the mother board 20. By forming the holes 23 in the chip mounting region of the mother board 20, the insulating resin layers (the first resin sheet 3 and the second resin sheet) can be formed without forming the release layer 11 described in the first embodiment. The mother substrate 20 can be peeled from the resin sealing body 14 without removing 6).

  Considering the ease with which the mother board 20 can be peeled off, it is considered that 50% of the bonding surface is necessary for the area where the mother board 20 and the semiconductor chip 21 do not contact each other. However, when the hole 23 is formed in the mother substrate 20 directly below the electrode pad 22 of the semiconductor chip 21, in the bonding wire process, for example, when a bonding method using ultrasonic vibration in combination with thermocompression bonding is used, ultrasonic waves are transmitted. It becomes difficult to connect a good conductive member. Therefore, the hole 23 is formed in a region that does not overlap the electrode pad 22 of the semiconductor chip 21 when viewed in plan. In other words, the semiconductor chip 21 is mounted on the chip mounting area DIA of the mother board 8 so that the plurality of electrode pads 22 of the semiconductor chip 21 do not overlap the recess 8a in plan view. From these, it is preferable that the diameter of the hole 23 formed in the mother substrate 20 is 0.4 mm (the ratio of the bonding surface is about 50%).

  However, if the diameter of the hole 23 formed in the mother board 20 is 0.4 mm, the margin between the hole 23 and the electrode pad 22 formed on the surface of the semiconductor chip 21 is 0.027 mm. When the die bonding accuracy of the conductive member connected to the electrode pad 22 is ± 0.05 mm, the possibility that the hole 23 and the electrode pad 22 interfere with each other increases.

  Therefore, as will be described next, in order to avoid interference between the hole 23 and the electrode pad 22, the shape of the hole 23 is a cross shape.

  FIG. 26 shows one chip mounting area of the mother board 24 of the second example. Here, similarly to the mother board 20 of the first example described above, a 4-pin specification semiconductor device is illustrated, and the four corners of the surface (first main surface) of the semiconductor chip 25 mounted on the semiconductor device are illustrated. Electrode pads (bonding pads) 26 are disposed. The size of the semiconductor chip 25 is, for example, 0.5 mm × 0.5 mm, and the size of the electrode pad 26 is, for example, 0.06 mm × 0.06 mm.

  Even if the width of the cross-shaped hole (through hole) 27 is set to, for example, 0.21 mm so that the ratio of the bonding surface is about 50%, the hole 27 and the electrode pad 26 formed on the surface of the semiconductor chip 25 The margin is 0.055 mm. Therefore, even when the die bonding accuracy of the conductive member connected to the electrode pad 26 is ± 0.05 mm, interference between the hole 27 and the electrode pad 26 can be avoided.

  In the mother substrate 20 of the first example and the mother substrate 24 of the second example, holes 23 and 27 that penetrate the mother substrates 20 and 24 are formed in the chip mounting region, but grooves that do not penetrate the mother substrates 20 and 24 ( The concave portion 8a) shown in FIG. 24 may be formed. When the holes 23 and 27 penetrating the mother substrates 20 and 24 are formed, there is a risk that the sealing resin leaks to the lower surface side of the mother substrates 20 and 24 when the semiconductor chips 21 and 25 and the like are sealed with the resin sealing body. There is. However, if the groove does not penetrate the mother substrates 20 and 24, such sealing resin leakage does not occur.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments described above, the use of two resin sheets (the first resin sheet 3 and the second resin sheet 6) has been described, but the resin sheet adhered to the back surface of the semiconductor chip 7 is Only one is good. However, as described above, considering the problem of adhesive strength when the semiconductor chip 7 is mounted on the mother substrate 8 and the reliability of the semiconductor device, a plurality of resins are used as in the first and second embodiments. It is preferable to use a sheet. Moreover, since the use of a large number of sheets may cause an increase in the thickness of the semiconductor device, the number of resin sheets to be used is preferably two as described above.

  The present invention can be applied to the manufacture of a semiconductor device in which a semiconductor chip is sealed with a sealing resin.

1 Semiconductor wafer 1x First main surface (surface)
1y 2nd main surface (back surface)
1CA chip area 1SA scribe area (dicing line)
2 Electrode pads (bonding pads)
3 First resin sheet (sealing sheet)
4 Dicing tape 5 Adhesive layer 6 Second resin sheet 7 Semiconductor chip 8 Mother board (base material, frame)
8a Recess 9 External terminal (electrode)
DESCRIPTION OF SYMBOLS 10 Mask 10a Opening part 11 Release layer 11a Release agent 13 Conductive member 14 Resin sealing body (sealing body)
15 Dicing Sheet 16 Adhesive Layer 17 Semiconductor Device (Semiconductor Package)
20 Mother board 21 Semiconductor chip 22 Electrode pad (bonding pad)
23 holes (through holes)
24 Mother board 25 Semiconductor chip 26 Electrode pad (bonding pad)
27 holes (through holes)
DIA chip mounting area

Claims (18)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a first main surface, a plurality of chip regions formed on the first main surface, a scribe region formed between the plurality of chip regions, and a second main opposite to the first main surface Preparing a semiconductor wafer having a surface;
(B) a step of attaching a first resin sheet to the second main surface of the semiconductor wafer;
(C) having an upper surface, a chip mounting region provided on the upper surface, a plurality of external terminals formed by electrolytic plating around the chip mounting region, and a lower surface opposite to the upper surface; Preparing a mother substrate made of a conductive member;
(D) forming a release layer in the chip mounting region of the mother substrate;
(E) a step of mounting a semiconductor chip obtained by dividing the semiconductor wafer on the chip mounting region of the mother substrate through the first resin sheet and the release layer;
(F) electrically connecting a plurality of electrode pads formed on the surface of the semiconductor chip and the plurality of external terminals via a plurality of conductive members;
(G) sealing a part of each of the plurality of external terminals, the upper surface of the mother board, the semiconductor chip, and the plurality of conductive members with a resin to form a sealed body;
(H) A step of removing the mother substrate after the step (g) and exposing other portions of the release layer and the plurality of external terminals from the sealing body. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein upper surfaces of the plurality of external terminals are positioned higher than the chip mounting region on the upper surface of the mother substrate. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the following steps after the step (b):
(I) preparing a dicing tape having an upper surface, a second resin sheet attached to the upper surface, and a lower surface opposite to the upper surface;
(J) A step of attaching the semiconductor wafer to the upper surface of the dicing tape via the first resin sheet and the second resin sheet. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the following steps after the step (b):
(I) a step of attaching a second resin sheet to the first resin sheet;
(J) preparing a dicing tape having an upper surface and a lower surface opposite to the upper surface;
(K) A step of attaching the semiconductor wafer to the upper surface of the dicing tape via the first resin sheet and the second resin sheet. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the release layer is made of fluorine molecules. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the release layer has a thickness of 0.1 to 1 μm. In the manufacturing method of the semiconductor device according to claim 1,
In the step (h), the region where the semiconductor chip is located is recessed from the lower surface of the sealing body. A method for manufacturing a semiconductor device comprising the following steps:
(A) a first main surface, a plurality of chip regions formed on the first main surface, a scribe region formed between the plurality of chip regions, and a second main opposite to the first main surface Preparing a semiconductor wafer having a surface;
(B) attaching a first resin sheet having a top surface and a bottom surface opposite to the top surface to the second main surface of the semiconductor wafer and containing a plurality of fillers;
(C) After the step (b), heat is applied to the first resin sheet to cure the first resin sheet;
(D) Adhesion formed on the upper surface of the first resin sheet, the second resin sheet containing a plurality of fillers, and the dicing tape so that the second main surface of the semiconductor wafer faces the dicing tape Fixing the semiconductor wafer to the dicing tape through a layer;
(E) obtaining a semiconductor chip having the first resin sheet and the second resin sheet formed on the lower surface of the first resin sheet by dividing the semiconductor wafer;
(F) After the step (e), the adhesive layer of the dicing tape is cured, and the first resin sheet and the second resin sheet formed on the lower surface of the first resin sheet are included. Peeling the semiconductor chip from the dicing tape;
(G) preparing a mother substrate having an upper surface and a chip mounting region provided on the upper surface;
(H) mounting the semiconductor chip on the chip mounting region of the mother board via the first resin sheet and the second resin sheet;
(I) A step of applying heat to the second resin sheet after the step (h) to cure the second resin sheet. The method of manufacturing a semiconductor device according to claim 8.
The method for manufacturing a semiconductor device, wherein the second resin sheet in the step (h) is softer than the first resin sheet in the step (h). The method of manufacturing a semiconductor device according to claim 8.
The method of manufacturing a semiconductor device, wherein the hardness of the second resin sheet in the step (h) is lower than the hardness of the first resin sheet in the step (h). The method of manufacturing a semiconductor device according to claim 8.
The method for manufacturing a semiconductor device, wherein the filler content of the second resin sheet is less than the filler content of the first resin sheet. The method of manufacturing a semiconductor device according to claim 8.
The method of manufacturing a semiconductor device, wherein the second resin sheet in the step (d) is pasted on the upper surface of the dicing tape via the adhesive layer in advance. A semiconductor chip having a surface, a plurality of electrode pads formed on the surface, and a back surface opposite to the surface;
A plurality of external terminals provided around the semiconductor chip;
The semiconductor chip has a first upper surface and a first lower surface opposite to the first upper surface, contains a plurality of fillers, and the first upper surface faces the back surface of the semiconductor chip. A first resin sheet formed on the back surface;
Having a second upper surface and a second lower surface opposite to the second upper surface, and containing a plurality of fillers, such that the second upper surface faces the first lower surface of the first resin sheet, A second resin sheet formed on the first lower surface of the first resin sheet;
A release layer formed on the second lower surface of the second resin sheet;
A plurality of conductive members that respectively electrically connect the plurality of electrode pads of the semiconductor chip and the plurality of external terminals;
A sealing body for sealing the semiconductor chip, the plurality of external terminals, the plurality of conductive members, the first resin sheet, and the second resin sheet;
A semiconductor device comprising:   14. The semiconductor device according to claim 13, wherein a part of the second lower surface of the second resin sheet is exposed from the sealing body and the release layer. The semiconductor device according to claim 13.
The content of the filler of the second resin sheet is less than the content of the filler of the first resin sheet. A method for manufacturing a semiconductor device comprising the following steps:
(A) a first main surface, a plurality of chip regions formed on the first main surface, a scribe region formed between the plurality of chip regions, and a second main opposite to the first main surface Preparing a semiconductor wafer having a surface;
(B) a step of attaching a first resin sheet to the second main surface of the semiconductor wafer;
(C) an upper surface, a chip mounting region provided on the upper surface and having a recess or a through hole, a plurality of external terminals formed by electrolytic plating around the chip mounting region, and the side opposite to the upper surface Preparing a mother substrate having a lower surface of the conductive material and comprising a conductive member;
(D) mounting a semiconductor chip obtained by dividing the semiconductor wafer on the chip mounting region of the mother board via the first resin sheet;
(E) electrically connecting a plurality of electrode pads formed on the surface of the semiconductor chip and the plurality of external terminals via a plurality of conductive members;
(F) sealing a part of each of the plurality of external terminals, the upper surface of the mother board, the semiconductor chip, and the plurality of conductive members with a resin to form a sealed body;
(G) A step of removing the mother substrate after the step (f). In the manufacturing method of the semiconductor device according to claim 16,
The method of manufacturing a semiconductor device, wherein a planar shape of the recess or the through hole is a cross shape or a circular shape.   17. The method of manufacturing a semiconductor device according to claim 16, wherein in the step (d), the semiconductor chip is placed on the mother substrate so that the plurality of electrode pads of the semiconductor chip do not overlap the recess in plan view. A semiconductor device manufacturing method comprising mounting in a chip mounting area.

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