JP2011170755A - Device, method and program for processing memory failure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent stoppage of a system even when a failure occurs in an RAID controller part. <P>SOLUTION: A node controller transfers, upon receipt of a memory write request from the arithmetic processor, the memory write request to each of the plurality of memory controllers connected to itself and a node controller of the other memory failure processing devices connected to itself. The node controller transfers, when a memory write request is transferred from the node controller of the other memory failure processing device connected to itself, the memory write request to each of the plurality of memory controllers connected to itself. Each of the plurality of memory controllers performs, when the memory write request is transferred and this memory write request is to a memory DIMM serving under itself, storage of data according to the write request. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to continuing system operation even when a multi-bit error or a memory controller failure occurs in a memory DIMM (Dual Inline Memory Module).

  In recent years, there has been a demand for a system that can perform maintenance intervention without stopping operation even if a failure occurs. There is a similar request for the memory, and one of the countermeasures is redundancy by the memory RAID.

  For example, Patent Document 1 discloses a technique related to redundancy of memory RAID. The technique described in Patent Document 1 proposes the following configuration.

  In the memory system described in Patent Document 1, the first data memory is the first memory controller, the second data memory is the second memory controller, and the parity memory is the parity memory. Coupled to the controller, the parity controller is directly coupled to the first and second memory controllers. The parity data control logic stores and retrieves parity information associated with the data in the first and second data memories, and the parity data control logic is associated with the data in the first data memory. The parity data is interleaved in the parity memory with the parity data associated with the data in the second data memory. By adopting the configuration as described above, it is possible to prevent the system from being complicated for the memory controller level RAID.

JP 2005-108224 A

When a memory DIMM failure such as a multi-bit error or a memory controller failure occurs, the DIMM or memory controller cannot guarantee data under its control, causing a system stop or the like. In order to avoid this, memory duplication and memory RAID are performed as in the technique described in Patent Document 1, for example. However, since duplication, data striping, and parity generation / check are centrally managed, the load is concentrated on the parity generation unit and the data decoding unit, resulting in performance degradation. In addition, since a single RAID memory controller controls a plurality of striping data, a system down cannot be avoided when a failure occurs in the controller. For example, in the technique described in Patent Document 1, the parity data control logic 460 performs writing to the memory, and the parity control logic in each D controller performs parity check and data decoding of data read from the memory. Further, the memory control logic in each D controller accesses the subordinate memory at once. (See FIG. 6. Note that FIG. 6 corresponds to FIG. 4 of Patent Document 1.)
That is, a general memory RAID has a centralized RAID architecture, and the system performance depends on the performance of the RAID controller. In addition, there is a concern that the system may be stopped when a failure occurs in the RAID controller unit.

  Therefore, an object of the present invention is to provide a memory failure processing apparatus, a memory failure processing method, and a memory failure processing program that do not cause a system stop when a failure occurs in a RAID controller unit.

  According to a first aspect of the present invention, an arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and subordinates of the plurality of memory controllers A memory fault processing device comprising a memory DIMM (Dual Inline Memory Module) in the memory controller, wherein when the node controller receives a memory write request from the arithmetic processing device, the memory fault processing device is connected to the memory fault processing device. The memory controller transfers the memory write request to each of the plurality of memory controllers and the node controller of another memory failure processing apparatus connected to the memory controller, and the node controller is connected to the other memory failure processing. When a memory write request is transferred from the device node controller, The memory write request is transferred to each of the plurality of connected memory controllers, and each of the plurality of memory controllers is a case where the memory write request is transferred, and the write request is under its control. A memory failure processing apparatus is provided that stores data in accordance with a write request when the data is in a memory DIMM.

  According to a second aspect of the present invention, there is provided a memory fault processing system having a plurality of memory fault devices, wherein the plurality of memory fault devices are the memory fault devices described above. The

  According to a third aspect of the present invention, an arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a subordinate of each of the plurality of memory controllers A memory failure processing method performed by a memory failure processing device including a memory DIMM (Dual Inline Memory Module) in the memory controller, when the node controller receives a memory write request from the arithmetic processing device, The memory write request is transferred to each of the plurality of memory controllers connected to the node controller and to the node controller of the other memory failure processing apparatus connected to itself, and the node controller is connected to itself. The memory write request is transferred from the node controller of the other memory fault processor. If it is sent, the memory write request is transferred to each of the plurality of memory controllers connected to itself, and each of the plurality of memory controllers is a case where the memory write request is transferred. Thus, there is provided a memory failure processing method that stores data according to the write request when the write request is for a memory DIMM under its control.

  According to a fourth aspect of the present invention, an arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a subordinate of each of the plurality of memory controllers A memory fault processing device comprising a memory DIMM (Dual Inline Memory Module) in the memory controller, wherein when the node controller receives a memory write request from the arithmetic processing device, the memory fault processing device is connected to the memory fault processing device. The memory controller transfers the memory write request to each of the plurality of memory controllers and the node controller of another memory failure processing apparatus connected to the memory controller, and the node controller is connected to the other memory failure processing. When a memory write request is transferred from the device node controller, The memory write request is transferred to each of the plurality of connected memory controllers, and each of the plurality of memory controllers is a case where the memory write request is transferred, and the write request is under its control. A memory failure processing program is provided that causes a computer to function as a memory failure processing device that stores data in accordance with the write request when the data is in a memory DIMM.

  According to the present invention, since the RAID construction process is distributed and leveled by the distribution of the RAID function, even if one of the memory controllers having the RAID function is stopped due to a failure or data inconsistency occurs, Reconstruction is possible.

It is a figure showing the basic composition of the embodiment of the present invention. It is a figure which represents typically the exchange of the data at the time of write access. It is a flowchart showing the basic operation | movement of embodiment of this invention. It is a figure which represents typically the exchange of the data at the time of read access. It is a flowchart showing the operation | movement at the time of write access. It is a figure for demonstrating a related technique (it is a figure equivalent to FIG. 4 of patent document 1).

  First, an outline of an embodiment of the present invention will be described. An embodiment of the present invention is roughly as follows.

  When data is written from the CPU to the memory, the memory access is once received by the node controller, and then the transaction is transferred to all the memory controllers. Each memory controller that receives the transaction has a common RAID architecture, determines whether it is an access to the memory under its own control from the address, and writes the corresponding striping data if it is an access to the memory under its own control. .

  When data is read from the CPU to the memory, memory access is once received by the node controller as in the case of writing, and then the transaction is transferred to all the memory controllers. Each memory controller determines whether it is an access to its own subordinate memory from the address, and if it is an access to its own subordinate memory, returns the corresponding striping data. The node controller has a RAID architecture equivalent to each memory controller, collects data returned from each memory controller, and returns the data to the CPU. When an uncorrectable error in the memory DIMM or a failure of the memory controller occurs, the node controller corrects the data and transfers the data to the CPU.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, FIG. 1 shows a system comprising a plurality of CELLs according to this embodiment. The system includes a first CELL 100, a second CELL 200, a third CELL 300, and a fourth CELL 400. Although the number of CELLs is four for convenience of explanation this time, this does not limit the number of CELLs of this embodiment. You may make it implement | achieve this system by the number of CELLs other than four.

  The first CELL 100 includes CPUs 111 to 114, a node controller 121, and memory controllers 131 and 132. Similarly, the second CELL 200 includes CPUs 211 to 214, a node controller 221, and memory controllers 231 and 232. The third CELL 300 includes CPUs 311 to 314, a node controller 321, and memory controllers 331 and 332. The fourth CELL 400 includes CPUs 411 to 414, a node controller 421, and memory controllers 431 and 432. A memory DIMM is connected to each memory controller mounted on each CELL. Each CELL corresponds to the “memory failure processing apparatus” of the present invention. A system combining a plurality of CELLs corresponds to the “memory failure processing system” of the present invention.

  Next, the function of each unit described above will be described.

  The CPUs 111 to 114, the CPUs 211 to 214, the CPUs 311 to 314, and the CPUs 411 to 414 are arithmetic processing units. Each of these CPUs makes an access request to the memory via the node controller of each CELL. There are two access requests: write and read.

  The node controller 121, the node controller 221, the node controller 321 and the node controller 421 receive access requests from each CPU and transfer them to other node controllers. Further, the striping data and parity returned from each memory controller are collected to the node controller under the CPU that issued the read request, and the data is assembled by the node controller. When a part of data is lost due to a failure of the memory controller or memory DIMM, the data is reconstructed by the node controller and the data is returned to the requesting CPU.

  When there is a write request, the memory controllers 131, 132, 231, 232, 331, 332, 431 and 432 determine whether the access is to the memory DIMM subordinate to the address, and at the same time, the memory controllers 131, 132, 231, 232, 331, 332, 431 and 432 Only the striping data or parity for which the subordinate memory DIMM is in charge is stored. When there is a read request, each memory controller determines whether it is an access to its own subordinate memory DIMM, and at the same time reads out the striping data or parity in charge from the subordinate memory DIMM by a common RAID architecture, Transfer to higher-level node controller.

  Next, an operation when a write access from the CPU to the memory occurs will be described with reference to FIG. 2 which is a diagram schematically showing exchange of data and FIG. 3 which is a flowchart showing the operation. This time, as a specific example, a case where a write access to the memory from the CPU 212 occurs will be described, but this does not limit the operation of the present embodiment. In this embodiment, any CPU can write access to the memory.

  First, in a system composed of a first CELL 100, a second CELL 200, a third CELL 300, and a fourth CELL 400 each having a CPU, a node controller, and a memory controller, the CPU 212 on the second CELL 200 to the memory Write access occurs (step S11).

  When the above write access occurs, the node controller 221 receives a write request from the CPU 212, and then transfers it directly to the node controllers 121, 321, and 421 of each CELL (step S12).

  Next, each node controller transfers the access as it is to the subordinate memory controller (step S13).

  Subsequently, each memory controller determines whether or not it is an access to its own subordinate memory DIMM based on preset information, and if it is a subordinate memory access, based on the preset information The data is divided to generate striping data or parity, and the data or parity corresponding to the memory DIMM is stored (step S14). In this example, it is assumed that the memory controller 131, 132, 231, 232, and 331 issued from the CPU 212 has made a memory write request to an address to be processed. In this case, processing is performed only by these five memory controllers, and striping data and possibly parity are stored in the memory DIMM under each controller. At this time, which part of data or parity is stored is determined from the address and the set offset.

  Next, an operation when a read access from the CPU to the memory occurs will be described with reference to FIG. 4 which is a diagram schematically showing exchange of data and FIG. 5 which is a flowchart showing the operation. Similar to the write access described above, in this embodiment, any CPU can read access to the memory.

  A read access to the memory from the CPU 413 on the fourth CELL 400 occurs (step S21).

  When the above read access occurs, the node controller 421 receives a read request from the CPU 413, and then transfers it directly to the node controllers 121, 221, and 321 of each CELL (step S22).

  Next, each node controller transfers the access as it is to the subordinate memory controller (step S23).

  Subsequently, each memory controller determines whether it is an access to its own memory DIMM based on preset information. If it is a memory access under its own, it reads out data to the memory DIMM. It performs (step S24).

  The data read from the memory DIMM is returned to the node controller with the lower address or parity flag added (Yes in step S25).

  The data received by each node controller is collected to the node controller 421 under the CPU 413 of the issuer, and the data is assembled by the node controller and returned to the requesting CPU 413 (step S26).

  At this time, if data cannot be returned due to a failure (No in step S25), an error flag is added from the memory controller and returned. Receiving this, the node controller 421 reconstructs data from the remaining striping data and parity, and returns the data to the requesting CPU 413 (step S27).

  The embodiment of the present invention described above has the following effects.

  The first effect is that the time required for data striping and parity generation can be shortened as compared with the centralized management method.

  This is because the RAID construction process is distributed and leveled by the distribution of the RAID function.

  The second effect is that data can be reconstructed even if one of the memory controllers having a RAID function is stopped due to a failure or data inconsistency occurs.

  The reason is that the striping data / parity generation unit and the data reconstruction unit are separated.

  The memory failure processing apparatus according to the embodiment of the present invention can be realized by hardware, but the computer reads a program for causing the computer to function as the memory failure processing apparatus from a computer-readable recording medium. It can also be realized by executing.

  In addition, the memory failure processing method according to the embodiment of the present invention can be realized by hardware, but the computer reads a program for causing the computer to execute the method from a computer-readable recording medium and executes the program. Can also be realized.

  Moreover, although the above-described embodiment is a preferred embodiment of the present invention, the scope of the present invention is not limited only to the above-described embodiment, and various modifications are made without departing from the gist of the present invention. Implementation in the form is possible.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary Note 1) An arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a memory DIMM (Dual Inline) under each of the plurality of memory controllers A memory fault processing apparatus comprising:
When the node controller receives a memory write request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And transfer the memory write request to
When the node controller receives a memory write request from a node controller of another memory failure processing apparatus connected to itself, the memory write request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers has a memory failure in which data is stored in accordance with the write request when the memory write request is transferred and the write request is for a memory DIMM under its control. A memory failure processing program for causing a computer to function as a processing device.

(Supplementary note 2) The memory fault processing program according to supplementary note 1, wherein
When the node controller receives a memory read request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And the memory read request is transferred to
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the memory read request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers attempts to read data in accordance with the read request when the memory read request has been transferred and the read request is for a memory DIMM under its control. A memory failure processing program that returns data read to the node controller when data reading is successful, and returns failure to the node controller when data reading fails.
(Supplementary note 3) The memory fault processing program according to supplementary note 2, wherein
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the node controller returns the read data or the failure returned from the memory DIMM under its control. To the node controller of the other memory fault processing device connected to itself,
When the node controller receives a memory read request from the arithmetic processing unit, the node controller displays the read data or the failure transferred from the node controller of another memory fault processing unit connected to the node controller. The data is assembled or reconstructed using the read data returned from the memory DIMM under its control or the failure, and the memory read request is made for the assembled or reconstructed data. A memory failure processing program which is returned to the arithmetic processing unit.
(Supplementary note 4) The memory fault processing program according to any one of supplementary notes 1 to 3,
The memory is stored by dividing the data based on preset information to generate striping data or parity, and storing the generated striping data or parity. .

100 first CELL
111, 112, 113, 114, 211, 212, 213, 214, 311, 312, 313, 314, 411, 412, 413, 414 CPU
121,221,321,421 Node controller 131,132,231,232,331,332,431,432 Memory controller 200 Second CELL
300 3rd CELL
400 4th CELL

Claims (10)

An arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a memory DIMM (Dual Inline Memory Module) under each of the plurality of memory controllers; A memory failure processing apparatus comprising:
When the node controller receives a memory write request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And transfer the memory write request to
When the node controller receives a memory write request from a node controller of another memory failure processing apparatus connected to itself, the memory write request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers stores data according to the write request when the memory write request has been transferred and the write request is for a memory DIMM under its control. A memory failure processing apparatus. The memory failure processing apparatus according to claim 1,
When the node controller receives a memory read request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And the memory read request is transferred to
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the memory read request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers attempts to read data in accordance with the read request when the memory read request has been transferred and the read request is for a memory DIMM under its control. A memory failure processing apparatus, wherein when the data reading is successful, the read data is returned to the node controller, and when the data reading fails, a failure notification is returned to the node controller. The memory failure processing apparatus according to claim 2,
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the node controller returns the read data or the failure returned from the memory DIMM under its control. To the node controller of the other memory fault processing device connected to itself,
When the node controller receives a memory read request from the arithmetic processing unit, the node controller displays the read data or the failure transferred from the node controller of another memory fault processing unit connected to the node controller. The data is assembled or reconstructed using the read data returned from the memory DIMM under its control or the failure, and the memory read request is made for the assembled or reconstructed data. A memory failure processing device, which is returned to the arithmetic processing device. The memory failure processing apparatus according to any one of claims 1 to 3,
The memory is stored by dividing the data based on preset information to generate striping data or parity, and storing the generated striping data or parity. .   5. A memory failure processing system having a plurality of memory failure devices, wherein the plurality of memory failure processing devices is the memory failure processing device according to any one of claims 1 to 4. An arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a memory DIMM (Dual Inline Memory Module) under each of the plurality of memory controllers; A memory fault processing method performed by a memory fault processing apparatus comprising:
When the node controller receives a memory write request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And transfer the memory write request to
When the node controller receives a memory write request from a node controller of another memory failure processing apparatus connected to itself, the memory write request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers stores data according to the write request when the memory write request has been transferred and the write request is for a memory DIMM under its control. A memory failure processing method characterized by the above. The memory failure processing method according to claim 6,
When the node controller receives a memory read request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And the memory read request is transferred to
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the memory read request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers attempts to read data in accordance with the read request when the memory read request has been transferred and the read request is for a memory DIMM under its control. A memory failure processing method comprising: returning data read to the node controller when data reading is successful; and returning failure to the node controller when data reading fails. The memory failure processing method according to claim 7,
When the node controller receives a memory read request from a node controller of another memory failure processing apparatus connected to the node controller, the node controller returns the read data or the failure returned from the memory DIMM under its control. To the node controller of the other memory fault processing device connected to itself,
When the node controller receives a memory read request from the arithmetic processing unit, the node controller displays the read data or the failure transferred from the node controller of another memory fault processing unit connected to the node controller. The data is assembled or reconstructed using the read data returned from the memory DIMM under its control or the failure, and the memory read request is made for the assembled or reconstructed data. A memory failure processing method comprising returning to the arithmetic processing unit. The memory failure processing method according to any one of claims 6 to 8,
The data storage is performed by dividing the data based on preset information to generate striping data or parity, and storing the generated striping data or parity. . An arithmetic processing unit, a node controller connected to the arithmetic processing unit, a plurality of memory controllers connected to the node controller, and a memory DIMM (Dual Inline Memory Module) under each of the plurality of memory controllers; A memory failure processing apparatus comprising:
When the node controller receives a memory write request from the arithmetic processing unit, each of the plurality of memory controllers connected to itself and a node controller of another memory fault processing unit connected to the node controller And transfer the memory write request to
When the node controller receives a memory write request from a node controller of another memory failure processing apparatus connected to itself, the memory write request is sent to each of the plurality of memory controllers connected to the node controller. Forward and
Each of the plurality of memory controllers has a memory failure in which data is stored in accordance with the write request when the memory write request is transferred and the write request is for a memory DIMM under its control. A memory failure processing program for causing a computer to function as a processing device.

Images