JP2011165936A - Laminated chip control circuit and laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a laminated chip to self-recognize an end chip which turns back transfer data. <P>SOLUTION: The laminated chip control circuit includes an input terminal (SE) for an SE signal common to each of the semiconductor chips (1, 2), an input terminal (SE2) for an SE2 signal in which the SE signal is branched at an immediate upper chip and returned, and an SO control circuit 24 which detects an end chip depending on the presence or absence of the SE2 signal input. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a stacked chip control circuit that controls data transfer to one side in a stacking direction in a plurality of stacked semiconductor chips, and a stacked semiconductor device that includes a stacked chip control circuit for each semiconductor chip.

A stacked semiconductor device is known in which a plurality of semiconductor chips are stacked to increase the degree of integration.
In a laminated semiconductor device, another semiconductor chip is usually bonded on the lowermost semiconductor chip as a base. However, if a plurality of thin semiconductor chips are stacked, it is possible to achieve high integration at a limited height. It is.
On the other hand, if a connection method such as wire bonding is used for a thin semiconductor chip, the chip strength is difficult, and if the semiconductor chip is thin, it is easy to form a through via that penetrates the thickness direction. A chip-to-chip connection method is generally performed.

  In this connection method, it is necessary to achieve consistency between the chip surfaces to be bonded with respect to the position of the through via. Although it is possible to combine the conductive layer and the contact via (plug) in order to shift the position of the connection terminal to the side, the restriction on the position of the connection terminal is still great.

  On the other hand, semiconductor chips with the same number and position of input / output terminals may be stacked. For example, in a memory device, a large scale can be achieved by stacking a plurality of semiconductor chips each having an integrated circuit having the same configuration including input / output terminals. At this time, if the configuration of the semiconductor chip is exactly the same, a chip cut out from a single wafer can be used, and the chip cost can be greatly reduced. In addition, since the specifications of the data input / output terminals may be the same even if the circuit functions are different from the same viewpoint, in such a case, chip stacking using through vias is possible even in the logic circuit.

A stacked memory device in which memory chips are stacked in layers is known (see, for example, Patent Document 1).
In Patent Document 1, through vias are formed at different positions in an internal circuit alternately between odd-numbered and even-numbered semiconductor chips. This makes it possible to easily set information in the internal circuit by changing the position of the input-side through via and the position of the output-side through via.

  On the other hand, as another example of stacking semiconductor chips having the same number and position of input / output terminals, there is a circuit for so-called scan test.

  Among scan tests, a test called boundary scan, in particular, can be inspected only after chip stacking because it detects a terminal connection failure between semiconductor chips. Therefore, the test data (test pattern) input from the lowermost base chip is transferred to an upper layer between circuits called scan chains. A boundary scan control circuit (boundary scan controller) for controlling the output of the execution instruction and data input / output at this time and controlling the operation of the scan chain circuit is required. The boundary scan controller also has a role of associating the relationship between the position in the stacked chip of the scan chain circuit to be tested and the output data.

  In the boundary scan controller, the same circuit is used for stacked semiconductor chips. The SI (Scan Data Input) terminal on the lower surface of the chip and the SO (Scan Data Output) terminal on the upper surface of the chip are arranged to be connected when stacked. However, it is not possible to realize a feedback path in which, for example, an SI signal (control data) input from the lowermost chip returns to the lowermost chip again.

  In order to return the control data to the lowermost layer chip, it is necessary to detect that the chip is the uppermost layer, and a circuit configuration for that purpose is proposed in Patent Document 2, for example.

JP 2008-187061 A JP 2004-264057 A

Although there are only two types in Patent Document 1, it is necessary to make different semiconductor chips having different configurations. For this reason, the costs involved in the development and manufacture of the semiconductor chips are large, and complicated process management is required when the order of stacking the semiconductor chips is alternated, resulting in an increase in assembly cost.
Further, Patent Document 1 does not disclose a circuit configuration for detecting that the chip is the uppermost layer chip in order to create a path for returning to the lowermost chip. If a chip having this circuit configuration is required, the number of semiconductor chips is further increased to three, and the development and manufacturing cost and assembly cost of the semiconductor chip increase.

  The technique described in Patent Document 2 described above has means for storing identification data (fixed data) of the uppermost chip, and by comparing this identification data with the identification data of each chip, the output destination of the control data is determined. Control. Specifically, in the control data output control, the path connection control to the TDO2 terminal to which the feedback path is connected among the TDO terminal and the TDO2 terminal to which the control data is branched and sent is based on the result of the comparison. Do it.

  For this purpose, means for storing fixed data, means for storing identification data, and means for comparing these data are required, and the semiconductor chip size increases. Further, a means for storing fixed data in advance and inputting identification data at the time of the test is required, and the test cost is high.

  The present invention provides a multilayer chip control circuit that can recognize itself when it is necessary to recognize that it is a semiconductor chip at the end of data transfer, such as boundary scan control, and therefore has a small circuit scale. It is. The present invention also provides a laminated semiconductor device in which a plurality of semiconductor chips each equipped with such a laminated chip control circuit are laminated.

The multilayer chip control circuit according to the present invention includes an input terminal for a common signal, an input terminal for a branch control signal, and an end chip detection circuit.
The common control signal is a signal given in common to each semiconductor chip of a plurality of stacked semiconductor chips.
The branch control signal is a signal that is branched and input from the other semiconductor chip adjacent to the data output side to the common control signal supplied to the other semiconductor chip.
When the common control signal is input but the branch control signal is not input, the end chip detection circuit detects that it is a terminal semiconductor chip in the stacking direction.

  According to the above configuration, when there is no branch control signal input to the end chip detection circuit, the stacked chip control circuit is mounted on the end chip, that is, the terminal semiconductor chip in the direction of sending the control signal. It can be detected. On the other hand, when a branch control signal is input to the end chip detection circuit, it can be detected that the multilayer chip control circuit including the multilayer chip control circuit including the end chip detection circuit is not an end chip.

  Therefore, it is not necessary to provide chip identification data or data for identifying the uppermost layer from the outside, and self-recognition (automatic detection) of the end chip can be easily performed. The detection result of the end chip enables control to connect the output destination of the control data to the feedback path only for the end chip. It should be noted that a chip identification method in which the chip identification data is included in the control data according to the test specification or the count value indicating the number of tests is incrementally transferred to replace the chip identification data is allowed. However, in the present invention, identification data is not used for detecting the end chip.

According to the present invention, when it is necessary to recognize that it is a semiconductor chip at the end of data transfer, for example, boundary scan control, the self-recognition is possible. Can be provided.
In addition, according to the present invention, it is possible to provide a low-cost laminated semiconductor device in which a plurality of semiconductor chips on which such a laminated chip control circuit is mounted are laminated.

It is a schematic diagram of the lamination | stacking state of the lamination | stacking semiconductor device which mounts the lamination | stacking chip control circuit concerning embodiment. It is a schematic block diagram of a multilayer chip control circuit and an internal circuit. It is a schematic block diagram of a boundary scan controller. It is a lamination | stacking block diagram of the lamination | stacking semiconductor device which mounts a boundary scan controller. 5 is a circuit diagram showing a first configuration example of an SO control circuit and a chart showing states of output terminals. 5 is a circuit diagram showing a second configuration example of an SO control circuit and a chart showing states of output terminals. 5 is a circuit diagram showing a third configuration example of the SO control circuit and a table showing the state of the output terminal. It is the figure which showed the penetration electrode position etc. of the semiconductor chip to laminate | stack. It is a figure which shows the structural example of the penetration electrode of Type A. It is a figure which shows the other structural example of the penetration electrode of type A. It is a figure which shows the structural example of the penetration electrode of Type B.

  The present invention can be widely applied to a laminated semiconductor device in which a plurality of semiconductor chips having the same configuration including a terminal arrangement at least in a laminated chip control circuit are laminated, and the laminated chip control circuit. The present invention can be widely applied as long as the same data or data processed by each chip is sequentially transferred between the semiconductor chips. Examples of such a stacked semiconductor chip include a stacked memory device and a stacked logic circuit device. In addition, the present invention can be widely applied to a control circuit for a scan test including a boundary scan test.

  The laminated chip control circuit and the laminated semiconductor device to which the present invention is applied include an end chip detection circuit that detects the end of the laminated chip opposite to the signal input side, or a circuit having the function (for example, output) Control circuit).

In addition, in the case of including a configuration for performing a scan test, the present invention is applied to both control circuits, whether the test target is an internal circuit itself or a boundary (boundary, here, meaning of an inter-chip connection state). it can. Needless to say in the case of a boundary scan test, even in the case of a normal scan test, there are cases where it is necessary to pass an execution command or the like between chips. Normally, it is preferable to perform this normal scan test in a chip state or wafer state before stacking, but there are cases where it is desired to perform a test that takes into account signal delay after stacking. In such a case, when control data is input in parallel to individual chips, the number of components for control input such as through vias becomes enormous, so that sequential transfer of control data to the upper layer is essential.
Note that the direction of sequential transfer of control data is not limited to the direction from the lower layer to the upper layer, but it is desirable that only the lowermost semiconductor chip can input / output data to / from the outside.

Hereinafter, embodiments of the present invention will be described in the following order with reference to the drawings, taking a boundary scan control circuit as an example.
1. Overall configuration of a stacked semiconductor device.
2. Configuration of multilayer chip control circuit.
3. Outline of the boundary scan test.
4). Route selection control by control signal.
5. 1 is a first configuration example of an SO control circuit.
6). 2 shows a second configuration example of an SO control circuit.
7). The 3rd structural example of SO control circuit.
8). Example of correspondence between electrode structure and terminal.
9. Modified example.

<1. Overall Configuration of Multilayer Semiconductor Device>
FIG. 1 is a schematic diagram of a stacked state of a stacked semiconductor device equipped with a stacked chip control circuit according to an embodiment of the present invention.
The stacked semiconductor device illustrated in FIG. 1 includes a semiconductor chip 1 on the lowest layer (input end side) connected to an external tester (not shown), and a semiconductor chip group 2 stacked on the semiconductor chip 1. Has been.

The semiconductor chip 1 has an internal circuit (not shown) and a laminated chip control circuit 20 in the integrated circuit.
The semiconductor chip 1 also has an SI pad 11 that is a terminal for scan data input (SI) and an SO pad 12 that is a terminal for scan data output (SO).
Here, the scan data corresponds to “control data” in the present invention. Hereinafter, the scan data is referred to as control data.

The multilayer chip control circuit 20 has an SI terminal and an SO terminal. The SI terminal is internally connected to the SI pad 11, and the SO terminal is internally connected to the SO pad 12.
The SI pad 11 and the SO pad 12 are, for example, pads for wire bonding, but may be provided on the back surface of the semiconductor chip 1 and connected to the mounting substrate.

The semiconductor chip group 2 and the semiconductor chip 1 constitute a “plurality of semiconductor chips” of the present invention.
Here, the number of chips included in the semiconductor chip group 2 is arbitrary, and the semiconductor chip group 2 only needs to include one or more semiconductor chips. Hereinafter, the chip at the uppermost layer (terminal) in the semiconductor chip group 2 is particularly referred to as “terminal semiconductor chip 2 end”.

  Each chip constituting the semiconductor chip group 2 is provided with a laminated chip control circuit 20 having the same configuration as that of the semiconductor chip 1 in the integrated circuit. In addition to this, an internal circuit (not shown) is included in the integrated circuit of each chip. The internal circuit of each chip may be the same in the semiconductor chip group 2 or may be different for each chip. Here, the laminated chip control circuit 20 having the same configuration is included in all of the plurality of semiconductor chips.

Each chip in the semiconductor chip 1 and the semiconductor chip group 2 includes a boundary scan controller 21 in the laminated chip control circuit 20. The boundary scan controller 21 corresponds to the “boundary scan control circuit” of the present invention.
Although details will be described later, the boundary scan controller 21 has a function of receiving control data given from the SI pad 11 and passing it to the upper layer. Further, data indicating a test result generated in the intermediate layer chip control circuit 20 (a kind of control data) is also sent to the upper layer. The test data input at this time is also a kind of control data. The transfer path to the upper layer of these control data is hereinafter referred to as a forward path FR.

The forward path FR is turned back at the uppermost (end) semiconductor chip 2end to become a feedback path FBR.
The boundary scan controller 21 of the terminal semiconductor chip 2end has a function of returning the path by detecting the terminal semiconductor chip and connecting the forward path FR to the feedback path FBR. A detailed circuit configuration for this purpose will be described later.

<2. Configuration of multilayer chip control circuit>
FIG. 2 is a schematic configuration diagram of the multilayer chip control circuit 20 and internal circuits, and FIG. 3 is a schematic block diagram of the boundary scan controller 21.

  The laminated chip control circuit 20 illustrated in FIG. 2 includes a boundary scan controller 21 and a scan chain circuit 22 controlled thereby.

The boundary scan controller 21 has five control input terminals, that is, an SCK (Scan Clock) terminal, an SI terminal, an SRST (Scan Reset) terminal, an SE (Scan Enable: enable signal) terminal, and an SE2. (Scan Enable: an enable signal input from a semiconductor chip on one level).
Note that the symbols “SCK”, “SI (and SO)”, “SRST”, “SE”, and “SE2” included in this terminal name bear the respective symbols as shown in part above. It is also used for signal names that are input and output from the selected terminals, and in some cases, path names.
Here, the SE signal corresponds to the “common control signal” of the present invention, and the SE2 signal corresponds to the “branch control signal” of the present invention.

  Although FIG. 2 shows the internal logic circuit 30 as an internal circuit, other circuits such as an internal memory circuit may be used. Although only 10 connection terminals are shown between the internal logic circuit 30 and the outside, the number thereof is arbitrary. Usually, a larger number of connection terminals are connected to the internal logic circuit 30.

There are five connection terminals on the left side and five on the right side. For example, the five terminals T1 to T5 on the left side are chip back surface terminals, and the five terminals T6 to T10 on the right side are chip surface terminals. And
Note that all the terminals T1 to T10 shown in FIG. 2 may be chip front terminals or chip back terminals. Here, a case where the scan chain circuit 22 is used not only as a boundary scan test but also as a scan chain for internal circuit operation is illustrated. For convenience of explanation, it is assumed that the terminals T1 to T5 are provided on the back side (signal input side) and the terminals T6 to T10 are provided on the front side (signal output side).

All terminals T1 to T10 that are assumed to be signal inputs can be connected to corresponding signal inputs of the internal logic circuit 30 via flip-flop circuits FF constituting the scan chain circuit 22.
Although not particularly illustrated, the flip-flop circuit FF includes terminals for data input, data output, clock input, and shift enable signal input. The data output terminal of each flip-flop circuit FF is connected to the data input of the next-stage flip-flop circuit FF.

This interconnection is made up of ten flip-flop circuits FF to form a shift register. The data input and data output of the flip-flop circuits FF at both ends are connected to the boundary scan controller 21.
In all flip-flop circuits FF constituting the scan chain circuit 22, a common clock signal can be applied in parallel from the boundary scan controller 21 to the clock input terminal.

  In the scan chain circuit 22, a part of the flip-flop circuits FF group (FF1 to FF5) is arranged on the input side of the internal logic circuit 30, and the other part of the flip-flop circuit FF group (FF6 to FF10) is internal logic. Placement and wiring are arranged so as to be arranged on the output side of the circuit 30. A predetermined number of flip-flop circuits FF may be arranged between the input-side and output-side flip-flop circuits FF as necessary, but here, five input-side and five output-side flip-flop circuits FF are provided by detour wiring. Is connected.

  The five flip-flop circuits FF arranged on the input side of the internal logic circuit 30 shown in FIG. 2 are connected to other logic circuits in the previous stage (not limited to the circuit under test) or externally input patterns (part of test data, the following , Also referred to as SI signal). Among these, the input pattern from the outside is given from the boundary scan controller 21 to the flip-flop circuit FF at the end. After the setting, the scan chain circuit 22 enters the shift mode under the control of the boundary scan controller 21. Then, every flip-flop circuit FF constituting the scan chain circuit 22 shifts the held bits of each flip-flop circuit FF to the subsequent flip-flop circuit FF every time a clock pulse is input to the clock input terminal. I do.

  The boundary scan controller 21 illustrated in FIG. 3 includes a boundary scan control circuit 23 and an SO control circuit 24.

  The boundary scan control circuit 23 is a circuit that performs the main part of the scan test control. The above-described input data is applied to the scan chain circuit 22 and synchronous control is performed by clock input. Further, the test results and the scan chain circuit 22 and internal circuits Is associated.

  The boundary scan control circuit 23 also controls the operation of receiving an output pattern after the scan test (also referred to as SO signal as part of test data) from the other end of the scan chain circuit 22 and returning it to the external tester.

  Further, the boundary scan control circuit 23 holds the input pattern (SI signal) given from the external tester in an internal holding register or the like, and outputs it to another boundary scan control circuit 23 on the upper layer or resets the SO signal. Then, the SI signal is initialized. The initialization of the SI signal by the transfer of the SI signal or the reset of the SO signal is controlled by the SRST signal given from the external tester.

The path of control data sent from the boundary scan control circuit 23 to the upper layer is called an internal SO path (Int-SO: internal scan out data).
The boundary scan control circuit 23 is given an SCK signal from an external tester. The SCK signal is used for the operation of the scan chain circuit 22 shown in FIG.

The SO control circuit 24 has an internal path that inputs an SO signal from an internal SO path (Int-SO) and branches the output destination into two, and has the above-described end chip detection function. The SO control circuit 24 is an example of the “end detection circuit” of the present invention. As described above, the end chip detection circuit of the present invention conceptually includes a circuit substantially including its function. Of course, the end chip detection circuit includes a circuit having only an end chip detection function.
The SO control circuit 24 in the present embodiment has a function of performing output control to determine the connection destination of the internal SO path (Int-SO) as either the SO terminal or the SO2 terminal, in addition to the end chip detection function. .

Here, the SE signal as the common control signal and the SE2 signal as the branch control signal will be described.
The SE signal and the SE2 signal are assumed to be SE = SE2 = L in the normal mode (non-test mode), and are assumed to be SE = SE2 = H in the scan test mode.
The SO path shown in the box of the SO control circuit 24 in FIG. 3 is a path connecting the internal SO path (Int-SO) and the SO terminal, and corresponds to the “internal data path” of the present invention. The SO2 path is a path connecting the internal SO path (Int-SO) and the SO2 terminal, and corresponds to the “branch path” of the present invention.
The SI terminal, SO terminal, and SO2 terminal constitute a serial interface for inputting and outputting test data.

<3. Outline of Boundary Scan Test>
The boundary scan controller 21 can electrically test the chip connection between the semiconductor chip 1 and the semiconductor chip group 2 by a path through which the SO signal output from the semiconductor chip 1 returns to the semiconductor chip 1 through the semiconductor chip group 2. It has become. This path is shown in FIG. 1 as FR path → SO2 path of the end semiconductor chip 2end → FBR path.
This test is a boundary scan test for testing whether a terminal connection state (boundary state) between chips is good or poor. The subject of the boundary scan test is an external tester (not shown), and the object is the stacked semiconductor device shown in FIG. The semiconductor chip 1 receives a supply of a clock and voltage from an external tester in addition to control data from a number of terminals including the SI pad 11 and the SO pad 12, and executes a boundary scan test.

  In the boundary scan test, control data is input from the SI pad 11 to the boundary scan controller 21 of the semiconductor chip 1, and this is sequentially transferred to the next higher level chip. The input control data includes a bit array (test data) that is actually used during a test, in addition to control information such as a test execution instruction, stop, and reset. The control data output from the semiconductor chip 1 includes output data indicating the test result.

Therefore, in the boundary test, every time the boundary between two adjacent semiconductor chips is tested, it is executed by examining how the test bit array (output data with respect to the test data at the time of input) changes with an external tester. .
This one boundary test is repeatedly performed from the lower layer to the upper layer for each inter-chip boundary (chip connection terminal group).
Each time one boundary test is executed, control information such as an execution instruction is sent to the upper layer. The test data (input data) moves between the registers respectively provided in the two boundary scan control circuits 23 of the adjacent chip every time one boundary test is executed. Further, every time one boundary test is executed, output data indicating the test result is read from the scan chain circuit 22 in the upper chip of the two semiconductor chips sandwiching the boundary. The read output data is further taken into control data transmitted to the upper layer.

In the feedback path FBR sent from the lower layer to the upper layer and returned from the uppermost layer shown in FIG. 1, input data and various control information are mixed in addition to the output data. The external tester that receives these data as serial data is the control entity that controls the clock transfer of these data, so that it knows that only the window section on the time axis indicated by the clock signal is the data indicating the test result. Can do.
The external tester can detect which terminal is open in the connection terminal group at the inter-chip boundary by comparing the test result with the input data sent first. That is, if there is a bit change between an input data bit and an output data bit having the same terminal address, it can be determined that the terminal is open.

Since the end semiconductor chip 2end shown in FIG. 1 can detect that it is an end chip, it can be changed to a configuration that blocks data other than output data.
For example, the SO control circuit 24 shown in FIG. 3 may receive timing control from the boundary scan control circuit 23 to mask data other than the output data.
However, in this case, the circuit scale increases and there is no problem even if control information is sent back. Therefore, it is desirable that the SO control circuit 24 outputs the information as it is without selecting information.

<4. Route selection control by control signal>
FIG. 4 is a stacked block diagram of a stacked semiconductor device on which the boundary scan controller 21 is mounted.
It is assumed that a signal input to the boundary scan controller 21 is supplied from a lowermost semiconductor chip (not shown). The SE signal (common control signal) input to the semiconductor chip is branched by physical means such as vias. One of the two branched SE signals is input to the boundary scan control circuit 23 and the SO control circuit 24 in the boundary scan controller 21. The other SE signal (SE2) is output to the semiconductor chip one layer below.

As shown in FIG. 3, the boundary scan controller 21 includes an SE signal input terminal (SE terminal) and an SE2 signal input terminal (SE2 terminal). These two signals are input to the SO control circuit 24. Since the SE signal is a mode signal, it is also sent to the boundary scan control circuit 23.
The SE terminal is the “common control signal input terminal” of the present invention, and the SE2 terminal is the “branch control signal input terminal” of the present invention.

  In the SO control circuit 24, whether the signal from the internal SO signal (Int-SO) is output to the SO terminal or the SO 2 terminal depending on the logic of the SE signal and the SE 2 signal input from the semiconductor chip on one layer. Be controlled.

In the uppermost semiconductor chip, the SE2 signal that should be input from the semiconductor chip one layer above is not input, and the SE2 terminal is electrically floating (or fixed to L). For this reason, in the terminal semiconductor chip 2end, the SO2 path (branch path) is connected to the feedback path FBR, which is the SO path, under the control of the SO control circuit 24 in FIG.
The SE2 terminal of the other chip is connected to the SI terminal of the semiconductor chip one level above, so that the SO2 signal is input. In this case, the SO control circuit 24 places the SO2 path end in a floating state.

  In the configuration of FIG. 4, not only the SE signal path and the feedback path FBR, but also the SRST path and the SCK path are provided in parallel to a plurality of semiconductor chips by through via paths outside the chip.

<5. First Configuration Example of SO Control Circuit>
FIG. 5A is a circuit diagram showing a first configuration example of the SO control circuit 24. FIG. 5B shows a table of SO and SO2 states for each mode divided into the uppermost layer and other layers. In the following description, when both the signal and the terminal can be taken, only the symbol such as “SO” is described.

In the circuit shown in FIG. 5, two transfer gates TG1 and TG2 are connected in series to the SO2 path. A branch point BP exists on the input side of the transfer gate TG1. In this circuit, the branch point BP, the internal SO signal (Int-SO) input terminal, and the SO terminal are connected in a straight line to form an internal data path (SO path).
The transfer gate TG1 is controlled by the SE signal and the inverted SE signal (/ SE) by the inverter INV1, and the transfer gate TG2 is controlled by the SE2 signal and the inverted SE2 signal (/ SE2) by the inverter INV2. In this example, when the SE2 signal is not given, its input node (SE2 terminal) is fixed to L via a resistor.

In this circuit configuration, the Int-SO signal is output to the SO terminal as it is, and is always output to the semiconductor chip one layer above the semiconductor chip of interest. With respect to SO2, in the scan test mode, SE = SE2 = H in the semiconductor chip other than the uppermost layer, the SO2 terminal is in a floating state, and is disconnected from the SO through via path common to all stacked semiconductor chips. Become.
On the other hand, in the uppermost semiconductor chip, the SE = H and SE2 terminals are in a floating state, but the Int-SO signal is also output to the SO2 terminal because the SE2 terminal is in an L state by a resistor that pulls the SE2 terminal down to the GND level. .
As a result, it is possible to realize a boundary scan chain in which the SI signal output from the lowermost semiconductor chip returns to the lowermost layer from the uppermost SO2 terminal via the boundary scan controller 21 of each stacked semiconductor chip.

  In the normal mode, SE = SE2 = L in the semiconductor chip other than the uppermost layer, and the SO2 terminal is fixed to L. In the uppermost semiconductor chip, SE = L and SE2 are in a floating state, the SO2 terminal is fixed to L, and data collision does not occur at the SO2 terminal.

  Since SE2 = H in the test mode, a small current flows between the VDD power supply and the GND power supply via the pull-down resistor. However, in the normal mode, SE2 = L, so that the semiconductor chip, There is no demerit such as an increase in current consumption of the stacked semiconductor device.

<6. Second Configuration Example of SO Control Circuit>
FIG. 6A is a circuit diagram showing a second configuration example of the SO control circuit 24. FIG. 6B shows a table showing the states of SO and SO2 separately for the uppermost layer and other layers for each mode.
6A is different from FIG. 5A in that the transfer gate TG3 is connected to the SO path and the SO terminal can be fixed to L by the transistor T2. The transfer gate TG3 is controlled by a signal similar to that of the transfer gate TG2, but the combination of the NMOS transistor and the PMOS transistor with respect to the control signal is reversed, and the transfer gate TG2 is inverted. The transistor T2 is controlled by the output of the inverter INV2.

In the scan test mode, in a semiconductor chip other than the uppermost layer, SE = SE2 = H, (Int-SO) is output from the SO terminal, and SO2 is (Hi-Z). In the uppermost semiconductor chip, SE = H and SE2 are floating, but are fixed to L by a pull-down resistor. Therefore, (Int-SO) is output from the SO2 terminal, and the SO terminal is fixed to L. As a result, it is possible to realize a boundary scan chain in which the SI signal output from the lowermost semiconductor chip returns to the lowermost layer from the uppermost SO2 terminal via the boundary scan controller 21 of each stacked semiconductor chip.
In the normal mode, since SE = SE2 = L, both the SO terminal and the SO2 terminal are fixed to L, and data does not collide at SO2.

<7. Third Configuration Example of SO Control Circuit>
FIG. 7A is a circuit diagram showing a third configuration example of the SO control circuit 24. FIG. 7B shows the states of SO and SO2 in a table for each mode divided into the uppermost layer and the others.
The configuration of FIG. 7A is different from that of FIG. 6A in that the position of the transfer gate TG1 has moved to the front (input side) of the branch point BP. This input side path constitutes a part of the SO path.
The circuit operation is the same as in FIG.

<8. Example of correspondence between electrode structure and terminal>
FIG. 8 is a diagram showing the positions of the through electrodes of the semiconductor chips to be stacked.
There are two types of through electrodes, Type A (Type A) and Type B (Type B). Type A is a through via in which the electrode coordinates located above and below the semiconductor chip are the same and the upper and lower electrodes are short-circuited, or a through electrode having the same logic.
In type B, the coordinates of the electrodes located above and below the semiconductor chip are the same, but the logic between the electrodes is separated by a logic circuit and is not necessarily a through electrode.

Since SCK, SRST, SE, and SO2 need to connect the lowermost semiconductor chip and the other stacked semiconductor chips in parallel, a type A through electrode is employed.
The terminal that outputs the SE signal input from the lower semiconductor chip as it is to the lower semiconductor chip needs to be connected to the SE2 terminal of the lower semiconductor chip. In addition, the SI terminal and the SO terminal need to be serially connected between the stacked semiconductor chips. Therefore, a type B through electrode is adopted for both terminals.

Here, correspondence with the present invention will be described.
The SI provided on one chip surface (in this case, the lower surface) is defined as the “first input terminal” of the present invention. On the opposite surface (upper surface), the terminal constituting the type B through electrode corresponding to SI (first input terminal) is SO, which corresponds to the “first output terminal” of the present invention.
On the other hand, a terminal provided on the same chip surface as SI (first input terminal) and from which SE is branched and outputted toward the lower layer corresponds to the “second output terminal” of the present invention. SE2 provided on the upper surface on the opposite side corresponding to the second output terminal (SE output terminal) corresponds to the “second input terminal” of the present invention that receives SE output of the upper chip and inputs it as SE2. To do.

For type A, the through via that transfers SE from the lower layer to the upper layer corresponds to the “first through via” of the present invention. Further, the through via which is the basic configuration of the feedback path FBR by passing SO from the upper layer to the lower layer corresponds to the “second through via” of the present invention.
Note that the SO2 path from the SO control circuit 24 is connected to a node in the middle of the second through via, and in the uppermost layer chip where the SO2 path is the output of the SO signal, the SO layer is lower than this node. The feedback path is limited.

Among the three SO control circuit configuration examples shown in FIGS. 5 to 7, the first configuration example (FIG. 5) shows that the first input terminal and the first output terminal are used for transferring control data, the second input terminal and the second input terminal This is an example in which the usage of the path through which the branch control signal is returned to the two output terminals and the usage are fixed.
On the other hand, in the second and third configuration examples (FIGS. 6 and 7), if the logic (H and L) of the control signal is inverted from the above description, the set of the first input terminal and the first output terminal, The application can be switched in reverse depending on the combination of the second input terminal and the second output terminal.
Although this configuration slightly increases the number of circuit elements, there is an advantage that more flexible terminals can be used.

  The transfer gates TG1 and TG2 or the transfer gates TG2 to TG3 correspond to “a plurality of switches” of the present invention.

FIG. 9 is a diagram illustrating a structure example of a type A through electrode.
The electrodes E1 and E2 above and below the semiconductor chip are short-circuited, and at the same time as the signal from the lower layer is transmitted to the upper layer semiconductor chip, the corresponding semiconductor chip can be used. With this structure, when semiconductor chips are stacked, the same signal can be input to each semiconductor chip.

  Further, as shown in FIG. 10, it is possible to connect a redriver (buffer) serially between the electrodes without directly short-circuiting the upper and lower electrodes E1 and E2, and to input logically the same signal.

FIG. 11 is a diagram illustrating a structure example of a type B through electrode.
Although the electrodes E1 and E2 existing above and below the semiconductor chip are at the same coordinate, both electrodes are not short-circuited, and a logic circuit (boundary scan controller 21 in the example of FIG. 8) is serially connected between the electrodes. It has become.
With this structure, when semiconductor chips are stacked, it is possible to connect a desired input terminal and output terminal without short-circuiting the input terminal and output terminal of the semiconductor chip even in the case of the same semiconductor chip.

  In both types A and B, the signal to be connected to the upper layer electrode is determined by a normal semiconductor manufacturing method, and therefore there is no difference in the process steps for forming the through electrode. Even when different semiconductor chips are stacked, the boundary scan controller 21 of the present invention can be applied as long as the coordinates of the SI electrode and the SO electrode are the same.

<9. Modification>
Although the boundary scan test has been described in the above embodiment, the configuration illustrated in FIGS. 1 to 11 can be used as it is in the circuit operation scan test for testing the operation of the internal logic circuit 30 shown in FIG.
However, the boundary scan control circuit 23 in FIG. 3 provides the input data to the scan chain circuit 22 in FIG. 2 and receives the output data collected from the scan chain portion on the output side of the internal logic circuit 30. It is different from scanning. In other words, in the boundary scan, the output data obtained by passing the data given by the lower layer chip through the chip boundary is received by the chip on the first layer. On the other hand, in the circuit operation scan test, data input and output are completed within the same chip.
Although the detailed control involved is slightly different, the basic data transmission method and feedback method are common to both tests. Therefore, the present invention can also be applied to a circuit operation scan test.

  In addition, when the same semiconductor chip is stacked, as well as when different semiconductor chips are stacked, the connection of the stacked semiconductor chips can be electrically inspected by mounting the boundary scan controller 21 of the present invention. It is.

  According to the present invention, a boundary scan test and a circuit operation scan test can be easily performed without the need for a dedicated semiconductor chip or a chip ID identification circuit in the semiconductor chip. As a result, there is an advantage that development costs can be suppressed, productivity can be improved, yield management can be easily performed, and a stacked semiconductor device can be manufactured at low cost.

  DESCRIPTION OF SYMBOLS 1 ... Input side semiconductor chip, 2 ... Semiconductor chip group, 2end ... Terminal semiconductor chip, 20 ... Stacked chip control circuit, 21 ... Boundary scan controller, 22 ... Scan chain circuit, 23 ... Boundary scan control circuit, 24 ... SO control circuit, SE (common control signal and its input terminal), SE2 (branch control signal and its input terminal).

Claims (9)

A common control signal input terminal commonly applied to each of the plurality of stacked semiconductor chips;
A branch control signal input terminal to which the common control signal given to the other semiconductor chip is branched and input from another semiconductor chip adjacent to the data output side;
When the common control signal is input but the branch control signal is not input, an end chip detection circuit that detects a semiconductor chip at the end in the stacking direction;
A multilayer chip control circuit comprising: The end chip detection circuit is connected to a branch path branched from an internal data path for passing control data in the stacking direction from the input end semiconductor chip to the end semiconductor chip, or the branch path and the internal data The multilayer chip control circuit according to claim 1, further comprising a plurality of switches connected to both of the paths and controlled to be turned on and off by the common control signal and the branch control signal. The control data can be applied to a stacked semiconductor device having a feedback path for returning the control data from the terminal semiconductor chip to the input-end semiconductor chip and outputting it to the outside by connection with through vias penetrating the plurality of semiconductor chips. ,
The branch path is a path for connecting the internal data path to the feedback path,
The plurality of switches is a logic circuit that brings the branch path into a conductive state at the terminal semiconductor chip to which the branch control signal is not inputted and blocks the branch path at another semiconductor chip to which the branch control signal is inputted. The multilayer chip control circuit according to claim 2, having a configuration. A first input terminal;
A first output terminal provided at a position corresponding to the first input terminal on the front and back surfaces of the semiconductor chip;
A second output terminal provided on the same chip surface side as the first input terminal;
A second input terminal provided at a position corresponding to the second output terminal on the chip surface side opposite to the second output terminal;
A first through via that penetrates the front and back surfaces of the semiconductor chip and serves as an input / output terminal for the common control signal;
A second through via penetrating the front and back surfaces of the semiconductor chip to form the feedback path;
The multilayer chip control circuit according to claim 3, comprising: The first input terminal and the first output terminal are terminals connected to the internal data path to transfer the control data;
The multilayer chip control circuit according to claim 4, wherein the second input terminal and the second output terminal are terminals of a path through which the branch control signal is returned. The set of the first input terminal and the first output terminal, and the set of the second input terminal and the second output terminal are a pair of terminals for passing the control data and a path through which the branch control signal is returned. 5. The multilayer chip control circuit according to claim 4, wherein the function of the terminal pair can be changed according to the logic of the first and branch control signals. The laminated chip control circuit is
Test data when testing the terminal connection between semiconductor chips for data input / output terminals of internal circuits that input multiple data in parallel and output multiple data generated in response to input data in parallel A scan chain circuit that serially transfers data in a semiconductor chip and in parallel between semiconductor chips;
A boundary scan control circuit that synchronously controls the transfer operation of the scan chain circuit between a plurality of semiconductor chips, and sequentially transfers the control data including the execution instruction at that time in the stacking direction;
An output control circuit that has a function of the end test detection circuit by including the plurality of switches, and controls an output destination of control data according to a detection result;
The multilayer chip control circuit according to claim 1, comprising: A plurality of stacked semiconductor chips; and
A laminated chip control circuit provided in each of the plurality of semiconductor chips;
A through via path extending through the plurality of semiconductor chips;
Have
External signals can be input and output to the stacked chip control circuit of the semiconductor chip located at one end in the stacking direction,
The laminated chip control circuit is
A common control signal input terminal;
A branch control signal input terminal to which the common control signal given to the other semiconductor chip is branched and input from another semiconductor chip adjacent to the data output side;
An end chip detection circuit that detects a terminal semiconductor chip in the stacking direction based on a combination of logics of the input common control signal and the branch control signal;
Have
When the semiconductor chip provided with the laminated chip control circuit is not at the end, the output destination of the control data is the side that delivers in the stacking direction, and when the semiconductor chip at the end is detected, the output destination of the control data is A stacked semiconductor device that changes to the through via path side. The laminated chip control circuit is
Test data when testing the terminal connection between semiconductor chips for data input / output terminals of internal circuits that input multiple data in parallel and output multiple data generated in response to input data in parallel A scan chain circuit that serially transfers data in a semiconductor chip and in parallel between semiconductor chips;
A boundary scan control circuit that synchronously controls the transfer operation of the scan chain circuit between a plurality of semiconductor chips, and sequentially transfers the control data including the execution instruction at that time in the stacking direction;
An output control circuit for control data, which has the function of the end test detection circuit by including the plurality of switches, and controls the output destination of the control data according to the detection result;
The laminated semiconductor device according to claim 8, comprising:

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