JP2011165216A - Method and apparatus for vectorizing multiple input instructions - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an effective method and an apparatus for vectorizing a plurality of input instructions. <P>SOLUTION: The apparatus has an optimization unit for searching two or more instructions with operation codes with common traces and when the two or more instructions have the same levels in a trace dependence tree for merging the two or more instructions with one SIMD (Single Instruction Multiple Data) instruction. The trace dependence tree has instructions in a plurality of levels with instructions where each level has the same instruction, and the trace instruction is stored in a memory of the apparatus. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method and apparatus for vectorizing a plurality of input instructions.

  A central processing unit (CPU) of a computer system may include a plurality of function execution units that process instructions in parallel. These instructions may include SIMD (Single Instruction Multiple Data) instructions. The SIMD instruction can execute a common process for a plurality of data in parallel. Thus, SIMD instructions may allow the CPU to perform multiple iterations simultaneously, in order to reduce the overall execution time. The use of SIMD processing may be particularly effective in multimedia applications such as voice and image processing.

  An object of the present invention is to provide an effective method and apparatus for vectorizing a plurality of input instructions.

  In order to solve the above problem, one feature of the present invention is to search for two or more instructions having a common operation code of trace, and when the two or more instructions have the same level in a trace dependency tree, An apparatus having an optimization unit for merging two or more instructions into one SIMD (Single Instruction Multiple Data) instruction, wherein the trace dependency tree includes a plurality of instructions each having the same height instruction. The apparatus has a command, and the trace command is stored in a memory.

  According to the present invention, an effective method and apparatus for vectorizing a plurality of input commands can be provided.

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention. FIG. 2 is a block diagram of an optimization unit according to an embodiment of the present invention. FIG. 3 is a diagram of an exemplary dependency tree useful for describing a method for converting an instruction into a SIMD instruction according to one embodiment of the present invention. FIG. 4 is a table useful for explaining vectorization processing according to an embodiment of the present invention. FIG. 5 is a table useful for explaining vectorization processing according to another embodiment of the present invention.

  In the following detailed description, numerous specific details are provided to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, processes, components and circuits have not been described in detail so as not to obscure the present invention.

  Some of the detailed description below is provided in terms of symbolic representations and algorithms for data bits or binary digital signals in computer memory. These algorithmic descriptions and representations may be techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art.

  As will be apparent from the following description, the use of terms such as “processing”, “calculation”, “decision”, etc. throughout the present specification, unless specifically explained, is used in the registers and / or memory of the computing system. Manipulate and / or convert data represented as physical quantities such as electronic quantities into memory, registers or other such information storage, transmission or other data similarly represented as physical quantities in display devices It is understood to represent the actions and / or processes of a computer, computing system or similar electronic computing device. Further, the term “plurality” may be used throughout this specification to describe two or more components, devices, elements, parameters, and the like. For example, “a plurality of instructions” represents two or more instructions.

  The terms “SIMDization” or “vectorization” refer to processing that is scheduled for execution and that merges processing that requires similar execution resources such as registers and functional units into a single SIMD instruction. It should be understood that they are equivalent terms. Although the scope of the present invention is not limited to this, for simplicity of explanation, the term “vectorization” is the process of merging processes that are scheduled for execution and require similar execution resources. Used to explain.

  It should be understood that the present invention can be used in a variety of applications. Although the invention is not so limited, the circuits and techniques disclosed herein may be used in numerous devices such as computer systems, processors, CPUs and the like. Processors to be included within the scope of the present invention include RISC (Reduced Instruction Set Computer), processors having pipelines, CISC (Complex Instruction Set Computer), and the like.

  Some embodiments of the present invention, for example, when executed by a machine (eg, by a processor and / or other suitable machine) cause the machine to perform the methods and / or processes according to embodiments of the present invention. It may be implemented utilizing a machine readable medium or article capable of storing instructions or a set of instructions. Such machines may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, etc., and hardware and / or software You may make it implement | achieve using arbitrary appropriate combinations. A machine-readable medium or article may include, for example, any suitable type of memory unit, storage device, memory article, storage medium, storage device, storage article, storage medium and / or unit, for example, Memory, removable or non-removable medium, erasable or non-erasable medium, writable or rewritable medium, digital or analog medium, hard disk, floppy (registered trademark) disk, CD-ROM (Compact Disk Read Only Memory) , CD-R (Compact Disk Recordable), CD-RW (Compact Disk Rewriteable), optical disk, magnetic medium, various types of DVD (Digital Versatile Disk), tape, Set may be one and the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, such as C, Includes any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming languages such as C ++, Java, BASIC, Pascal, Fortran, Cobol, assembly language, machine code There may be.

  Referring to FIG. 1, a block diagram of a computer system 100 according to one embodiment of the present invention is shown. Although the scope of the present invention is not limited thereto, the computer system 100 may be a personal computer (PC), a personal digital assistant (PDA), an internet device, a cellular phone, or any other computing device. . In one example, computer system 100 may have a main processing unit 110 that is driven by a power source 120. In an embodiment of the present invention, the main processing unit 110 may include a multi-processing unit 130 that is electrically connected to the storage device 140 and one or more interface circuits 150 by a system interconnect 135. For example, system interconnect 135 may be an address / data bus, if desired. It should be understood that interconnects other than buses can be used to connect the multi-processing unit 130 to the storage device 140. For example, one or more dedicated lines and / or crossbars can be used to connect the multi-processing unit 130 to the storage device 140.

According to some embodiments of the present invention, the multi-processing unit 130 may be an Intel® Pentium ^™ based microprocessor, an Intel® Itanium ^™ based microprocessor, and / or an Intel ( It may have any type of processing unit such as an XScale ^™ processor of the registered trademark. Further, the multi-processing unit 130 may have any type of cache memory such as SRAM (Static Random Access Memory). The storage device 140 may include a DRAM (Dynamic Random Access Memory), a nonvolatile memory, or the like. As an example, the storage device 140 may store a software program that can be executed by the multi-processing unit 130 if desired.

  Although the scope of the present invention is not limited to this, the interface circuit 110 may include an Ethernet (registered trademark) interface, a USB (Universal Serial Bus) interface, or the like. In an embodiment of the present invention, one or more input devices 160 can be connected to the interface circuit 150 for inputting data and commands to the main processing unit 110. For example, the input device 160 may include a keyboard, a mouse, a touch screen, a trackpad, a trackball, an isopoint, a voice recognition system, and the like.

  Although the scope of the present invention is not limited thereto, the output device 170 can be operatively connected to the main processing unit 110 via one or more interface circuits 160, and if desired, one or more. Other displays, printers, speakers, and / or other output devices. For example, one of the output devices may be a display. The display may be a CRT (Cathode Ray Tube), LCD (Liquid Crystal Display) or any other type of display.

  Although the scope of the present invention is not limited to this, the computer system 100 may include one or more storage apparatuses 180. For example, computer system 100 may include one or more hard drives, one or more CD drives, one or more DVD drives, and / or other computer media input / output (I / O) devices, if desired. Also good.

  Although the scope of the present invention is not limited to this, the computer system 100 can exchange data with other devices via a connection with the network 190. The network connection may be any type of network connection such as an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, etc. Network 190 may be any type of network such as the Internet, a telephone network, a cable network, a wireless network, and the like.

  The scope of the present invention is not limited to this embodiment, but in this embodiment of the present invention, the multi-processing unit 130 may include the optimization unit 200. According to an embodiment of the present invention, the optimization unit 200 may execute a process of searching for two or more candidate instructions for tracing. Further, the optimization unit 200 may merge two or more candidate instructions into a SIMD instruction according to the depth of the trace dependency tree. In some embodiments of the present invention, candidate instructions may include similar and / or the same type of operation code included in SIMD instructions. For example, the optimization unit 200 may search for a candidate instruction that performs similar processing based on the depth of dependency of the candidate instruction. According to embodiments of the present invention, optimization unit 200 may merge at least some of the candidate instructions into SIMD instructions if desired. While the scope of the invention is not so limited, it should be understood that the optimization unit 200 can be implemented by software, hardware or any suitable combination of software and hardware. .

  Referring to FIG. 2, a block diagram of the optimization unit 200 of FIG. 1 is shown according to one embodiment of the present invention. Although the scope of the present invention is not limited to this, the optimization unit 200 may include an input trace buffer 210, a sequencer 220, a vectorization unit 230, and an output trace buffer 240. . Although the scope of the present invention is not so limited, in some embodiments of the present invention, the vectorization unit 230 includes a first stage 232, a second stage 234, and a memory 236 such as a cache memory. It may have.

  Although the scope of the present invention is not limited to this, the input trace buffer 210 may accept an instruction trace having an operation code (operation) code. In some embodiments of the present invention, the sequencer 220 may receive instructions from the input trace buffer 210 and provide operation codes and / or instruction traces (such as sequences) to the vectorization unit 230. For example, the instruction may have at least two types of processing such as memory processing such as LOAD and STORE and arithmetic processing such as ADD, SUBTRACT, MULT, SHIFT, and AND. Furthermore, the instruction may include an input value and an output value such as a register and a constant.

  According to an embodiment of the present invention, vectorization unit 230 may receive a trace from sequencer 220 and retrieve candidate instructions according to trace dependencies. In some embodiments of the present invention, the first stage 232 processes opcode instructions received from the sequencer 220. For example, trace instructions and / or opcodes may be converted to SSA (Single Static Assignment) format. In SSA format, registers can only be written to the trace once, and the rest of the processing may introduce “virtual” register names to satisfy the SSA condition. A program code such as a program code described by a conventional ISA (Instruction Set Architecture) provides two source registers having the same register and the same name, although the scope of the present invention is not limited thereto. Might do.

  Although the scope of the present invention is not limited to this, the first stage 232 may search for candidates for vectorization by placing instructions in a dependency tree.

  Referring to FIG. 3, an exemplary dependency tree 300 useful for describing a method for generating SIMD instructions according to one embodiment of the present invention is shown. Although the scope of the present invention is not so limited, the dependency tree 300 may include instructions of different heights. Although the scope of the present invention is not so limited, the levels of the dependency tree 300 may include instructions of the same height. The first level 310 may include instructions 312 and 314, the second level 320 may include instructions 322, the third level 330 may include instructions 332 and 334, and the fourth level 340 may include instructions 342. Further, the depth of the dependency tree 300 is calculated according to the distance from the initial height 310 to the final height 340 of the dependency tree 300 (eg, the distance may be indicated by an arrow between levels). May be.

  Referring to FIG. 2, although the scope of the present invention is not limited to this, the first stage 232 stores candidate instructions for vectorization in the memory 236. According to embodiments of the present invention, the second stage 234 may retrieve similar opcodes having the same or similar levels from the memory 236 and generate SIMD instructions. Further, the second stage 232 may replace the original trace instruction with the SIMD instruction, and may store the SIMD instruction in the output trace buffer 240.

  Although the scope of the present invention is not limited to this, the processing of the first stage 232 and the second stage of the optimization unit 200 can be described by a pseudo code algorithm simulating the C language as an example.

  Although the scope of the present invention is not limited to this, the first part of the pseudo code algorithm simulating C language defines constants, variable structures, and the like.

  For example, the maximum number of instructions for tracing is

として定義される。

Is defined as

  The maximum number of instructions source is

として定義される。

Is defined as

  The maximum number of instruction destinations is

として定義される。

Is defined as

  Trace range and internal buffer size are

として定義される。

Is defined as

  According to a pseudo-code algorithm simulating C language, the instruction structure may have a Boolean variable, a destination register, an opcode, and a source register that indicate whether the instruction is suitable for vectorization. This instruction structure is

として定義される。

Is defined as

  According to a pseudo-code algorithm that mimics the C language, a trace is defined as a sequence of at most MAX_TRACE_SIZE instructions represented by a vector of MAX_TRACE_SIZE entries. In addition, two dimensions (2D)) trace dependent bitmaps can be used to show the validity of the instructions in the trace. If the actual number of instructions in the trace may be INITIAL_TRACE_SIZE, only the first INITIAL_TRACE_SIZE entry may be valid.

Ｃ言語を模した擬似コードアルゴリズムによると、メモリ２３６に格納されるＳＩＭＤマトリックスは、オペレーションコードを有し、Ｍ個のオペコード位置のＮ本のラインを保持するかもしれない（例えば、合計でＮ^ｘＭ^ｘｌｏｇ（ＭＡＸ＿ＴＲＡＣＥ＿ＳＩＺＥ）ビットなど）。

According to a pseudo-code algorithm that mimics the C language, the SIMD matrix stored in the memory 236 has an operation code and may hold N lines of M opcode positions (eg, a total of N ^x M ^x log (MAX_TRACE_SIZE) bit, etc.).

本発明の範囲はこれに限定されるものではないが、本実施例のアルゴリズムでは、最適化ユニット２３０の第１ステージ２３２は、昇順にトレースの命令を繰り返すことによってトレースの候補命令を検索する。第１ステージ２３２は、リネーミング処理中に構成されるトレース［ｉ］のすべてのプレデセッサ（ｐｒｅｄｅｃｅｓｓｏｒ）を比較する。さらに、第１ステージ２３２は、トレース［ｉ］の依存性の高さ（レベルなど）と、それの可能性のある最先のスケジューリング位置を計算することによって、依存性ツリー（依存性ツリー３００など）における命令の高さ（レベルなど）をタグ付けするようにしてもよい。

Although the scope of the present invention is not limited to this, in the algorithm of this embodiment, the first stage 232 of the optimization unit 230 searches for trace candidate instructions by repeating the trace instructions in ascending order. The first stage 232 compares all predecessors of trace [i] configured during the renaming process. Further, the first stage 232 calculates a dependency tree (such as the dependency tree 300) by calculating the high dependency (level, etc.) of the trace [i] and the earliest possible scheduling position. ) May be tagged with the height (level, etc.) of the instruction.

本発明の範囲はこれに限定されるものではないが、本例のＣ言語を模した擬似コードアルゴリズムでは、第２ステージ２３４は、ベクトル化に適した命令（マトリックスＳＩＭＤなど）をメモリ２３６から検索する。例えば、適切な命令は、同じ依存性ツリーの高さ（レベルなど）におけるより以前の命令トレース［ｊ］であるかもしれない。さらに、第２ステージ２３６は、ＳＩＭＤ命令を生成し、以下に示すように、元の命令をＳＩＭＤ命令と置換するかもしれない。

Although the scope of the present invention is not limited to this, in the pseudo code algorithm simulating the C language in this example, the second stage 234 searches the memory 236 for instructions (such as matrix SIMD) suitable for vectorization. To do. For example, a suitable instruction may be an earlier instruction trace [j] at the same dependency tree height (level, etc.). Further, the second stage 236 may generate a SIMD instruction and replace the original instruction with a SIMD instruction, as shown below.

本発明の一部の実施例によると、最適化ユニット２００は、メモリにアクセスする２つの命令が、連続するメモリアドレスにアクセスする場合、単一のＳＩＭＤ命令に合成されるというルールに従って、ＳＩＭＤ命令を生成するようにしてもよい。すなわち、これら２つの命令によってアクセスされるデータが（少なくともバーチャルメモリ空間において）隣接することは、それらのメモリアドレスと対応するデータ長から計算することが可能である。例えば、以下の命令を含むトレースでは、すなわち、
１．ＥＳＰ＋４から４バイトをＬＯＡＤする。
２．ＥＳＰ＋１２から４バイトをＬＯＡＤする。
３．ＥＳＰ＋８から４バイトをＬＯＡＤする。
では、命令は、所望される場合には、単一のＳＩＭＤ命令である「ＥＳＰ＋４から１２バイトをＬＯＡＤする」に合成されるかもしれない。

According to some embodiments of the present invention, the optimization unit 200 follows the rule that two instructions accessing a memory are combined into a single SIMD instruction when accessing consecutive memory addresses. May be generated. That is, the fact that the data accessed by these two instructions is adjacent (at least in the virtual memory space) can be calculated from their memory addresses and the corresponding data length. For example, in a trace that includes the following instructions:
1. LOAD 4 bytes from ESP + 4.
2. LOAD 4 bytes from ESP + 12.
3. LOAD 4 bytes from ESP + 8.
Then, if desired, the instruction may be combined into a single SIMD instruction “LOAD 12 bytes from ESP + 4” if desired.

  Referring to FIG. 4, a table 400 is shown. Although the scope of the present invention is not limited thereto, the table 400 is provided by a level column indicating the level of the instruction in the dependency tree (such as the dependency tree 300), the input trace buffer 210, and the sequencer 220. The original trace column indicating the original instruction to be output and the trace after vectorization indicating the instruction in the output trace buffer 240 are included. The rows of the table 400 may indicate the level of the instruction, the original instruction, and the instruction after vectorization.

  Although the scope of the present invention is not so limited, the optimization unit 200 may tag the depth of the trace dependency graph (such as the height of the trace instruction). Further, for example, according to the table 400, the optimization unit 200 includes instructions “EAX ← LOAD (ESP, 4)” and “EBX ← LOAD (ESP, ESP,) at the same level (level 2 etc.) as the candidates for vectorization. 8) may be specified, and if desired, these instructions may be combined into SIMD instructions “EAX, EBX ← SIMD_LOAD (ESP, 4)”. Although the scope of the present invention is not limited to this, the optimization unit 200 is based on a common process (such as LOAD) and is at the same depth (such as height) of the trace dependency graph 2. Two instructions are combined into a single SIMD instruction (such as SIMD_LOAD) if all their non-constant sources (such as registers) are similar and / or if the constant or direct sources are different A SIMD instruction may be generated by following the rules.

  Referring to FIG. 5, a table 500 according to another embodiment of the present invention is shown. Although the scope of the present invention is not so limited, the table 500 is provided by a level column indicating the level of the original instruction in the dependency tree (such as the dependency tree 300), and the input trace buffer 210 and sequencer 220. Of the original trace column indicating the original instruction to be processed, a level column indicating the level of the instruction after the basic conversion such as SSA, a column indicating the instruction after the conversion, and the trace after the vectorization in the output trace buffer 240 And a column indicating an instruction. The rows of the table 500 may indicate the instruction level, the original instruction level of the instruction after basic conversion, the instruction after basic conversion, and the instruction after vectorization.

Although the scope of the present invention is not so limited, according to the example table 500, the optimization unit 200 tags the height of the original instruction in the trace. The optimization unit 200 may convert the trace instructions into SSA format. The optimization unit 200 may convert the instructions of the trace by utilizing that the trace is converted to SSA format. The optimization unit 200 is
For example,

などのベクトル化のための候補命令と同一レベルの変換された命令をタグ付けし、それらをＳＩＭＤ命令

Tag the converted instructions at the same level as the candidate instructions for vectorization, etc. and SIMD them

にそれぞれ合成するようにしてもよい。

May be combined respectively.

  While the features of the invention have been illustrated and described herein, many modifications, substitutions, changes and equivalents will occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

100 Computer System 110 Main Processing Unit 120 Power Supply 130 Multi-Processing Unit 140 Storage Device

Claims (18)

When two or more instructions having a common operation code of the trace are searched and the two or more instructions have the same level in the trace dependency tree, the two or more instructions are converted into one SIMD (Single Instruction Multiple Data). An apparatus having an optimization unit that merges into instructions,
The trace dependency tree has instructions at multiple levels, each level having the same height instruction;
The trace command is stored in a memory. The apparatus of claim 1, comprising:
The common operation code comprises a memory operation code or an arithmetic operation code. The apparatus of claim 1, comprising:
The optimization unit is
A first stage that retrieves the two or more instructions from a trace of instructions received from a sequencer by placing the two or more instructions in the trace dependency tree;
A cache memory for storing the instructions in the trace dependency tree;
A second stage for retrieving the two or more instructions in the cache memory to generate the one SIMD instruction;
A device characterized by comprising: The apparatus of claim 1, comprising:
The apparatus is characterized in that the optimization unit is capable of combining the two or more instructions for accessing consecutive memory addresses into the one SIMD instruction. The apparatus of claim 1, comprising:
The optimization unit is capable of converting an input instruction into an SSA (Single Static Assignment) format. Retrieving two or more instructions having a common operation code in the trace;
Merging the two or more instructions into a single instruction multiple data (SIMD) instruction if the two or more instructions have the same level in a trace dependency tree;
A method comprising:
The method of claim 1, wherein the trace dependency tree has a plurality of levels, each level having the same height instruction. The method of claim 6, comprising:
A method comprising the step of selecting the common operation code comprised of a memory processing operation code or an arithmetic operation code. The method of claim 6, comprising:
A method comprising combining the two or more instructions that access consecutive memory addresses into the one SIMD instruction. The method of claim 6, comprising:
The method of merging comprises converting the input instruction of the trace into an SSA (Single Static Assignment) format. With bus,
A storage device connected to the bus;
When two or more instructions having a common operation code of the trace are searched and the two or more instructions have the same level in the trace dependency tree, the two or more instructions are converted into one SIMD (Single Instruction Multiple Data). A processor having an optimization unit that merges into the instructions;
A system comprising:
The trace dependency tree has instructions at multiple levels, each level having the same height instruction;
The trace command is stored in the storage device. The system of claim 10, wherein
The common operation code includes a memory operation code or an arithmetic operation code. The system of claim 10, wherein
The optimization unit is
A first stage that retrieves the two or more instructions from a trace of instructions received from a sequencer by placing the two or more instructions in the trace dependency tree;
A cache memory for storing the instructions in the trace dependency tree;
A second stage for retrieving the two or more instructions in the cache memory to generate the one SIMD instruction;
The system characterized by having. The system of claim 10, wherein
The system is characterized in that the optimization unit is capable of combining the two or more instructions that access consecutive memory addresses into the one SIMD instruction. The system of claim 10, wherein
The optimization unit is capable of converting an input instruction into an SSA (Single Static Assignment) format. Retrieving two or more instructions having a common operation code in the trace;
Merging the two or more instructions into a single instruction multiple data (SIMD) instruction if the two or more instructions have the same level in a trace dependency tree;
A program for causing a computer to execute
The trace dependency tree has a plurality of levels, each level having an instruction having the same height. The program according to claim 15, wherein
A program for causing the computer to execute the step of selecting the common operation code composed of a memory processing operation code or an arithmetic operation code. The program according to claim 15, wherein
A program for causing the computer to execute a step of combining the two or more instructions for accessing consecutive memory addresses into the one SIMD instruction. The program according to claim 15, wherein
A program that causes the computer to execute a step of converting an input instruction into an SSA (Single Static Assignment) format.

Images