JP2011164758A - Compiler for vliw type processor, and system and method for developing program for vliw type processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a development system capable of easily developing a program for a VLIW type processor that can efficiently perform power control for setting a computing unit which is not continuously used to a low power consumption mode. <P>SOLUTION: The development system for the VLIW type processor includes a plurality of slots 35A, 35B respectively including a plurality of computing units 36AA, 36AB, 36AC, 36BA, 36BB, 36BC and capable of setting at least a part of the computing units to the low power consumption mode. The system includes: a compiler 21 for the VLIW type processor; a computing unit use information generation part 38 for generating the use information of the computing unit to be used for executing a program outputted from the compiler 21; and a computing unit use information output part 72 for generating and outputting a power control compilation option based on the use information. The compiler 21 includes an interface to which the power control compilation option for instructing a change in the computing units to be used for respective slots is inputted. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compiler for a VLIW processor, a program development system for a VLIW processor, and a program development method for a VLIW processor.

  In recent years, with the expansion of the mobile device market, there has been a demand for a low power consumption processor system for mobile devices that can extend the operating time of the battery. In addition, even in high-performance servers used to provide services on the Internet, the power of the server itself and the power required for temperature management of the room where the server is installed are on the rise. It is requested. As a method for satisfying such a requirement, a method is known in which the inside of a processor system is divided into a plurality of domains, at least a part of the domains can be set to a low power consumption mode, and power control is performed for each domain.

  For example, a multiprocessor system includes a plurality of processors, and processing is distributed among the plurality of processors. In such a configuration, the instruction execution state is monitored by the instruction execution control unit in each of the plurality of processors. When the instruction idle counter detects a continuous stop state for a predetermined time, the clock distribution control unit stops the clock supply to the processor in which the stop state is detected. Thereby, the power consumption of the processor whose clock supply is stopped can be reduced.

  As a technique for improving the performance of a processor, a VLIW (Very Long Instruction Word set) type processor is known. The VLIW processor has a large number of instruction input terminals and can accept a plurality of instructions simultaneously. The VLIW processor has a plurality of slots for executing a plurality of instructions received simultaneously in parallel. Each slot includes a plurality of computing units. For example, a VLIW type processor that can accept an instruction having an instruction length of 32 bits and 8 instructions simultaneously has been put into practical use.

  When a program is executed by a VLIW type processor, it is difficult to sufficiently improve the processing efficiency only by inputting a normal processor program in parallel. Therefore, an execution format program is created by performing debugging and performance tuning so that instructions can be efficiently executed in each slot according to the contents of the program. This debugging and performance tuning is performed based on program source code and compile options using a VLIW processor program development system including a VLIW processor compiler.

  The program development system for a VLIW processor is realized by software in a computer. FIG. 1 is a diagram showing a hardware configuration of a widely known computer. As shown in FIG. 1, the computer includes a CPU 11, a memory 12, a storage device 13, a display device 14, an input device 15, a drive device 16 that drives a disk device 17 that is an external memory, and a bus 18. . A description of the computer is omitted.

  FIG. 2 is a block diagram showing a configuration of a program development system for a VLIW processor.

  As shown in FIG. 2, the VLIW processor program development system 20 includes a VLIW processor compiler 21, a program source code storage unit 22, a normal compile option storage unit 23, and an executable program storage unit 24. Prepare. The execution format program stored in the execution format program storage unit 24 is executed by a real VLIW processor 31 or a virtual VLIW processor 31 realized by software using an instruction level simulator. Here, the real or virtual VLIW processor 31 will be described as being included in the development system 20.

  The VLIW processor 31 includes a fetch unit 32 that fetches an instruction, a decode unit 33 that decodes an instruction, an execution unit 34 that executes an instruction, and a power control unit 37. The execution unit 34 includes a plurality of slots. As described above, the VLIW processor 31 having 8 slots and capable of accepting 8 instructions at any time is also realized. Here, the VLIW processor having two slots of the first slot 35A and the second slot 35B is realized. The following description is given by taking 31 as an example. The first slot 35A includes a calculator A36AA, a calculator B36AB, and a calculator C36AC. The second slot 35B includes a computing unit A36BA, a computing unit B36BB, and a computing unit C36BC. The configuration related to the arithmetic unit in each slot has various modifications, and the number and type of arithmetic units included in each slot can be the same or different. For example, the first slot includes five arithmetic units, the second slot includes three arithmetic units, and the three arithmetic units can be shared. In addition, when eight slots are provided, four slots are used for integer arithmetic, the remaining four slots are used for floating point arithmetic, and the four slots for integer arithmetic have the same configuration, and floating point arithmetic is provided. The four slots may be configured to have the same configuration. Here, the following description will be given on the assumption that the configurations of the arithmetic units of the first slot 35A and the second slot 35B are the same. Accordingly, the arithmetic units A36AA and A36BA have the same configuration, the arithmetic units B36AB and B36BB have the same configuration, and the arithmetic units C36AC and C36BC have the same configuration.

  FIG. 3 is a flowchart showing an execution format program creation process in the VLIW processor program development system.

  As shown in FIG. 3, the compiler 21 creates an executable program by creating an executable program from the program source code stored in the program source code storage unit 22 and the normal compile option stored in the normal compile option storage unit 23. Store in the program storage unit 24. The compiler 21 executes a lexical analysis process 41 of a program source code, a syntax analysis process 42, a semantic analysis process 43, a code optimization process 44, and a code generation process 45 while referring to a normal compile option. To create an executable program.

  FIG. 4 is a flowchart showing a program development process in the VLIW processor program development system. As shown in FIG. 4, the compiler 21 repeats the debugging process 51 and the performance tuning process 52 to create an optimal executable program.

  Even when a VLIW type processor is used, the above-mentioned method of performing power control for each domain is applied, and a computing unit in which a continuous stop state for a certain time is detected is set to a low power consumption mode, whereby the VLIW type processor is used. It is conceivable to reduce the power consumption of the processor. The power control unit 37 provided in the VLIW processor 31 of FIG. 2 controls the computing unit in which a continuous stop state for a certain period of time is detected to enter the low power consumption mode to reduce power consumption.

  When such power control is performed, the power consumption can be further reduced by increasing the number of arithmetic units to be set in the low power consumption mode and the period in which the arithmetic units are in the low power consumption mode.

  However, VLIW processor compilers used so far have been aimed at improving processing efficiency and increasing processing speed, and have generated executable programs without considering power control. Therefore, the unused time of the computing units in each slot is short, and the number of computing units that are stopped for a certain period of time is small. Therefore, the number of computing units that are set to the low power consumption mode and the computing units are set to the low power consumption mode. I could not increase the period. Therefore, even when the above power control is applied to the VLIW processor, the power consumption of the VLIW processor cannot be sufficiently reduced.

  In addition, the VLIW processor compilers used so far perform complex processing to achieve high processing efficiency for program content analysis, etc., so that users can change slots and calculators. Was not made.

JP 2000-181881 A JP 2000-112559 A

http://img.jp.fujitsu.com/download/jp/jmag/vol155-6/paper04.pdf

  The embodiment describes a program development system that can easily develop a program for a VLIW processor that can efficiently perform power control for setting a computing unit that is not continuously used in the VLIW processor to a low power consumption mode.

  A first aspect of the embodiment is a VLIW processor program development system that includes a plurality of slots each having a plurality of computing units, and at least a part of the plurality of computing units can be set in a low power consumption mode. . The VLIW processor development system includes a VLIW processor compiler, a calculator usage information generator that generates calculator usage information used when executing a program output by the compiler, and power control based on the usage information. A computing unit usage information output unit that outputs computing unit usage information for supporting generation of compile options, and the VLIW processor compiler has a power control compile option that instructs a change of a computing unit used in each slot. An input interface is provided.

  A second aspect of the embodiment is a method for developing a program for a VLIW processor that includes a plurality of slots each having a plurality of computing units, and at least a part of the plurality of computing units can be set in a low power consumption mode. It is. This VLIW processor program development method uses a VLIW processor compiler to create a pre-power tuning program by performing debugging and performance tuning based on the program source code and compile options. It is characterized in that usage information of a computing unit to be used at the time of execution is generated, and the computing unit used in each slot is changed from the usage information so that the same computing unit is not used for a long time.

  According to the embodiment, when a program is executed using a VLIW processor, the number of arithmetic units that can be set in the low power consumption mode and the period during which the arithmetic unit is set in the low power consumption mode can be increased. A formal program can be created, and power consumption when a VLIW processor is used can be reduced.

  Further, according to the embodiment, it is possible to easily create an execution format program for such a VLIW type processor.

FIG. 1 is a diagram showing a hardware configuration of a computer in which a program development system for a VLIW processor is realized by software. FIG. 2 is a block diagram showing a configuration of a program development system for a VLIW processor. FIG. 3 is a flowchart showing an execution format program creation process in the VLIW processor program development system. FIG. 4 is a flowchart showing a program development process in the VLIW processor program development system. FIG. 5 is a block diagram showing the configuration of the VLIW processor program development system of the first embodiment. FIG. 6 is a diagram showing the internal configuration of the VLIW processor compiler in the first embodiment. FIG. 7 is a flowchart showing a program development process in the VLIW processor program development system of the first embodiment. FIG. 8 shows a usage example of an arithmetic unit in an execution format program before power tuning and a usage example of an arithmetic unit in an execution format program in which the number of arithmetic units used after power tuning is reduced in the first embodiment. FIG. 9 shows another use example of the arithmetic unit in the execution form program before power tuning and another use example of the arithmetic unit in the execution form program in which the number of use of the arithmetic unit after power tuning is reduced in the first embodiment. Show. FIG. 10 is a block diagram illustrating a configuration of a program development system for a VLIW processor according to the second embodiment. FIG. 11 is a diagram illustrating an internal configuration of a processor according to the second embodiment. FIG. 12 is a diagram illustrating an internal configuration of a calculator usage log generator according to the second embodiment. FIG. 13 is a diagram illustrating a configuration example of a calculator usage log. FIG. 14 is a diagram illustrating an output example of compile option creation support information for power control generated by the power control compile option creation support device in the second embodiment.

  The program development system for the VLIW processor of the first embodiment is realized by software on a computer having a hardware configuration as shown in FIG. 1, and is an executable program of the VLIW processor 31 as shown in FIG. Are created using this development system.

  FIG. 5 is a block diagram showing the configuration of the VLIW processor program development system of the first embodiment.

  As shown in FIG. 5, the VLIW processor program development system 20 of the first embodiment includes a VLIW processor compiler 21, a program source code storage unit 22, a normal compile option storage unit 23, and an executable program storage. Unit 24, a power control compile option storage unit 25, an execution format program storage unit 27 in which the number of calculators used is reduced, a calculator usage information generation unit 28, and a calculator usage information output unit 29. . The program source code storage unit 22, the normal compile option storage unit 23, and the execution format program storage unit 24 have a configuration and functions similar to those shown in FIG. The VLIW processor compiler 21 creates an executable program from the program source code and the normal compile option, and stores the executable program in the executable program storage unit 24, similar to that shown in FIG.

  The VLIW processor compiler 21 includes an interface 26 to which a power control compilation option stored in the power control compilation option storage unit 25 is input. Further, the VLIW processor compiler 21 performs power tuning processing on the execution format program stored in the execution format program storage unit 24 with reference to the compile option for power control. The execution format program with the reduced number of used computing units created as a result of the power tuning process is stored in the execution format program storage unit 27 with the reduced number of used computing units.

  The computing unit usage information generation unit 28 receives information related to the computing unit when the real or virtual VLIW processor 31 executes the program output by the VLIW processor compiler 21 and generates computing unit usage information to be presented to the operator. To do. The computing unit usage information generation unit 28 is realized by software. The computing unit usage information output unit 92 is a part that outputs computing unit usage information for supporting the generation of power control compile options based on the usage information generated by the computing unit usage information generation unit 91 to the operator. This is realized by the driver program.

  FIG. 6 is a diagram showing an internal configuration of the VLIW processor compiler 21 in the first embodiment. As shown in FIG. 3, the VLIW processor compiler 21 refers to the normal compile option while referring to the program source code lexical analysis processing 41, syntax analysis processing 42, semantic analysis processing 43, and code optimization. The execution process 44 and the code generation process 45 are executed to create an executable program.

  Furthermore, the VLIW processor compiler 21 receives a compile option for power control via the interface 26. The compile option for power control is information indicating whether the arithmetic unit in the processor is valid (used) or invalid (not used). Based on this information, the processor arithmetic unit information in the VLIW processor compiler 21 is updated ( Be changed. The processor arithmetic unit information becomes an input of code optimization processing in the compiler, and a program suitable for using an effective (used) arithmetic unit designated by the processor arithmetic unit information is created.

  FIG. 7 is a flowchart showing a program development process in the VLIW processor program development system 20 of the first embodiment. As described with reference to FIG. 4, the debug process 51 and the performance tuning process 52 are performed, and an executable program is created and stored in the executable program storage unit 24. In the first embodiment, the power tuning process 53 is executed on the execution format program stored in the execution format program storage unit 24 with reference to the compile option for power control. In the power tuning process 53, a power measurement process 54, a power control compile option creation process 55, and a process 56 for determining whether to repeat the power measurement process 54 and the power control compile option creation process 55 are performed. Then, at the end of the power tuning process 53, a process 57 for selecting a power control compile option that optimizes performance and power consumption from the investigated information is performed.

  FIG. 8A shows an example of the use of an arithmetic unit in an execution format program before power tuning, which is created at the stage of performance tuning and stored in the execution format program storage unit 24. FIG. 8B shows an execution format program after power tuning generated by performing power tuning processing on the execution format program before power tuning and stored in the execution format program storage unit 24 in which the number of computing units used is reduced. An example of using a computing unit is shown. In other words, FIG. 8A shows an example of the use of an arithmetic unit in an execution format program created by a conventional VLIW processor program development system. FIG. 8B shows an example of the use of an arithmetic unit in an execution format program created by the VLIW processor program development system of the first embodiment. The computing unit usage information generation unit 28 generates computing unit usage information to be presented to the operator based on such usage information of the computing unit.

  As shown in FIG. 8A, in the order of execution steps, instructions that use the arithmetic units A, A, B, and C are executed in the first slot, and arithmetic units B, C, A, and A are executed in the second slot. An instruction using is executed. Accordingly, the three arithmetic units A, B, and C in the first slot and the three arithmetic units A, B, and C in the second slot are used once during the four execution steps.

  In power tuning, focus on the second execution step. In the second execution step, an instruction using the arithmetic unit A is executed in the first slot, and an instruction using the arithmetic unit C is executed in the second slot. Here, as shown in FIG. 8B, in the second execution step, an instruction using the arithmetic unit A is executed in the second slot, and an instruction using the arithmetic unit C is executed in the first slot. Change as follows. Thus, the computing unit C in the second slot is not used once during the four execution steps. Therefore, the computing unit C in the second slot is not used continuously for a long time, and is therefore set in the low power consumption mode. The operator to be used is changed by the operator creating a power control compile option and instructing the compiler 21 via the interface 26.

  FIG. 9A shows another usage example of the arithmetic unit in the execution format program before power tuning, which is created at the stage of performance tuning and stored in the execution format program storage unit 24. FIG. 9B shows an example of the use of an arithmetic unit in an execution format program after power tuning generated by performing power tuning processing on the execution format program before power tuning of FIG.

  As shown in FIG. 9A, in the order of execution steps, instructions that use the arithmetic units A, C, B, and C are executed in the first slot, and the arithmetic units B, C, A, and A are executed in the second slot. An instruction using is executed. In the second execution step, an instruction using the arithmetic unit C is executed in the first slot, and an instruction using the arithmetic unit C is executed in the second slot. In other words, an instruction using the arithmetic unit C is executed in both the first and second slots. Also in this case, attention is paid to the second execution step in the power tuning. As shown in FIG. 9B, the two instructions using the arithmetic unit C executed in the second execution step of FIG. 9A are changed to be executed only in the first slot. As a result of this change, the number of execution steps is increased by 1 compared to the example of FIG. 9A, but the computing unit C in the second slot is not used once during the five execution steps. As described above, it is possible to give priority to the reduction of power consumption within the range where the increase in the number of execution steps (decrease in the execution speed) does not become a problem. In other words, an increase in the number of execution steps and a reduction in power consumption due to the appearance of arithmetic units that are not used continuously for a long time are in a trade-off relationship, and it is desirable to appropriately determine in consideration of performance.

  As described above, in the first embodiment, the operator can change the computing unit to be used by creating a power control compilation option and instructing the compiler 21 via the interface 26. As a result, it is possible to reduce power consumption by causing a computing unit that is not used continuously for a long time and putting the computing unit in a low power consumption mode.

  FIG. 10 is a block diagram illustrating a configuration of a program development system for a VLIW processor according to the second embodiment.

  As shown in FIG. 10, a VLIW processor program development system 70 according to the second embodiment includes a VLIW processor compiler 21, a program source code storage unit 22, a normal compile option storage unit 23, and an executable program storage. Unit 24, power control compile option storage unit 25, execution form program storage unit 27 in which the number of arithmetic units used is reduced, arithmetic unit use log storage unit 71, power control compile option creation support device 72, option A creation support information storage unit 73 and a processor 31 are provided. The VLIW processor compiler 21 includes an interface 26 to which a power control compilation option stored in the power control compilation option storage unit 25 is input.

  In the VLIW processor program development system 70 of the second embodiment, a VLIW processor compiler 21, a program source code storage unit 22, a normal compile option storage unit 23, an execution format program storage unit 24, and a compile option storage unit for power control 25 and the execution format program storage unit 27 in which the number of calculators used is reduced are the same as those in the first embodiment. In other words, the VLIW processor program development system 70 according to the second embodiment includes an arithmetic unit use log storage unit 71, a power control compile option creation support device 72, and an option creation support information storage unit 73, and the processor 31. Is different from the development system 20 of the first embodiment in that it further includes a calculator usage log generator 38. The processor 31 may be real hardware or a virtual VLIW processor realized by software using an instruction level simulator.

  The processor 31 executes the execution format program stored in the execution format program storage unit 24, and the calculator usage log generator 38 outputs the usage status and instruction address of the calculator according to the program for each processor cycle. Here, the usage status and instruction address of the computing unit are referred to as a computing unit usage log. The computing unit usage log output from the processor 31 is stored in the computing unit usage log storage unit 71.

  The power control compile option creation support device 72 receives the calculator usage log stored in the calculator usage log storage unit 71 and generates compile option creation support information for power control indicating the usage status of the calculator. Therefore, in the second embodiment, the power control compile option creation support device 72 corresponds to the computing unit usage information generation unit 28. Compile option creation support information for power control is stored in the option creation support information storage unit 73 and presented to the operator. The operator creates a power control compilation option while referring to power control compilation option creation support information.

  FIG. 11 is a diagram illustrating an internal configuration of the processor 31 according to the second embodiment. The processor 31 in the second embodiment includes a fetch unit 32 that fetches an instruction, a decode unit 33 that decodes an instruction, an execution unit 34 that executes an instruction, a power control unit 37, and an arithmetic unit use log generator 38. . Also in the example illustrated in FIG. 11, the execution unit 34 includes two slots, a first slot 35A and a second slot 35B. The first slot 35A includes a calculator A36AA, a calculator B36AB, and a calculator C36AC. The second slot 35A includes a calculator A36BA, a calculator B36BB, and a calculator C36BC. The configurations related to the computing units of the first slot 35A and the second slot 35B are the same. In other words, the processor 31 according to the second embodiment is different from the first embodiment in that the processor 31 includes a calculator usage log generator 38. The calculator usage log generator 38 is connected to each part of the calculation pipeline of the VLIW processor 31.

  FIG. 12 is a diagram showing an internal configuration of the arithmetic unit use log generator 38 in the second embodiment. The processor 31 includes an arithmetic pipeline 80. The arithmetic pipeline 80 includes a memory access unit 80 and a register access unit 82 in addition to the fetch unit 32, the decode unit 33, and the execution unit 34 described above. The arithmetic unit use log generator 38 receives an instruction address from the fetch unit 32 and holds the address value until an execution phase in the arithmetic pipeline 80, and a decoding unit PC (program counter) 87 and an execution unit PC (program Counter) 88 and a control unit 86. The computing unit usage log generator 38 can receive information related to pipeline operations from the computing pipeline 80 and can output a PC of instructions actually executed by the execution unit.

  Since the arithmetic unit use log generator 38 has such a configuration, among the instructions speculatively input to the pipeline 80 of the processor 31 by the branch prediction mechanism or the like, that is, among the instructions that are not determined to be executed, Instructions that have not been executed by the calculator of the execution unit 34 can be excluded from the log output target, and only the instructions executed by the calculator of the execution unit 34 can be output in a log.

  There are various types of information that can be output by the calculator usage log generator 38. In the second embodiment, a calculator usage log as shown in FIG. 13 is generated and stored in the calculator usage log storage unit 71. As shown in FIG. 13, the calculator usage log includes the calculator used in each slot and its instruction address stored in correspondence with the order of execution steps. In FIG. 13, slots A, B, and C indicate computing units used in each slot, and “0” indicates that no computing unit is used. For example, in the execution step 1, the arithmetic unit B is used in the first slot, the arithmetic unit is not used in the second slot, and the instruction address at this time is 0. In execution step 2, the arithmetic unit A is used in the first slot, and the arithmetic unit B is used in the second slot. The instruction address at this time is 4. Therefore, in execution steps 1 and 2, the instruction address advances by 4. In execution step 3, the arithmetic unit A is used in the first slot, and the arithmetic unit A is also used in the second slot. The instruction address at this time is 12. Accordingly, in execution steps 2 to 3, the instruction address advances by 8.

  FIG. 14 is a diagram illustrating an output example of compile option creation support information for power control generated by the power control compile option creation support device 72 in the second embodiment. In the example shown in FIG. 14, the vertical axis indicates the type of slot and calculator, and the calculator usage count is displayed for each calculator. By displaying the number of times the computing unit is used, it is possible to notify the operator of the computing unit that is used less frequently. The number of times the arithmetic unit is used is useful information for the operator to create the power control compile option. The horizontal axis is the number of execution steps, and the number of steps used by each computing unit is displayed as a horizontal bar graph. If any horizontal bar graph is selected, its address (for example, 100 addresses) is displayed. As a result, the operator can know the address of the portion where the horizontal bar graph is discretely displayed, and can identify the location where the use frequency of the arithmetic unit is low from the program.

  The execution format program creation process in which the number of computing units used in the second embodiment is reduced is performed in the same flow as in the first embodiment shown in FIG. However, since the operator can use the compile option creation support information for power control generated by the power control compile option creation support device 72, the number of repetitions of power measurement and power control compile option creation can be reduced as compared with the first embodiment. It becomes possible.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
A compiler for a VLIW processor having a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode;
It has an interface for inputting power control compile options to instruct the change of the arithmetic unit used in each slot,
A compiler for a VLIW processor, which performs optimization according to a change in use of a specified arithmetic unit.
(Appendix 2)
A system for developing a program for a VLIW processor, comprising a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode;
A compiler for a VLIW processor;
A computing unit usage information generating unit that generates usage information of a computing unit to be used when executing the program output by the compiler;
A computing unit usage information output unit that outputs computing unit usage information for supporting power control compilation option generation based on the usage information;
The VLIW processor compiler is a VLIW processor program development system including an interface to which a power control compile option for instructing a change of an arithmetic unit used in each slot is input.
(Appendix 3)
The VLIW processor program development system according to appendix 2, wherein the computing unit usage information generation unit is the VLIW processor.
(Appendix 4)
The VLIW processor program development system according to appendix 2, wherein the arithmetic unit usage information generation unit is an instruction level simulator that simulates execution of a program in the VLIW processor.
(Appendix 5)
The VLIW according to any one of appendices 2 to 4, wherein the arithmetic unit usage information generation unit generates usage information of the arithmetic unit including an execution step number, an arithmetic unit used in each slot, and an instruction address. Development system for type processor.
(Appendix 6)
The VLIW processor program development system according to any one of appendices 2 to 5, wherein the computing unit usage information output unit displays the number of times the plurality of computing units are used in the plurality of slots.
(Appendix 7)
The VLIW processor program development system according to any one of appendices 2 to 6, wherein the computing unit usage information output unit displays a usage status of the plurality of computing units in the plurality of slots for each execution step.
(Appendix 8)
The VLIW processor program development system according to appendix 7, wherein the arithmetic unit usage information output unit displays an instruction address when an arithmetic unit in use is displayed for each execution step.
(Appendix 9)
The computing unit usage information generation unit identifies an instruction that has been speculatively input to the VLIW type processor but has not been executed,
The VLIW processor program development system according to any one of appendices 2 to 8, wherein the computing unit usage information output unit does not output the instruction that is speculatively input but not executed as the computing unit usage information.
(Appendix 10)
A VLIW processor program development method comprising a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode,
Using a VLIW processor compiler, create a pre-power tuning program by debugging and performance tuning based on the program source code and compile options,
Generate usage information of an arithmetic unit used when executing the program before power tuning,
A method for developing a program for a VLIW processor, characterized in that, based on the usage information, a computing unit used in each slot is changed so that the same computing unit is not used for a long time.

20 Program Development System for VLIW Processor 21 Compiler for VLIW Processor 22 Program Source Code Storage Unit 23 Normal Compile Option Storage Unit 24 Execution Format Program Storage Unit 25 Compile Option Storage Unit for Power Control 26 Interface 27 Number of Units Used is Reduced Execution format program storage unit 28 Calculator usage information generator 29 Calculator usage information output unit

Claims (6)

A compiler for a VLIW processor having a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode;
It has an interface for inputting power control compile options to instruct the change of the arithmetic unit used in each slot,
A compiler for a VLIW processor, which performs optimization according to a change in use of a specified arithmetic unit. A system for developing a program for a VLIW processor, comprising a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode;
A compiler for a VLIW processor;
A computing unit usage information generating unit that generates usage information of a computing unit to be used when executing the program output by the compiler;
A computing unit usage information output unit that outputs computing unit usage information for supporting power control compilation option generation based on the usage information;
The VLIW processor compiler is a VLIW processor program development system including an interface to which a power control compile option for instructing a change of an arithmetic unit used in each slot is input.   3. The VLIW processor program according to claim 2, wherein the computing unit usage information generating unit generates usage information of the computing unit including an execution step number, a computing unit used in each slot, and an instruction address. Development system.   4. The VLIW processor program development system according to claim 2, wherein the computing unit usage information output unit displays the number of times the computing units are used in the plurality of slots. 5.   5. The VLIW processor program development system according to claim 2, wherein the computing unit usage information output unit displays a usage status of the plurality of computing units in the plurality of slots for each execution step. 6. . A VLIW processor program development method comprising a plurality of slots each having a plurality of computing units, wherein at least a part of the plurality of computing units can be set in a low power consumption mode,
Using a VLIW processor compiler, create a pre-power tuning program by debugging and performance tuning based on the program source code and compile options,
Generate usage information of an arithmetic unit used when executing the program before power tuning,
A method for developing a program for a VLIW processor, characterized in that, based on the usage information, a computing unit used in each slot is changed so that the same computing unit is not used for a long time.

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