JP2011151084A - Peeling test device, and peeling test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test method in which a stage where peeling has occurred can be ascertained. <P>SOLUTION: Each of a plurality of peeling reinforcement blocks 2-1, 2-2, 2-3 and 2-4 includes wiring groups formed in a plurality of wiring layers and conductor holes which electrically connect the wiring groups between the plurality of wiring layers. A test circuit 1 includes a plurality of data holding circuits provided corresponding to the plurality of peeling reinforcement blocks, a test signal supply terminal for supplying a test signal to one end of each of the plurality of peeling reinforcement blocks, and a nonvolatile storage circuit connected to the plurality of data holding circuits. Each of the plurality of data holding circuits holds, as a test result, a signal output from the other end of corresponding one of the respective peeling reinforcement blocks in response to the test signal. The nonvolatile storage circuit is connected to the respective data holding circuits so that test result data held in the respective data holding circuits are made to correspond to the respective data holding circuits to be stored. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a peel test apparatus and a peel test method.

  An integrated circuit such as an LSI (Large Scale Integration) is formed on a semiconductor chip. A plurality of wiring layers are formed on the semiconductor chip. The plurality of wiring layers are stacked via an interlayer film. The interlayer film may be peeled off from the underlying film due to various causes. Therefore, a technique for preventing the peeling of the interlayer film is desired.

  As a related technique, there is a semiconductor device described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-165392). This semiconductor device is a semiconductor device in which a plurality of first reinforcing patterns each having a multilayer wiring structure are concentrically formed on the outer periphery of an element region of a semiconductor chip having a multilayer wiring structure. In this semiconductor device, at least the innermost reinforcing pattern is formed in a state where the wiring of each layer and the vias between the layers in the multilayer wiring structure are divided in the length direction. This semiconductor device has a stacked chain structure in which each divided wiring and each via are connected in series so as to form one wiring path three-dimensionally as a whole. A pair of pad electrodes are formed corresponding to both ends of the wiring path of the uppermost layer wiring. By monitoring the electrical connection state between the pair of pad electrodes, it is possible to evaluate whether or not interlayer film peeling has occurred.

  As another related technique, there is a semiconductor integrated circuit described in Patent Document 2 (Japanese Patent Application Laid-Open No. 2005-191083). This semiconductor integrated circuit is connected to an evaluation wiring, one end of the evaluation wiring, an input circuit for writing a predetermined logic level at one end, and the other end of the evaluation wiring, and latches the logic level at the other end. A latch circuit; a first switch circuit for connecting the output of the input circuit to the input of the latch circuit; a second switch circuit for connecting the output of the input circuit to one end of the evaluation wiring; and the other end of the evaluation wiring being a latch circuit A third switch circuit connected to the input of the first and second output circuits for reading out the logic level latched by the latch circuit.

JP2007-165392A JP 2005-191083 A

  The peeling of the interlayer film may occur in the manufacturing process of the integrated circuit, or may occur after the integrated circuit is shipped as a product. Therefore, it is desirable to know at which stage the peeling of the interlayer film has occurred. However, the techniques disclosed in Patent Documents 1 and 2 have a problem that it is only possible to know the presence or absence of peeling during a test, and not to know at which stage peeling has occurred.

  The peel test apparatus according to the present invention includes a plurality of peel reinforcing blocks and a test circuit. Each of the plurality of peeling reinforcing blocks includes a wiring group formed in a plurality of wiring layers and a conductor hole that electrically connects the wiring group between the plurality of wiring layers. The test circuit is provided corresponding to the plurality of peel reinforcing blocks, a plurality of data holding circuits, and a test signal supply end for supplying a test signal to one end of each of the plurality of peel reinforcing blocks, A nonvolatile memory circuit connected to the plurality of data holding circuits. Each of the plurality of data holding circuits holds, as test result data, a signal output in accordance with the test signal from the other end of each corresponding peel reinforcing block. The nonvolatile storage circuit is connected to the data holding circuits so as to store the test result data held in the data holding circuits in association with the data holding circuits.

  According to the present invention, when peeling occurs between the wiring layers in the peel reinforcing block, the one end and the other end of the peel reinforcing block are electrically disconnected. Therefore, it is possible to know the presence or absence of peeling in each peeling reinforcing block using the test result data held in each data holding circuit. In addition, according to the present invention, test result data is stored in a nonvolatile storage circuit. Therefore, by referring to the data stored in the memory circuit, it is possible to confirm at which stage peeling has occurred.

  In the peel test method according to the present invention, a test signal is supplied to one end of each of the plurality of peel reinforcing blocks, and a signal output according to the test signal from the other end of each peel reinforcing block is tested. The step of holding as result data, and the non-volatile storage circuit include the step of storing the test result data in the non-volatile storage circuit in association with each data holding circuit. Each of the separation reinforcing blocks includes a wiring group formed in a plurality of wiring layers and a conductor hole that electrically connects the wiring group between the plurality of wiring layers.

  According to the present invention, it is possible to provide a peeling test apparatus and a peeling test method capable of knowing at which stage peeling has occurred.

It is the schematic which shows the semiconductor chip provided with the peeling test apparatus which concerns on 1st Embodiment. It is a schematic sectional drawing which shows a peeling reinforcement block. It is the schematic which shows the structure of a test circuit. It is a figure which shows the connection relation of a peeling reinforcement block and a scan flip-flop. It is a schematic sectional drawing which shows a peeling reinforcement block when peeling generate | occur | produces. It is a figure which shows the position of the peeling reinforcement block. It is sectional drawing which shows roughly each peeling reinforcement block which concerns on 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic view showing a semiconductor chip 10 provided with a peel test apparatus according to the present embodiment. Although not shown in FIG. 1, the semiconductor chip 10 is provided with a plurality of wiring layers. The plurality of wiring layers are stacked via an interlayer film. As shown in FIG. 1, an LSI internal area 3 (an area where an integrated circuit is formed) is provided in the central portion of the semiconductor chip 10. A plurality of peel reinforcing blocks 2 (2-1 to 2-4) are provided on the outer peripheral portion of the semiconductor chip 10. A test circuit 1 is formed in the LSI internal region 3 as a part of the integrated circuit. The peel test apparatus according to the present embodiment is realized by a test circuit 1 and a plurality of peel reinforcing blocks 2. The plurality of peel reinforcing blocks 2 are connected to the test circuit 1.

  Each peeling reinforcement block 2 is provided in order to prevent peeling of the interlayer film. Each peeling reinforcement block 2 is provided at a corner of the semiconductor chip. FIG. 2 is a schematic cross-sectional view showing each peel reinforcing block 2. As shown in FIG. 2, each separation reinforcing block 2 includes wiring provided in a plurality of wiring layers 4 (4-1 to 4-3) and conductor holes 5 that connect the wirings between the wiring layers. I have. The conductor hole 5 extends so as to penetrate between the uppermost layer 4-1 of the plurality of wiring layers and the lowermost layer 4-2 of the plurality of wiring layers. In this manner, by using a configuration in which wirings provided between a plurality of wiring layers are connected by conductor holes, it is possible to prevent the interlayer film from peeling off.

  The test circuit 1 is provided to test whether or not peeling of the interlayer film occurs in each peeling reinforcing block 2. FIG. 3 is a schematic diagram showing the configuration of the test circuit 1. As shown in FIG. 3, the test circuit 1 includes a plurality of scan flip-flops 6 (6-1 to 6-4), a scan-in terminal SIN, a test signal supply terminal IN, a clock signal supply terminal CLK, a counter circuit 11, In addition, a nonvolatile storage unit 9 is provided.

  The plurality of scan flip-flops 6 (6-1 to 6-4) are provided corresponding to the plurality of separation reinforcing blocks 2 (2-1 to 2-4). Each scan flip-flop 6 has a multiplexer 8 and a flip-flop circuit 7. The input terminal of the flip-flop circuit 7 is connected to the output terminal of the multiplexer 8. The flip-flop circuit 7 is connected to the clock signal supply terminal CLK. A clock signal is supplied to the flip-flop circuit 7 from the clock signal supply terminal CLK. The multiplexer 8 has two input ends, and one input end is connected to the corresponding peel reinforcing block 2. The other input terminal of the multiplexer 8 is connected to the output terminal of the flip-flop circuit 7 included in the upper scan flip-flop 6. However, in the uppermost scan flip-flop 6-1, the other input terminal of the multiplexer 8 is connected to the scan-in terminal SIN. In the lowermost scan flip-flop 6-4, the output terminal of the flip-flop circuit 7 is connected to the storage unit 9.

  The counter circuit 11 is connected to the clock signal supply terminal CLK. The counter circuit 11 is provided in order to be able to identify at which stage the test is performed. The counter circuit 11 has a function of counting the number of times the clock signal is supplied, and notifies the storage unit 9 of the coefficient result.

  Next, the connection relationship between each peeling reinforcing block 2 and each scan flip-flop 6 will be described. FIG. 4 is a diagram showing a connection relationship between each separation reinforcing block 2 and each scan flip-flop 6. As shown in FIG. 4, one end of each peel reinforcing block 2 is connected to a test signal supply terminal IN. The other end of each peel reinforcing block is connected to one input end of the multiplexer 8.

  Next, an operation method of the above-described peel test apparatus will be described.

  First, predetermined data is held in the flip-flop circuit 7 of each scan flip-flop 6. Specifically, the multiplexer 8 of each scan flip-flop 6 outputs a signal supplied from the other input terminal (the input terminal connected to the upper flip-flop circuit 7 or the scan-in terminal SIN). Be controlled. Then, by supplying the clock signal, predetermined data is supplied from the scan-in terminal SIN to the flip-flop circuit 7 of each scan flip-flop 6. As a result, predetermined data is held in the flip-flop circuit 7.

  Next, the multiplexer 8 is controlled so as to output a signal supplied from one input end (input end connected to the corresponding peel reinforcing block 2). Then, a test signal is supplied from the test signal supply terminal IN to each separation reinforcing block 2. Here, when no peeling of the interlayer film occurs in the peeling reinforcing block 2, a test signal is transmitted from each peeling reinforcing block 2 to the flip-flop circuit 7. As a result, the data held in the flip-flop circuit 7 is rewritten to data corresponding to the test signal. On the other hand, as shown in FIG. 5, when an interlayer film peel 12 occurs in the peel reinforcing block 2, the one end and the other end of the peel reinforcing block 2 are electrically disconnected. Therefore, the test signal does not pass through the peel reinforcing block 2. The data held in the flip-flop circuit 7 cannot be rewritten. In addition, the counter circuit 11 notifies the storage unit 9 of the number of times the clock signal is supplied when the test signal is supplied as time data.

  Thereafter, the multiplexer 8 is controlled so as to again output a signal supplied from the other input terminal (an input terminal connected to the upper flip-flop circuit 7 or the scan-in terminal SIN). Then, the data held in each scan flip-flop 6 is read to the storage unit 9 as test result data by the clock signal. In the storage unit 9, test result data is stored in association with data specifying each scan flip-flop 6 (each flip-flop circuit 7). The test result data is also associated with the time data sent from the counter circuit 11 and stored.

  As described above, according to the present embodiment, it is possible to know whether or not peeling has occurred in each peeling reinforcing block 2 by referring to the test result data stored in the storage unit 9. Here, since a plurality of peeling reinforcement blocks 2 are provided, it is possible to specify at which position in the semiconductor chip 10 peeling occurs by specifying the peeling reinforcement block 2 where peeling has occurred. it can.

  If it is simply confirmed whether or not peeling has occurred, a pair of electrode pads is provided on the uppermost wiring of each peeling reinforcing block 2 as described in Patent Document 1 (Japanese Patent Laid-Open No. 2007-165392). It is also conceivable to monitor the electrical connection state between the pair of electrode pads. However, the semiconductor chip is usually used by being sealed with a sealing body. Therefore, after sealing, in order to confirm the presence or absence of peeling, the sealing body must be destroyed to expose the electrode pad. On the other hand, in this embodiment, the test circuit 2 inspects for the presence or absence of peeling. Since the test circuit 2 is formed as a part of the integrated circuit, the test can be performed without opening even after sealing.

  In the present embodiment, test result data is stored in the nonvolatile storage unit 9. Therefore, it is possible not only to confirm the presence / absence of the peeling and the peeling location at the time of performing the test, but also to check the test result data even when time has elapsed since the test was performed. Further, since the test result data is stored in association with the time data, it is possible to confirm at which stage peeling has occurred. For example, when a defect occurs after shipment, it is possible to know whether peeling occurred before shipment or after shipment by reading and checking the test result data in the test conducted before shipment Become.

  In the present embodiment, the case where the plurality of peeling reinforcing blocks 2 are provided at the corners of the outer peripheral portion of the semiconductor chip 2 has been described. However, the positions of the plurality of peel reinforcing blocks 2 are not particularly limited. For example, as shown in FIG. 6, the plurality of peel reinforcing blocks 2 may include blocks provided in places other than the corners in the outer peripheral portion 13.

(Second Embodiment)
Next, the second embodiment will be described. In this embodiment, the structure of each peeling reinforcement block 2 is changed from 1st Embodiment. Since other points can be the same as those in the first embodiment, a detailed description thereof will be omitted.

  FIG. 7 is a cross-sectional view schematically showing each separation reinforcing block 2 in the present embodiment. As shown in FIG. 7, each separation reinforcing block 2 is configured to connect from the α-th wiring layer 4-α to the n-th wiring layer 4-n. Here, the α-th wiring layer 4-α is a layer below the uppermost wiring layer 4-1, and the n-th wiring layer 4-n is a layer above the lowermost wiring layer 4-2. It is. One of the α-th wiring layer 4-α and the n-th wiring layer 4-n may coincide with the uppermost wiring layer 4-1 or the lowermost wiring layer 4-2. That is, the conductor hole 5 is not provided so as to penetrate from the uppermost layer to the lowermost layer, but is provided so as to penetrate a part between the uppermost layer and the lowermost layer.

  By adopting the above-described configuration, it is possible to specify which wiring layer among the plurality of wiring layers 4 is peeled off. Accordingly, it is possible to specify which layer is formed during the manufacturing process in which peeling occurs.

  The present invention has been described using the first embodiment and the second embodiment. These embodiments are not independent from each other, and can be used in combination within a consistent range.

1 Test Circuit 2 Peeling Reinforcement Block 3 LSI Internal Area (Integrated Circuit)
4-1 Wiring layer (top layer)
4-2 Wiring layer (lowermost layer)
4-3 Wiring layer (inside)
4-n n-th wiring layer 4-α-th α-wiring layer 5 conductor hole 6 (6-1 to 6-4) scan flip-flop 7 flip-flop circuit 8 multiplexer 9 storage unit 10 semiconductor chip 11 counter circuit 12 peeling 13 outer peripheral unit

Claims (8)

A plurality of peel reinforcing blocks;
A test circuit;
Comprising
Each of the plurality of peel reinforcing blocks is
A wiring group formed in a plurality of wiring layers;
A conductor hole electrically connecting the wiring group between the plurality of wiring layers;
The test circuit includes:
A plurality of data holding circuits provided corresponding to the plurality of peel reinforcing blocks;
A test signal supply end for supplying a test signal to one end of each of the plurality of peel reinforcing blocks;
A nonvolatile memory circuit connected to the plurality of data holding circuits,
Each of the plurality of data holding circuits holds a signal output according to the test signal from the other end of each corresponding peeling reinforcing block as test result data,
The non-volatile storage circuit is connected to each data holding circuit so as to store the test result data held in each data holding circuit in association with each data holding circuit. . A peel test apparatus according to claim 1,
Furthermore,
The test circuit includes a time data generation circuit that generates time data indicating a time when the test signal is supplied,
The peeling test apparatus, wherein the storage circuit stores the test result data in association with the time data. The peel test apparatus according to claim 1 or 2,
Each data holding circuit includes a flip-flop circuit. A peel test apparatus according to any one of claims 1 to 3,
The plurality of peel reinforcing blocks are peel test devices provided on an outer peripheral portion of a semiconductor chip in which an integrated circuit device is formed at a central portion. A peel test apparatus according to claim 4, wherein
The plurality of peel reinforcing blocks are peel test devices provided at corners of the semiconductor chip. A peel test apparatus according to any one of claims 1 to 5,
The peeling test apparatus is provided so that the conductor hole penetrates between an uppermost layer of the plurality of wiring layers and a lowermost layer of the plurality of wiring layers. A peel test apparatus according to any one of claims 1 to 5,
The peeling test apparatus, wherein the conductor hole is provided so as to penetrate a part of the wiring layers of the plurality of wiring layers. Supplying a test signal to one end of each of the plurality of peel reinforcing blocks;
Holding a signal output in response to the test signal from the other end of each peel reinforcing block as test result data;
The nonvolatile memory circuit stores the test result data in a nonvolatile memory circuit in association with each data holding circuit;
Comprising
Each of the peeling reinforcing blocks is
A wiring group formed in a plurality of wiring layers;
A peeling test method comprising a conductor hole for electrically connecting the wiring group between the plurality of wiring layers.

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